FLASH_CTRL Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.642m	121.693us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.480s	15.524us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.410s	48.830us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.280s	742.385us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.122m	2.744ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	57.720s	5.470ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	21.110s	177.188us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.280s	742.385us	20	20	100.00
		flash_ctrl_csr_aliasing	57.720s	5.470ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.960s	18.443us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.060s	18.630us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.110s	88.512us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.033m	256.714us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.709m	340.359ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.075m	170.196ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.110s	16.075us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.913m	272.684ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.220m	5.850ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.453m	5.001ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.128h	60.653ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.403m	5.727ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.230s	63.834us	39	40	97.50
		flash_ctrl_rw_evict_all_en	33.110s	159.131us	37	40	92.50
		flash_ctrl_re_evict	36.060s	227.178us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.546m	1.986ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.546m	1.986ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	22.460m	35.670ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	35.140s	6.514ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	15.446m	386.089us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	44.585m	7.121ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	19.033m	10.413ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	53.878m	1.017ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.770s	15.356us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.841m	5.354ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.790s	16.194us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.640s	31.197us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	27.879m	1.704ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.688m	19.907ms	50	50	100.00
		flash_ctrl_otp_reset	2.248m	43.504us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.709m	340.359ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.904m	6.720ms	38	40	95.00
		flash_ctrl_intr_wr	1.497m	7.627ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.328m	174.518ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.484m	108.237ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.594m	2.000ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.235m	3.939ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.140s	62.234us	5	5	100.00
		flash_ctrl_ro_derr	3.010m	1.576ms	10	10	100.00
		flash_ctrl_rw_derr	13.278m	6.376ms	7	10	70.00
		flash_ctrl_derr_detect	41.830s	164.309us	0	5	0.00
		flash_ctrl_integrity	11.872m	15.345ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.180s	22.339us	5	5	100.00
		flash_ctrl_ro_serr	2.793m	568.807us	10	10	100.00
		flash_ctrl_rw_serr	11.777m	23.400ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.450m	4.537ms	3	5	60.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.534m	3.490ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.920m	27.806ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.490s	148.096us	1	1	100.00
		flash_ctrl_read_word_sweep	14.240s	25.194us	1	1	100.00
		flash_ctrl_ro	2.574m	2.510ms	19	20	95.00
		flash_ctrl_rw	12.231m	41.261ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	42.790s	646.087us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	22.573m	95.757ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.349m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.370s	150.743us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.400s	14.633us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.820s	66.871us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.820s	66.871us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.410s	48.830us	5	5	100.00
		flash_ctrl_csr_rw	18.280s	742.385us	20	20	100.00
		flash_ctrl_csr_aliasing	57.720s	5.470ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.540s	889.282us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.410s	48.830us	5	5	100.00
		flash_ctrl_csr_rw	18.280s	742.385us	20	20	100.00
		flash_ctrl_csr_aliasing	57.720s	5.470ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.540s	889.282us	20	20	100.00
V2		TOTAL			991	1013	97.83
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.220s	18.874us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.220s	18.874us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.220s	18.874us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.220s	18.874us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.370s	38.415us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.331h	1.152ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.284m	1.597ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.284m	1.597ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.284m	1.597ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.220s	63.117us	3	3	100.00
		flash_ctrl_wr_intg	15.240s	44.593us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.642m	121.693us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.248m	43.504us	80	80	100.00
		flash_ctrl_disable	22.790s	16.194us	50	50	100.00
		flash_ctrl_sec_info_access	1.456m	937.693us	50	50	100.00
		flash_ctrl_connect	16.640s	31.197us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.310s	37.954us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.280s	742.385us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.220s	18.874us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.280s	742.385us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.220s	18.874us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.280s	742.385us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.220s	18.874us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.790s	16.194us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.220s	63.117us	3	3	100.00
		flash_ctrl_access_after_disable	13.910s	21.720us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	29.730s	27.573us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.790s	16.194us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	35.140s	6.514ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.231m	41.261ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.777m	23.400ms	9	10	90.00
		flash_ctrl_rw_derr	13.278m	6.376ms	7	10	70.00
		flash_ctrl_integrity	11.872m	15.345ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.709m	340.359ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.331h	1.152ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.331h	1.152ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.331h	1.152ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.331h	1.152ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.170s	806.325us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.660s	28.399us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	16.140s	60.174us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.331h	1.152ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.331h	1.152ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.331h	1.152ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	46.130s	269.960us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1259	1281	98.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.24	95.70	93.99	98.31	92.52	98.21	96.89	98.09

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 3 failures:
- Test flash_ctrl_serr_counter has 1 failures.
  - 0.flash_ctrl_serr_counter.46451388012342517007613306447872752360168201560906351565265358710865418027331
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest/run.log
```
  Job ID: smart:d095ebfc-e741-4cc9-9dc8-cf2254854bd1
```
- Test flash_ctrl_rw has 2 failures.
  - 16.flash_ctrl_rw.52920933760959711644794192149765438854136209325320944082088689442895525480708
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:2d876381-9a29-4833-a8a3-05768aa972cb
```
  - 19.flash_ctrl_rw.66768994628296839581223942702155179864140384967005934434486203069570095041044
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:54d2feb8-e143-4fc7-b5ac-b15c982b0aa7
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 1.flash_ctrl_rw_serr.102524850427486285090375035021381454745880800676224843514395777784610327598867
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 415064.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 415064.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_serr_counter has 1 failures.
  - 3.flash_ctrl_serr_counter.66390759629080338567322123874910363405943081941036741867401638441579537659555
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest/run.log
```
  UVM_ERROR @ 487136.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 487136.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_ro has 1 failures.
  - 12.flash_ctrl_ro.48874225677240711050340031816912908777149190347814548530879946129746735995825
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 169324.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 169324.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_integrity has 2 failures.

0.flash_ctrl_integrity.100443409880410526565697577338751051256576200032866987798305648056555413218664
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 2975985.2 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (60229530293303179810945 [0xcc10ca4240804c11881] vs 23769243356674658986689 [0x5088884020c0688eac1])
  UVM_INFO @ 2975985.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_integrity.62105642436038143206530980500768778572412082457913586909981477938230606724394
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 4524448.5 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (57866098916288874156569 [0xc40ed7128a206c01219] vs 47228350577959256459801 [0xa0041072020dc000a19])
  UVM_INFO @ 4524448.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_rw_derr has 2 failures.
  - 3.flash_ctrl_rw_derr.3790256253828067973738923168120637503355613564877444296002432197392027249947
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 3053227.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003ca8
  UVM_INFO @ 3053227.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.flash_ctrl_rw_derr.11633726404149836698895676079175263204521912735990271629789231767675704721839
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 621913.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004c10
  UVM_INFO @ 621913.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 19.flash_ctrl_rw_evict_all_en.88535549776811629464878257604007824769282568072308742938834609882462252841585
    Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 11899.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 11899.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.flash_ctrl_rw_evict_all_en.636890906888044252665623666797037407543075927973175362866143639889677962560
    Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 29197.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 29197.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153161) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.38199450057912212217116665826317019107268181510814357997409855452679356868260
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 74751.6 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153161) { a_addr: 'h3a2b4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4d  a_opcode: 'h4  a_user: 'h258aa  d_param: 'h0  d_source: 'h4d  d_data: 'h496206cb  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd69  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 74751.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 1.flash_ctrl_rw_derr.62778643653183661845641221163137192755803558184904753179591795608508723373696
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1930258.0 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (2963194040380194565642 [0xa0a294000d08002e0a] vs 2963194040929950379546 [0xa0a294008d08002e1a])
  UVM_INFO @ 1930258.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157357) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.85637391609859360091480435497428294768196383716936854967871694375555867327284
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 306953.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157357) { a_addr: 'h7e234  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5a  a_opcode: 'h4  a_user: 'h2432a  d_param: 'h0  d_source: 'h5a  d_data: 'h8769fb79  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd57  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 306953.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153843) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.65249129481518730605770890798188154882049197115895326496604085977024374905128
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 164308.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153843) { a_addr: 'h864b8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha9  a_opcode: 'h4  a_user: 'h26aaa  d_param: 'h0  d_source: 'ha9  d_data: 'h35fce5f5  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd0c  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 164308.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153139) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.103315936011182068814500836330576470117433652917540729363774014659675027408441
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 28569.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153139) { a_addr: 'h9e410  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h4  a_user: 'h2662a  d_param: 'h0  d_source: 'h3e  d_data: 'h5de6cdc6  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd44  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 28569.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153517) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.60746197228990010148739708861244369210206170629408070321004558848981468880937
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 26072.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153517) { a_addr: 'h72c48  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h85  a_opcode: 'h4  a_user: 'h248aa  d_param: 'h0  d_source: 'h85  d_data: 'h8690f950  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd4b  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 26072.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 4.flash_ctrl_rw_evict.86483727535027345745534241303176831788685129571831350545999809145291314928077
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 32942.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 32942.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *b10960a_b0850939:ffffffff_b* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 12.flash_ctrl_intr_rd.95003210285806173019709264234833810400526274532053783564635656935349397955565
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 298379.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    7b10960a_b0850939:ffffffff_b0850939  mismatch!!
  UVM_INFO @ 298379.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 31.flash_ctrl_rw_evict_all_en.26045540170047697071596006270945466680180706063224811370901810763757628538458
    Line 297, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_FATAL @ 12032.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001ed0
  UVM_INFO @ 12032.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c603e92_7e512715:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 35.flash_ctrl_intr_rd.92575218280856140105068353113732470099367255832841427063116319032614815879615
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 806869.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    7c603e92_7e512715:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 806869.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```