FLASH_CTRL Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.931m	703.961us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.650s	16.881us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.200s	46.035us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.270s	178.484us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.537m	11.887ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.149m	7.103ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.980s	467.995us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.270s	178.484us	20	20	100.00
		flash_ctrl_csr_aliasing	1.149m	7.103ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.950s	16.035us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.680s	84.341us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.160s	107.637us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.487m	51.741us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.075m	275.187ms	2	3	66.67
		flash_ctrl_hw_rma_reset	19.130m	350.284ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.870s	20.242us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.078m	237.833ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.193m	5.618ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.354m	2.422ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.153h	50.873ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.972m	1.385ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	31.650s	41.422us	37	40	92.50
		flash_ctrl_rw_evict_all_en	32.070s	28.910us	40	40	100.00
		flash_ctrl_re_evict	35.580s	251.438us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.290m	2.125ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.290m	2.125ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.786m	78.181ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.480s	595.791us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.010m	982.889us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.854m	25.589ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.517m	2.853ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	42.718m	10.657ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.710s	21.723us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.141m	3.749ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.400s	14.076us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.480s	22.640us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	25.829m	453.024us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.599m	3.206ms	50	50	100.00
		flash_ctrl_otp_reset	2.252m	41.389us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.075m	275.187ms	2	3	66.67
V2	interrupts	flash_ctrl_intr_rd	4.187m	2.353ms	38	40	95.00
		flash_ctrl_intr_wr	1.267m	4.827ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	9.401m	50.057ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.938m	154.538ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.498m	2.964ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.244m	818.842us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.660s	64.524us	5	5	100.00
		flash_ctrl_ro_derr	2.807m	655.087us	10	10	100.00
		flash_ctrl_rw_derr	13.072m	40.319ms	9	10	90.00
		flash_ctrl_derr_detect	42.910s	49.030us	0	5	0.00
		flash_ctrl_integrity	10.947m	4.691ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.190s	23.988us	5	5	100.00
		flash_ctrl_ro_serr	2.677m	12.110ms	10	10	100.00
		flash_ctrl_rw_serr	11.319m	22.047ms	5	10	50.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.602m	3.123ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.605m	1.844ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.814m	33.285ms	19	20	95.00
		flash_ctrl_write_word_sweep	15.490s	38.274us	1	1	100.00
		flash_ctrl_read_word_sweep	14.010s	25.608us	1	1	100.00
		flash_ctrl_ro	2.158m	516.748us	20	20	100.00
		flash_ctrl_rw	11.723m	17.231ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	41.560s	726.806us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.631m	178.953ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.928m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.410s	133.181us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.690s	36.733us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.580s	234.577us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.580s	234.577us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.200s	46.035us	5	5	100.00
		flash_ctrl_csr_rw	18.270s	178.484us	20	20	100.00
		flash_ctrl_csr_aliasing	1.149m	7.103ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.610s	1.474ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.200s	46.035us	5	5	100.00
		flash_ctrl_csr_rw	18.270s	178.484us	20	20	100.00
		flash_ctrl_csr_aliasing	1.149m	7.103ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.610s	1.474ms	20	20	100.00
V2		TOTAL			990	1013	97.73
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.170s	14.737us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.170s	14.737us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.170s	14.737us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.170s	14.737us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.470s	58.725us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.320h	992.654us	5	5	100.00
		flash_ctrl_tl_intg_err	15.115m	2.940ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.115m	2.940ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.115m	2.940ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.940s	63.156us	3	3	100.00
		flash_ctrl_wr_intg	15.190s	45.162us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.931m	703.961us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.252m	41.389us	80	80	100.00
		flash_ctrl_disable	22.400s	14.076us	50	50	100.00
		flash_ctrl_sec_info_access	1.591m	6.912ms	50	50	100.00
		flash_ctrl_connect	16.480s	22.640us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.080s	22.856us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.270s	178.484us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.170s	14.737us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.270s	178.484us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.170s	14.737us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.270s	178.484us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.170s	14.737us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.400s	14.076us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.940s	63.156us	3	3	100.00
		flash_ctrl_access_after_disable	14.020s	13.573us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.070s	27.537us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.400s	14.076us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.480s	595.791us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.723m	17.231ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.319m	22.047ms	5	10	50.00
		flash_ctrl_rw_derr	13.072m	40.319ms	9	10	90.00
		flash_ctrl_integrity	10.947m	4.691ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.075m	275.187ms	2	3	66.67
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.320h	992.654us	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.320h	992.654us	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.320h	992.654us	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.320h	992.654us	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.840s	885.845us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.150s	16.791us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.310s	4.615us	3	5	60.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.320h	992.654us	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.320h	992.654us	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.320h	992.654us	5	5	100.00
V2S		TOTAL			145	147	98.64
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.950s	63.233us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1256	1281	98.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.71	94.08	98.31	91.16	98.19	96.99	98.24

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 4 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 2.flash_ctrl_rw_serr.38334887937332056069857188574348159179424385371533986059901475879871217820907
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:1b841852-1f41-46c3-bf43-5ef9a41cd4e9
```
  - 3.flash_ctrl_rw_serr.374670407283591918592043559125130946267215262315017120044935026589567029487
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:d0503e9a-73d2-4993-9487-6dd7d38a79f1
```
- Test flash_ctrl_rw has 1 failures.
  - 6.flash_ctrl_rw.46112618144503192981475888528158581474369316860016928152034736407749221541329
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:27f9ea6b-d1e8-4e24-89df-31fd92180500
```
- Test flash_ctrl_wo has 1 failures.
  - 12.flash_ctrl_wo.61537418250511513111691891570612097054009112093110925062365295624989458825146
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:47adfe56-0cd8-4db6-814c-70e9da791567
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 0.flash_ctrl_rw_derr.16533432767607817594864877795859676923490759080074397216695713471134431739612
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 11222598.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004400
  UVM_INFO @ 11222598.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_integrity has 2 failures.
  - 0.flash_ctrl_integrity.52996713432467971105987844011507145080936296876459969840085821242706810777674
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 15165844.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004800
  UVM_INFO @ 15165844.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_integrity.100321375101385457257720786817526452928339547290033588514799401244579372189902
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 634408.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003810
  UVM_INFO @ 634408.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict has 2 failures.
  - 0.flash_ctrl_rw_evict.20181720366604676134878893330388450142193120625470548245236260488869179830618
    Line 300, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 13469.5 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 13469.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.flash_ctrl_rw_evict.97462197464519169199374526421008982613280790006013115487192290382541524547491
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 29008.2 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 29008.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 2 failures:
- Test flash_ctrl_phy_ack_consistency has 2 failures.
  - 0.flash_ctrl_phy_ack_consistency.11658936038341422968876285106187051932631762495569301950846702379858631045381
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 65827.7 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x12)
  UVM_INFO @ 65827.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_phy_ack_consistency.113937565785269832985605194872680264044368573567219312039767466018807707237768
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 4614.7 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x8)
  UVM_INFO @ 4614.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 5.flash_ctrl_rw_serr.44342341123892026362417342274338864303736194320354844261002568505590258838562
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 1217428.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1217428.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.flash_ctrl_rw_serr.81497598928956281708159001348206019632999768307621347306615179448148921096309
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 820149.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 820149.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '$fell(src_ack_o)' has 1 failures:
- Test flash_ctrl_hw_rma has 1 failures.
  - 0.flash_ctrl_hw_rma.109850563708415479984656379802926042560287232418016468964179034409970003873303
    Line 395, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest/run.log
```
      Offending '$fell(src_ack_o)'
  UVM_ERROR @ 598428862.1 ns: (prim_sync_reqack.sv:349) [ASSERT FAILED] SyncReqAckHoldReq
  UVM_INFO @ 598428862.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153443) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.110954795762520919687943749751861469102377508034122927030218196189380910112058
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 40923.5 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153443) { a_addr: 'hc0d0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hbe  a_opcode: 'h4  a_user: 'h2472a  d_param: 'h0  d_source: 'hbe  d_data: 'hf3f1d424  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd27  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 40923.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154436) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.79232228202744534925600254332836775006496913934912520756470252884440039787004
    Line 307, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 45352.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154436) { a_addr: 'hf1c58  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h2622a  d_param: 'h0  d_source: 'h38  d_data: 'h965bc50b  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd1f  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 45352.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 1.flash_ctrl_oversize_error.38948285129128275982455659438558479410815329010625444513898015429231119496361
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 799737.7 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 799737.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156156) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.96738416996743076373026321644507682176755695154430929196265246054012571599910
    Line 306, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 241814.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156156) { a_addr: 'hc1688  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h4  a_user: 'h26eaa  d_param: 'h0  d_source: 'h20  d_data: 'heff249e4  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd0a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 241814.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154193) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.73988446062064177650986300282784063917846855893546792942461378104324625625540
    Line 301, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 41087.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154193) { a_addr: 'h55438  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hfe  a_opcode: 'h4  a_user: 'h2732a  d_param: 'h0  d_source: 'hfe  d_data: 'h1604a5ab  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd6f  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 41087.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 3.flash_ctrl_integrity.72730189413559395264991141186072785419615888863136681420147571809326971605424
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 2422649.3 ns: (flash_ctrl_otf_scoreboard.sv:552) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (26054404875396935979555 [0x5846980980530021223] vs 41841863717384010008430 [0x8dc408193440363076e])
  UVM_INFO @ 2422649.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:364) [flash_ctrl_rw_vseq] Check failed (*) Too many unsuccessful attempts to create a prog_op has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 4.flash_ctrl_rw_serr.84594739869980164354030852256050409784207535059903489620168371187343327474601
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 14381492.8 ns: (flash_ctrl_otf_base_vseq.sv:364) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (0) Too many unsuccessful attempts to create a prog_op
  UVM_INFO @ 14381492.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157234) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.59182669161290102158530599522814575479341209013225909828425091664115097363399
    Line 296, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 49029.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157234) { a_addr: 'h70bb0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h4  a_user: 'h2722a  d_param: 'h0  d_source: 'h2b  d_data: 'h903cc793  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd39  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 49029.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c506_d5aa3dd5:ffffffff_d5aa3dd* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 20.flash_ctrl_intr_rd.29346762752840196990954930071668870613313136055539763462713339514051703139705
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 926476.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    3069c506_d5aa3dd5:ffffffff_d5aa3dd5  mismatch!!
  UVM_INFO @ 926476.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c3df32_655af321:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 24.flash_ctrl_intr_rd.85611251696894950696324184624018393681811853430929923274557596880361505169731
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 4929515.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    71c3df32_655af321:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 4929515.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 34.flash_ctrl_rw_evict.45247702074017973128897898903432904327383354533668072984181205809697601136430
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 16173.4 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 16173.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0bfa990ddc`