FLASH_CTRL Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.776m	2.726ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.110s	39.893us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.790s	33.727us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.890s	272.219us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.471m	3.811ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	57.300s	2.595ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.520s	325.476us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.890s	272.219us	20	20	100.00
		flash_ctrl_csr_aliasing	57.300s	2.595ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.940s	25.147us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.050s	48.402us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.630s	23.498us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.093m	205.387us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.822m	108.675ms	3	3	100.00
		flash_ctrl_hw_rma_reset	19.234m	540.337ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.220s	15.534us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.866m	1.345s	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	6.724m	2.132ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.708m	5.414ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.124h	49.895ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.386m	6.886ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.710s	80.802us	40	40	100.00
		flash_ctrl_rw_evict_all_en	32.620s	32.725us	40	40	100.00
		flash_ctrl_re_evict	36.320s	126.898us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.146m	4.091ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.146m	4.091ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.004m	122.878ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.890s	2.407ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.674m	941.211us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.785m	5.007ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.502m	429.499us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	50.276m	933.240us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.310s	26.347us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.535m	2.925ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.910s	12.782us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.550s	60.412us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	18.910m	215.681us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.711m	27.384ms	50	50	100.00
		flash_ctrl_otp_reset	2.278m	76.100us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.822m	108.675ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.826m	1.739ms	38	40	95.00
		flash_ctrl_intr_wr	1.411m	2.913ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	8.171m	41.979ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	6.628m	431.245ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.620m	1.927ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.214m	818.278us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.150s	22.646us	5	5	100.00
		flash_ctrl_ro_derr	3.305m	7.480ms	10	10	100.00
		flash_ctrl_rw_derr	12.176m	17.677ms	5	10	50.00
		flash_ctrl_derr_detect	43.360s	30.899us	0	5	0.00
		flash_ctrl_integrity	14.092m	4.139ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.300s	77.514us	5	5	100.00
		flash_ctrl_ro_serr	2.783m	1.264ms	10	10	100.00
		flash_ctrl_rw_serr	12.559m	4.467ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.705m	4.695ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.984m	1.139ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.703m	2.714ms	17	20	85.00
		flash_ctrl_write_word_sweep	15.050s	54.031us	1	1	100.00
		flash_ctrl_read_word_sweep	15.110s	24.007us	1	1	100.00
		flash_ctrl_ro	2.574m	652.005us	20	20	100.00
		flash_ctrl_rw	12.488m	52.685ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	44.510s	1.334ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.759m	72.648ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.531m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.760s	223.614us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.760s	53.344us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.970s	1.214ms	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.970s	1.214ms	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.790s	33.727us	5	5	100.00
		flash_ctrl_csr_rw	17.890s	272.219us	20	20	100.00
		flash_ctrl_csr_aliasing	57.300s	2.595ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.830s	185.868us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.790s	33.727us	5	5	100.00
		flash_ctrl_csr_rw	17.890s	272.219us	20	20	100.00
		flash_ctrl_csr_aliasing	57.300s	2.595ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.830s	185.868us	20	20	100.00
V2		TOTAL			989	1013	97.63
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.060s	42.884us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.060s	42.884us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.060s	42.884us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.060s	42.884us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.160s	19.562us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.326h	3.719ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.177m	13.759ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.177m	13.759ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.177m	13.759ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.090s	208.720us	3	3	100.00
		flash_ctrl_wr_intg	15.220s	81.005us	2	3	66.67
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.776m	2.726ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.278m	76.100us	80	80	100.00
		flash_ctrl_disable	22.910s	12.782us	50	50	100.00
		flash_ctrl_sec_info_access	1.562m	10.676ms	50	50	100.00
		flash_ctrl_connect	16.550s	60.412us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.670s	199.094us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.890s	272.219us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.060s	42.884us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.890s	272.219us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.060s	42.884us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.890s	272.219us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.060s	42.884us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.910s	12.782us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.090s	208.720us	3	3	100.00
		flash_ctrl_access_after_disable	13.860s	59.490us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.260s	27.409us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.910s	12.782us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.890s	2.407ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.488m	52.685ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.559m	4.467ms	7	10	70.00
		flash_ctrl_rw_derr	12.176m	17.677ms	5	10	50.00
		flash_ctrl_integrity	14.092m	4.139ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.822m	108.675ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.326h	3.719ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.326h	3.719ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.326h	3.719ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.326h	3.719ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.270s	686.426us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.410s	66.722us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.700s	17.984us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.326h	3.719ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.326h	3.719ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.326h	3.719ms	5	5	100.00
V2S		TOTAL			145	147	98.64
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.950s	201.891us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1255	1281	97.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	13	13	11	84.62
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.19	95.74	94.02	98.31	91.84	98.25	96.99	98.21

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 8 failures:
- Test flash_ctrl_rw has 2 failures.
  - 5.flash_ctrl_rw.74505414055086197239899506601924133809712418311426025766640135172159198746213
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:c5f88af3-b5ad-4b00-b8b8-f6a6339749d4
```
  - 7.flash_ctrl_rw.67006505717742801690638489783815568387457243601021919049425927573179365131596
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:94e17ad9-7c38-44d0-83eb-2d7940e207b4
```
- Test flash_ctrl_intr_wr has 1 failures.
  - 5.flash_ctrl_intr_wr.31964350330168658978160885412914399103123576962873563346107152028589014205207
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest/run.log
```
  Job ID: smart:ef51da1e-10b5-4060-8a5e-c5f0a301fbe2
```
- Test flash_ctrl_rw_serr has 1 failures.
  - 8.flash_ctrl_rw_serr.11029064037453344877917391205891728067807294710722630744325364495672920571070
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:1191d004-3469-46dd-9330-823a9fbc6123
```
- Test flash_ctrl_wo has 3 failures.
  - 13.flash_ctrl_wo.15781685803603285881437257163114283530800930863185400698550332725193220250175
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:00e55d2b-c113-4a3d-91d1-f62b5898033b
```
  - 14.flash_ctrl_wo.42861965765663844742693493649801153232545220712514048328896630953445446377554
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest/run.log
```
  Job ID: smart:9fa85734-fc5d-4d0b-a254-09b5a420436e
```
  - ... and 1 more failures.
- Test flash_ctrl_prog_reset has 1 failures.
  - 16.flash_ctrl_prog_reset.3154762857446668334717698348757930317962655049030575766953818306488061606855
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest/run.log
```
  Job ID: smart:48d18c7d-09e8-4842-ae22-f3d57e6f4b34
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 5 failures:
- Test flash_ctrl_rw_derr has 4 failures.
  - 1.flash_ctrl_rw_derr.89089148669671665815213364244326613063613836790200651098427789789824686310712
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 2236885.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004400
  UVM_INFO @ 2236885.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_rw_derr.3472963262849612162371175520376621142960123965702820359315448431139906489530
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 5261588.8 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003200
  UVM_INFO @ 5261588.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test flash_ctrl_integrity has 1 failures.
  - 2.flash_ctrl_integrity.43870888296194921663776615073727133704582361594803374957222579548789873721635
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 29795643.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004200
  UVM_INFO @ 29795643.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
- Test flash_ctrl_derr_detect has 2 failures.
  - 1.flash_ctrl_derr_detect.89104037797507970312859629206673775998531835537262454473406770166625929862140
    Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 82834.0 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 82834.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_derr_detect.12535256474357520046673434035497046777420618361126965897685447536204974218248
    Line 302, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 45510.0 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 45510.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 8.flash_ctrl_rw_derr.13998576438785590574541117958131346228011890877756671637593325928687349009008
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 4638936.7 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 4638936.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 2 failures.
  - 2.flash_ctrl_rw_serr.20444968276332585855249189147773031036261736863859364575446362893925390097957
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 338545.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 338545.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.flash_ctrl_rw_serr.66264837044931879994415245667930643805974276731256172366784661784802032649603
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 2075529.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2075529.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155376) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.2229274978337884898343075254445712562240817359576468244099073177401232006380
    Line 301, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 80039.7 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155376) { a_addr: 'h2e988  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4c  a_opcode: 'h4  a_user: 'h25faa  d_param: 'h0  d_source: 'h4c  d_data: 'h1025b3ff  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd3c  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 80039.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [wdata_page0_comp_bank0] *: obs:exp ccafcd70_7da676cb:a8052e1d_e9a044bb mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 1.flash_ctrl_wr_intg.3921879171192790309642384987875885264175144372346382964300616600752310488380
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 59135.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [wdata_page0_comp_bank0]    0: obs:exp    ccafcd70_7da676cb:a8052e1d_e9a044bb  mismatch!!
  UVM_INFO @ 59135.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153841) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.70147974791327608681813976488054250666201521877709039028029778998425769470123
    Line 304, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 30899.0 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153841) { a_addr: 'hc4e10  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h79  a_opcode: 'h4  a_user: 'h2652a  d_param: 'h0  d_source: 'h79  d_data: 'h92de8686  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd22  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 30899.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:555) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 3.flash_ctrl_integrity.22767052711396681026928367239384393635091237546942132936783164812308623086386
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 3400678.3 ns: (flash_ctrl_otf_scoreboard.sv:555) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (10035028786081819787269 [0x220000009148a440005] vs 10035047989153565507621 [0x2200044422c18440025])
  UVM_INFO @ 3400678.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157107) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.61700145808059587893503499899525309481938117950276284175416337541366495591938
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 27217.9 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157107) { a_addr: 'hd45c4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hfd  a_opcode: 'h4  a_user: 'h2532a  d_param: 'h0  d_source: 'hfd  d_data: 'h9979d069  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd52  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 27217.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 4.flash_ctrl_phy_ack_consistency.102491311759529904783322036238525371657541440941690107229399605321702649360962
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 18287.7 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x64)
  UVM_INFO @ 18287.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp bab5f93b_0f52474f:ffffffff_0f52474f mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 12.flash_ctrl_intr_rd.62806489334053437412850818276941969069493577744995109271341446843875794556964
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 819893.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    bab5f93b_0f52474f:ffffffff_0f52474f  mismatch!!
  UVM_INFO @ 819893.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp e6d1fbaf_48697ebb:ffffffff_48697ebb mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 34.flash_ctrl_intr_rd.57378398210370168768010507354193522964734649162764556666834339492820868521586
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1023946.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    1: obs:exp    e6d1fbaf_48697ebb:ffffffff_48697ebb  mismatch!!
  UVM_INFO @ 1023946.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

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Past Results

GitHub Revision: `e439226b6c`