FLASH_CTRL Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.229m	1.687ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.150s	16.062us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	38.650s	122.094us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.220s	107.088us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.375m	3.208ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.108m	3.281ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.400s	39.322us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.220s	107.088us	20	20	100.00
		flash_ctrl_csr_aliasing	1.108m	3.281ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.420s	18.814us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.730s	31.778us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.870s	25.468us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.084m	266.906us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	39.059m	140.749ms	3	3	100.00
		flash_ctrl_hw_rma_reset	26.312m	760.522ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.880s	16.375us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	48.676m	288.973ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.249m	13.932ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.210m	44.364ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.254h	58.698ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.068m	3.805ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	31.850s	33.508us	38	40	95.00
		flash_ctrl_rw_evict_all_en	31.840s	146.112us	40	40	100.00
		flash_ctrl_re_evict	36.070s	971.971us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.892m	23.076ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.892m	23.076ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	11.085m	10.022ms	19	20	95.00
V2	fetch_code	flash_ctrl_fetch_code	31.160s	2.349ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.035m	1.888ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.077m	17.469ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.190m	3.208ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	41.995m	1.977ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.850s	15.346us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.056m	1.598ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.530s	13.663us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.400s	19.648us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	26.923m	1.857ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.426m	5.868ms	50	50	100.00
		flash_ctrl_otp_reset	2.279m	50.096us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	39.059m	140.749ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.080m	1.568ms	39	40	97.50
		flash_ctrl_intr_wr	1.332m	13.971ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.731m	32.268ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.629m	92.023ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.496m	3.889ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.245m	1.338ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.180s	208.660us	5	5	100.00
		flash_ctrl_ro_derr	2.987m	3.384ms	9	10	90.00
		flash_ctrl_rw_derr	12.513m	7.259ms	5	10	50.00
		flash_ctrl_derr_detect	42.850s	42.930us	0	5	0.00
		flash_ctrl_integrity	12.304m	8.425ms	2	5	40.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.190s	23.434us	5	5	100.00
		flash_ctrl_ro_serr	2.826m	11.147ms	10	10	100.00
		flash_ctrl_rw_serr	12.390m	6.045ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.231m	2.614ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.703m	972.073us	4	5	80.00
V2	scramble	flash_ctrl_wo	4.530m	3.238ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.330s	75.084us	1	1	100.00
		flash_ctrl_read_word_sweep	14.150s	41.015us	1	1	100.00
		flash_ctrl_ro	2.415m	605.081us	20	20	100.00
		flash_ctrl_rw	11.962m	15.080ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	43.060s	1.319ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.749m	332.109ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.514m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.390s	73.555us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.320s	17.323us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.470s	73.277us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.470s	73.277us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	38.650s	122.094us	5	5	100.00
		flash_ctrl_csr_rw	18.220s	107.088us	20	20	100.00
		flash_ctrl_csr_aliasing	1.108m	3.281ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.790s	806.847us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	38.650s	122.094us	5	5	100.00
		flash_ctrl_csr_rw	18.220s	107.088us	20	20	100.00
		flash_ctrl_csr_aliasing	1.108m	3.281ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.790s	806.847us	20	20	100.00
V2		TOTAL			990	1013	97.73
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.010s	36.613us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.010s	36.613us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.010s	36.613us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.010s	36.613us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.230s	38.778us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.342h	5.601ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.010m	2.172ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.010m	2.172ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.010m	2.172ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.450s	453.288us	3	3	100.00
		flash_ctrl_wr_intg	15.190s	45.452us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.229m	1.687ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.279m	50.096us	80	80	100.00
		flash_ctrl_disable	22.530s	13.663us	50	50	100.00
		flash_ctrl_sec_info_access	1.444m	9.111ms	50	50	100.00
		flash_ctrl_connect	16.400s	19.648us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.360s	39.083us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.220s	107.088us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.010s	36.613us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.220s	107.088us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.010s	36.613us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.220s	107.088us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.010s	36.613us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.530s	13.663us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.450s	453.288us	3	3	100.00
		flash_ctrl_access_after_disable	13.870s	24.720us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.270s	26.989us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.530s	13.663us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	31.160s	2.349ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.962m	15.080ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.390m	6.045ms	7	10	70.00
		flash_ctrl_rw_derr	12.513m	7.259ms	5	10	50.00
		flash_ctrl_integrity	12.304m	8.425ms	2	5	40.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	39.059m	140.749ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.342h	5.601ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.342h	5.601ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.342h	5.601ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.342h	5.601ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.550s	795.154us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.270s	23.303us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.280s	188.841us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.342h	5.601ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.342h	5.601ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.342h	5.601ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.120s	48.012us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1257	1281	98.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	45	81.82
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	95.24	93.90	98.31	92.52	97.14	96.89	98.18

Failure Buckets

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:555) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 3 failures:

Test flash_ctrl_integrity has 3 failures.

0.flash_ctrl_integrity.91977062385175509354633586688920622234598903301267191821129114210866711257905
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 2792134.6 ns: (flash_ctrl_otf_scoreboard.sv:555) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (2365806610056424849409 [0x8040298144044a0001] vs 18894167695064490323208 [0x4004140051204002d08])
  UVM_INFO @ 2792134.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_integrity.106334991868716441224952741908293159749128372457746130860626722045026313142271
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_ERROR @ 2651745.2 ns: (flash_ctrl_otf_scoreboard.sv:555) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (453174731205393441353 [0x1891101102389ae249] vs 21702596655628142434821 [0x498800801023802da05])
  UVM_INFO @ 2651745.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_rw_serr has 2 failures.

2.flash_ctrl_rw_serr.60401334093257829790861609609853096844354486686645833762395374810719919592604
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 3585629.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3585629.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_serr.46044118227849666941825837021054018979396265648259055022411921182876571364152
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 1289727.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1289727.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_serr_address has 1 failures.

4.flash_ctrl_serr_address.17657250605928426732162459019307593923968309537570743523251325717141224440177
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest/run.log

  UVM_ERROR @ 1299690.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1299690.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_rw_derr has 3 failures.
  - 3.flash_ctrl_rw_derr.96530028378354759820769004193863412940550202268181632306367499219837732763762
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 5963480.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002a78
  UVM_INFO @ 5963480.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_rw_derr.44645934636253412412608150307286532735991224878720503832211084787503738652179
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 2792897.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004680
  UVM_INFO @ 2792897.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 2 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 5.flash_ctrl_intr_wr_slow_flash.26178033399178035346432877897132239963028860576910065344882904841616952216873
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job ID: smart:6a286828-948c-4cc7-9123-0956b4b25da7
```
- Test flash_ctrl_rw_serr has 1 failures.
  - 9.flash_ctrl_rw_serr.84401471743396652712800091225743215091100131936362473599583812239088726069991
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:4e637d81-724b-4aa1-b572-e0867e87518e
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict has 2 failures.
  - 13.flash_ctrl_rw_evict.32557797920491586436348396933396492598252684335193955366735685934879348834456
    Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 8905.5 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 8905.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.flash_ctrl_rw_evict.108639973188632187408763999334408834548716145045067339835742555155282576658957
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 43668.0 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 43668.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:555) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 0.flash_ctrl_rw_derr.82435878134717266819286077891629145121938686092655767275839829278110433120152
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 9643678.8 ns: (flash_ctrl_otf_scoreboard.sv:555) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (55544029484681529088 [0x302d408880c440700] vs 55544029486829012736 [0x302d408888c440700])
  UVM_INFO @ 9643678.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152886) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 0.flash_ctrl_derr_detect.104735552449051138674648012287047235899760496179841100059783855858064924333566
    Line 306, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 42930.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152886) { a_addr: 'he0ed0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha9  a_opcode: 'h4  a_user: 'h2692a  d_param: 'h0  d_source: 'ha9  d_data: 'h45ae52fe  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd6e  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 42930.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153183) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 1.flash_ctrl_derr_detect.47723328455584541377075768222305423409333214302594908438034477898993267755910
    Line 305, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 35052.5 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153183) { a_addr: 'hc14cc  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h241aa  d_param: 'h0  d_source: 'h1  d_data: 'hb0e62af1  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd0d  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 35052.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 1.flash_ctrl_phy_ack_consistency.32063493643088942333439173847560333075666568266475137119480079091344814767293
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 18565.2 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x18)
  UVM_INFO @ 18565.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153003) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.54305853597642485871965203925267373034593480227644583698115271483649634699316
    Line 302, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 28109.2 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153003) { a_addr: 'h11ab4  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h73  a_opcode: 'h4  a_user: 'h24baa  d_param: 'h0  d_source: 'h73  d_data: 'h6dcd1538  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd43  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 28109.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154871) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 3.flash_ctrl_derr_detect.32691625159724261728343041043619930852940879301516817404161323568516104743857
    Line 300, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 357616.8 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154871) { a_addr: 'h6dc58  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he8  a_opcode: 'h4  a_user: 'h2612a  d_param: 'h0  d_source: 'he8  d_data: 'h4a659c6d  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd6b  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 357616.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_scoreboard.sv:863) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153474) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.16827119287252300214247292316685635850869326548074238745704278073873843970821
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 78244.0 ns: (flash_ctrl_scoreboard.sv:863) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153474) { a_addr: 'h24a00  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3d  a_opcode: 'h4  a_user: 'h27baa  d_param: 'h0  d_source: 'h3d  d_data: 'h5d5b1946  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd1a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 78244.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp b738b6aa_3b46e0c1:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 4.flash_ctrl_intr_rd.46757855685584374945728987576780114136113310779285641319171542803930676185562
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 16297.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    b738b6aa_3b46e0c1:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 16297.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:481) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@3628465) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_derr has 1 failures.

5.flash_ctrl_rw_derr.84947657729633427443810179544069581874904810357837409958166849684747161192732
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log

  UVM_ERROR @ 2009227.5 ns: (cip_base_scoreboard.sv:481) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@3628465) { a_addr: 'h40090  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h54  a_opcode: 'h4  a_user: 'h25daa  d_param: 'h0  d_source: 'h54  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2009227.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:193) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:* has 1 failures:
- Test flash_ctrl_mp_regions has 1 failures.
  - 6.flash_ctrl_mp_regions.104302406770009949532520302201518414548092669101486395683916126745112705903326
    Line 316, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest/run.log
```
  UVM_FATAL @ 464424.9 ns: (flash_ctrl_mp_regions_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:3  exp_alert_cnt:4
  UVM_INFO @ 464424.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
- Test flash_ctrl_ro_derr has 1 failures.
  - 7.flash_ctrl_ro_derr.79709737735964576911048560765203469502012616600552704778208907304524744552483
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest/run.log
```
  UVM_ERROR @ 2667743.1 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 2667743.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```