FLASH_CTRL Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: 4877b481e8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.380m	4.249ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.570s	13.484us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	31.040s	250.519us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.940s	86.387us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.440m	3.101ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	57.050s	1.575ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.200s	44.772us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.940s	86.387us	20	20	100.00
		flash_ctrl_csr_aliasing	57.050s	1.575ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.530s	44.047us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.690s	17.608us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.420s	125.090us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.874m	917.815us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.508m	1.340s	3	3	100.00
		flash_ctrl_hw_rma_reset	18.268m	200.218ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.840s	15.776us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	54.045m	296.759ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.757m	13.942ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.715m	4.518ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.070h	49.891ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.039m	5.419ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.320s	62.856us	37	40	92.50
		flash_ctrl_rw_evict_all_en	31.860s	234.331us	39	40	97.50
		flash_ctrl_re_evict	36.380s	85.903us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.013m	17.258ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.013m	17.258ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	13.636m	73.540ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.760s	1.600ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.409m	2.562ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.316m	48.251ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.515m	430.040us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.044m	580.598us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.730s	15.996us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.445m	16.548ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.760s	27.452us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.070s	13.545us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.374m	4.244ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.213m	6.429ms	50	50	100.00
		flash_ctrl_otp_reset	2.253m	56.587us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	36.508m	1.340s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.630m	1.562ms	39	40	97.50
		flash_ctrl_intr_wr	1.526m	17.217ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.556m	12.064ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.109m	227.673ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.509m	6.463ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.241m	2.690ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.740s	32.366us	5	5	100.00
		flash_ctrl_ro_derr	2.876m	587.886us	10	10	100.00
		flash_ctrl_rw_derr	4.587m	2.232ms	10	10	100.00
		flash_ctrl_derr_detect	3.419m	3.199ms	5	5	100.00
		flash_ctrl_integrity	13.342m	20.070ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.110s	103.264us	5	5	100.00
		flash_ctrl_ro_serr	2.593m	669.218us	10	10	100.00
		flash_ctrl_rw_serr	4.504m	6.016ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.572m	11.616ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.542m	946.294us	5	5	100.00
V2	scramble	flash_ctrl_wo	4.529m	3.244ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.760s	101.731us	1	1	100.00
		flash_ctrl_read_word_sweep	14.390s	31.888us	1	1	100.00
		flash_ctrl_ro	2.467m	2.163ms	20	20	100.00
		flash_ctrl_rw	11.793m	15.514ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	41.790s	675.971us	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.938m	62.596ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.112m	10.011ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.860s	106.197us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.930s	163.148us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.080s	247.761us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.080s	247.761us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	31.040s	250.519us	5	5	100.00
		flash_ctrl_csr_rw	17.940s	86.387us	20	20	100.00
		flash_ctrl_csr_aliasing	57.050s	1.575ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.840s	431.103us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	31.040s	250.519us	5	5	100.00
		flash_ctrl_csr_rw	17.940s	86.387us	20	20	100.00
		flash_ctrl_csr_aliasing	57.050s	1.575ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.840s	431.103us	20	20	100.00
V2		TOTAL			1005	1013	99.21
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.040s	26.296us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.040s	26.296us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.040s	26.296us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.040s	26.296us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.030s	20.742us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.368h	1.928ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.404m	5.343ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.404m	5.343ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.404m	5.343ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.980s	206.500us	3	3	100.00
		flash_ctrl_wr_intg	14.990s	42.292us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.380m	4.249ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.253m	56.587us	80	80	100.00
		flash_ctrl_disable	22.760s	27.452us	50	50	100.00
		flash_ctrl_sec_info_access	1.379m	1.867ms	50	50	100.00
		flash_ctrl_connect	16.070s	13.545us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.910s	197.509us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.940s	86.387us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.040s	26.296us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.940s	86.387us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.040s	26.296us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.940s	86.387us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.040s	26.296us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.760s	27.452us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.980s	206.500us	3	3	100.00
		flash_ctrl_access_after_disable	13.640s	22.173us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.820s	27.797us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.760s	27.452us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.760s	1.600ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.793m	15.514ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.504m	6.016ms	10	10	100.00
		flash_ctrl_rw_derr	4.587m	2.232ms	10	10	100.00
		flash_ctrl_integrity	13.342m	20.070ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.508m	1.340s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.368h	1.928ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.368h	1.928ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.368h	1.928ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.368h	1.928ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.310s	927.583us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.200s	14.833us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.100s	27.398us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.368h	1.928ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.368h	1.928ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.368h	1.928ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.160s	96.834us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1281	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	49	89.09
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.18	95.71	93.85	98.31	91.84	98.21	97.18	98.18

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 4 failures:

  • Test flash_ctrl_rw_evict has 3 failures.

    • 19.flash_ctrl_rw_evict.24094446822752955044281193443717801059743120661744967656911553404323755380525
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 26158.6 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 26158.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.flash_ctrl_rw_evict.25041884186387372815532298214647036061304730017693771617241987510438605769116
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 21936.7 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 21936.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 19.flash_ctrl_rw_evict_all_en.56603174296645102780105342693804702819139595998143306854483747216814521010445
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 31927.1 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 31927.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:

  • Test flash_ctrl_fs_sup has 1 failures.

    • 2.flash_ctrl_fs_sup.17089706037686876940085238606198600437481028192275823996123186433531833969420
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest/run.log

        UVM_ERROR @ 952927.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 952927.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw has 1 failures.

    • 11.flash_ctrl_rw.32647882267257056024257339488098708105523200716387918750541631359725690989858
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest/run.log

        UVM_ERROR @ 92471.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 92471.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:

  • Test flash_ctrl_integrity has 1 failures.

    • 0.flash_ctrl_integrity.68614774808911608651399498168908812705757377802063714816964146372895618426406
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

        UVM_ERROR @ 12569788.4 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003a00
        UVM_INFO @ 12569788.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e6c_e223993f:ffffffff_e223993f mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 32.flash_ctrl_intr_rd.37772217002611848161851783595509960461652123218987018285258850720876430844834
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 1622043.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    79060e6c_e223993f:ffffffff_e223993f  mismatch!!
        UVM_INFO @ 1622043.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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