FLASH_CTRL Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.283m	74.632us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.010s	104.576us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.430s	42.453us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.860s	306.080us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.841m	22.099ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.165m	7.115ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.610s	42.806us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.860s	306.080us	20	20	100.00
		flash_ctrl_csr_aliasing	1.165m	7.115ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.480s	23.673us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.600s	15.413us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.850s	37.877us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.018m	69.210us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	30.576m	169.351ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.113m	420.298ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.030s	40.108us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	54.672m	2.004s	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.256m	4.168ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.398m	11.240ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.069h	99.778ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.160m	1.415ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.630s	132.171us	39	40	97.50
		flash_ctrl_rw_evict_all_en	31.730s	31.578us	38	40	95.00
		flash_ctrl_re_evict	35.730s	295.871us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.808m	5.525ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.808m	5.525ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.242m	33.247ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	26.850s	1.019ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	17.361m	130.658us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.460m	19.131ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.546m	3.203ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	41.126m	1.834ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.900s	46.111us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.138m	2.337ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.520s	38.992us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.230s	22.005us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	25.137m	1.013ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.073m	3.268ms	50	50	100.00
		flash_ctrl_otp_reset	2.235m	312.663us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	30.576m	169.351ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.536m	1.771ms	36	40	90.00
		flash_ctrl_intr_wr	1.836m	45.400ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.184m	110.236ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.284m	117.955ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.544m	5.746ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.413m	15.780ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.690s	61.350us	5	5	100.00
		flash_ctrl_ro_derr	2.982m	594.799us	10	10	100.00
		flash_ctrl_rw_derr	4.572m	3.220ms	10	10	100.00
		flash_ctrl_derr_detect	3.788m	3.432ms	5	5	100.00
		flash_ctrl_integrity	11.992m	8.139ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.410s	108.065us	5	5	100.00
		flash_ctrl_ro_serr	2.418m	646.606us	10	10	100.00
		flash_ctrl_rw_serr	4.450m	3.913ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.499m	5.692ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.473m	3.432ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.425m	19.140ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.100s	41.102us	1	1	100.00
		flash_ctrl_read_word_sweep	14.170s	23.361us	1	1	100.00
		flash_ctrl_ro	2.372m	1.195ms	20	20	100.00
		flash_ctrl_rw	11.002m	3.620ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	41.570s	449.722us	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.885m	83.099ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.565m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.370s	59.782us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.010s	45.441us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.270s	131.075us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.270s	131.075us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.430s	42.453us	5	5	100.00
		flash_ctrl_csr_rw	17.860s	306.080us	20	20	100.00
		flash_ctrl_csr_aliasing	1.165m	7.115ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	33.520s	151.162us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.430s	42.453us	5	5	100.00
		flash_ctrl_csr_rw	17.860s	306.080us	20	20	100.00
		flash_ctrl_csr_aliasing	1.165m	7.115ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	33.520s	151.162us	20	20	100.00
V2		TOTAL			1005	1013	99.21
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.400s	50.785us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.400s	50.785us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.400s	50.785us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.400s	50.785us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.040s	12.237us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.361h	5.228ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.153m	677.717us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.153m	677.717us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.153m	677.717us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.930s	624.259us	3	3	100.00
		flash_ctrl_wr_intg	15.280s	805.815us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.283m	74.632us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.235m	312.663us	80	80	100.00
		flash_ctrl_disable	22.520s	38.992us	50	50	100.00
		flash_ctrl_sec_info_access	1.557m	24.113ms	50	50	100.00
		flash_ctrl_connect	16.230s	22.005us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.820s	20.371us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.860s	306.080us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.400s	50.785us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.860s	306.080us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.400s	50.785us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.860s	306.080us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.400s	50.785us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.520s	38.992us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.930s	624.259us	3	3	100.00
		flash_ctrl_access_after_disable	13.900s	22.362us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.240s	39.802us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.520s	38.992us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	26.850s	1.019ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.002m	3.620ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.450m	3.913ms	10	10	100.00
		flash_ctrl_rw_derr	4.572m	3.220ms	10	10	100.00
		flash_ctrl_integrity	11.992m	8.139ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	30.576m	169.351ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.361h	5.228ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.361h	5.228ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.361h	5.228ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.361h	5.228ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.970s	886.077us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.190s	159.099us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.130s	43.504us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.361h	5.228ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.361h	5.228ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.361h	5.228ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	49.680s	114.001us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1281	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	51	92.73
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.27	95.67	93.88	98.25	92.52	98.14	97.18	98.21

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:

  • Test flash_ctrl_rw_evict_all_en has 2 failures.

    • 3.flash_ctrl_rw_evict_all_en.83555389215567442060373374108259387180501341766646879976057489324851021985543
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 17585.6 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 17585.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.flash_ctrl_rw_evict_all_en.75938847085018898397214931806377909826836073366422769440819295607016639980411
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 16624.3 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 16624.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw_evict has 1 failures.

    • 29.flash_ctrl_rw_evict.115353268027730665287525841758003125106986425408902532217924459957776946053330
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 8604.5 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 8604.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_fs_sup has 1 failures.

    • 4.flash_ctrl_fs_sup.78065007290719510993672958566897718511302015185219252057643045099868351164525
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest/run.log

        UVM_ERROR @ 889633.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 889633.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *f246_e8bb7f62:ffffffff_e8bb7f* mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 12.flash_ctrl_intr_rd.37958824206718506604863464908052362269271800457410513122288671602818446155950
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 1275448.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    7745f246_e8bb7f62:ffffffff_e8bb7f62  mismatch!!
        UVM_INFO @ 1275448.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *d975e9_401f92be:ffffffff_401f92be mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 15.flash_ctrl_intr_rd.88233524060273237690134990256427721728215324406032052635297249876573464014395
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 1690191.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    53d975e9_401f92be:ffffffff_401f92be  mismatch!!
        UVM_INFO @ 1690191.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *fea5de_d438f4ae:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 33.flash_ctrl_intr_rd.50747870473269579424095853872901450730164916394044796086328087662498324415563
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 6016186.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    92fea5de_d438f4ae:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 6016186.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *_60d6fdf3:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 39.flash_ctrl_intr_rd.490258089020961755475508559663582129012581922474025659440318392319962374257
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 601060.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    28334443_60d6fdf3:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 601060.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.07.27_10.02.40
• 2024.07.26_09.23.23
• 2024.07.25_08.55.43
• 2024.07.24_08.35.00
• 2024.07.23_09.06.29