FLASH_CTRL Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.715m	123.674us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	25.910s	77.760us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.500s	24.825us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.750s	295.995us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.109m	662.879us	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.140m	1.634ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.710s	159.619us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.750s	295.995us	20	20	100.00
		flash_ctrl_csr_aliasing	1.140m	1.634ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.740s	17.094us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.920s	45.990us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.990s	77.694us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.331m	420.078us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.596m	141.196ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.567m	230.202ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.060s	25.626us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	40.922m	359.022ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.515m	11.217ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.875m	10.804ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.280h	203.468ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	4.081m	2.010ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.510s	75.140us	40	40	100.00
		flash_ctrl_rw_evict_all_en	32.190s	48.831us	39	40	97.50
		flash_ctrl_re_evict	36.180s	157.613us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.389m	2.088ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.389m	2.088ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	21.620m	64.653ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.920s	1.339ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.303m	3.890ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	45.231m	6.310ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.641m	792.297us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	49.132m	11.343ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.840s	15.436us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.730m	1.612ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.840s	13.739us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.680s	17.527us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.480m	291.385us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.734m	18.099ms	50	50	100.00
		flash_ctrl_otp_reset	2.236m	50.088us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	36.596m	141.196ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.401m	16.519ms	39	40	97.50
		flash_ctrl_intr_wr	1.319m	2.327ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.188m	49.615ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.726m	89.941ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.733m	3.936ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.225m	3.520ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.850s	38.969us	5	5	100.00
		flash_ctrl_ro_derr	2.817m	1.265ms	10	10	100.00
		flash_ctrl_rw_derr	4.845m	10.272ms	10	10	100.00
		flash_ctrl_derr_detect	3.603m	1.893ms	5	5	100.00
		flash_ctrl_integrity	12.656m	7.264ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.320s	71.182us	5	5	100.00
		flash_ctrl_ro_serr	2.675m	575.919us	10	10	100.00
		flash_ctrl_rw_serr	4.689m	8.241ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.587m	3.637ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.642m	10.246ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.298m	11.041ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.250s	42.277us	1	1	100.00
		flash_ctrl_read_word_sweep	14.260s	22.842us	1	1	100.00
		flash_ctrl_ro	2.273m	2.329ms	20	20	100.00
		flash_ctrl_rw	11.607m	18.261ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	41.140s	458.089us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.656m	40.555ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.240m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	16.090s	348.555us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.060s	47.293us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.540s	267.110us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.540s	267.110us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.500s	24.825us	5	5	100.00
		flash_ctrl_csr_rw	17.750s	295.995us	20	20	100.00
		flash_ctrl_csr_aliasing	1.140m	1.634ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.100s	179.378us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.500s	24.825us	5	5	100.00
		flash_ctrl_csr_rw	17.750s	295.995us	20	20	100.00
		flash_ctrl_csr_aliasing	1.140m	1.634ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.100s	179.378us	20	20	100.00
V2		TOTAL			1010	1013	99.70
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.500s	48.221us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.500s	48.221us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.500s	48.221us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.500s	48.221us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.100s	34.391us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.359h	3.795ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.278m	862.633us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.278m	862.633us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.278m	862.633us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.140s	113.317us	3	3	100.00
		flash_ctrl_wr_intg	15.410s	581.260us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.715m	123.674us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.236m	50.088us	80	80	100.00
		flash_ctrl_disable	22.840s	13.739us	50	50	100.00
		flash_ctrl_sec_info_access	1.692m	22.141ms	50	50	100.00
		flash_ctrl_connect	16.680s	17.527us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.180s	22.796us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.750s	295.995us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.500s	48.221us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.750s	295.995us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.500s	48.221us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.750s	295.995us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.500s	48.221us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.840s	13.739us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.140s	113.317us	3	3	100.00
		flash_ctrl_access_after_disable	14.200s	14.324us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.370s	27.536us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.840s	13.739us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.920s	1.339ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.607m	18.261ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.689m	8.241ms	10	10	100.00
		flash_ctrl_rw_derr	4.845m	10.272ms	10	10	100.00
		flash_ctrl_integrity	12.656m	7.264ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.596m	141.196ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.359h	3.795ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.359h	3.795ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.359h	3.795ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.359h	3.795ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.790s	826.036us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.090s	15.641us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.600s	30.467us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.359h	3.795ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.359h	3.795ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.359h	3.795ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.870s	59.366us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1278	1281	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	52	94.55
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.16	95.71	94.01	98.31	91.84	98.25	96.80	98.18

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_serr_counter has 1 failures.

    • 0.flash_ctrl_serr_counter.81638489434656912211289060713213374213787598757613336008996269025479486748575
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest/run.log

        UVM_ERROR @ 608954.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 608954.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 9.flash_ctrl_rw_evict_all_en.106244956273595372516683521622437716909119826964430863940965741529017103714587
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 11618.6 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 11618.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *d55f_17a84e9e:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 12.flash_ctrl_intr_rd.41342715009977700905077106853913848055072381992207201975947375977440113360413
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 7615045.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    2689d55f_17a84e9e:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 7615045.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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