FLASH_CTRL Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.696m	833.984us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.030s	29.153us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.010s	105.124us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.590s	53.885us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.198m	5.462ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.195m	10.403ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	21.070s	47.585us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.590s	53.885us	20	20	100.00
		flash_ctrl_csr_aliasing	1.195m	10.403ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.240s	28.731us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.550s	47.682us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.830s	93.767us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.635m	57.429us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.008m	337.777ms	2	3	66.67
		flash_ctrl_hw_rma_reset	20.945m	420.314ms	20	20	100.00
		flash_ctrl_lcmgr_intg	15.120s	6.425us	18	20	90.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.226m	299.313ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.456m	30.484ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.443m	2.370ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.144h	49.894ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.652m	1.724ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.300s	48.395us	39	40	97.50
		flash_ctrl_rw_evict_all_en	33.390s	29.767us	39	40	97.50
		flash_ctrl_re_evict	35.970s	86.275us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.388m	2.911ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.388m	2.911ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	10.558m	16.975ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.390s	472.021us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.161m	5.091ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.865m	6.499ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	19.057m	608.224us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.300m	977.583us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.930s	45.602us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.528m	1.255ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.260s	24.963us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.460s	69.656us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	35.006m	4.506ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.704m	12.487ms	50	50	100.00
		flash_ctrl_otp_reset	2.315m	41.125us	79	80	98.75
V2	isolation_partition	flash_ctrl_hw_rma	33.008m	337.777ms	2	3	66.67
V2	interrupts	flash_ctrl_intr_rd	5.327m	5.910ms	38	40	95.00
		flash_ctrl_intr_wr	1.476m	11.218ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.293m	23.780ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.850m	100.701ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.556m	4.009ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.288m	4.028ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.700s	32.112us	5	5	100.00
		flash_ctrl_ro_derr	3.370m	4.150ms	10	10	100.00
		flash_ctrl_rw_derr	4.245m	3.185ms	9	10	90.00
		flash_ctrl_derr_detect	3.651m	977.497us	5	5	100.00
		flash_ctrl_integrity	13.360m	4.569ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.130s	44.356us	5	5	100.00
		flash_ctrl_ro_serr	2.907m	1.141ms	10	10	100.00
		flash_ctrl_rw_serr	5.592m	29.727ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.466m	743.964us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.518m	3.569ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.183m	6.015ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.450s	299.481us	1	1	100.00
		flash_ctrl_read_word_sweep	14.470s	82.660us	1	1	100.00
		flash_ctrl_ro	2.823m	5.082ms	19	20	95.00
		flash_ctrl_rw	12.183m	4.750ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	44.230s	1.303ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.072m	40.540ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.383m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.250s	220.137us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.960s	47.727us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.240s	65.398us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.240s	65.398us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.010s	105.124us	5	5	100.00
		flash_ctrl_csr_rw	17.590s	53.885us	20	20	100.00
		flash_ctrl_csr_aliasing	1.195m	10.403ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.890s	1.138ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.010s	105.124us	5	5	100.00
		flash_ctrl_csr_rw	17.590s	53.885us	20	20	100.00
		flash_ctrl_csr_aliasing	1.195m	10.403ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.890s	1.138ms	20	20	100.00
V2		TOTAL			1001	1013	98.82
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.260s	23.652us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.260s	23.652us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.260s	23.652us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.260s	23.652us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.110s	34.914us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.329h	2.693ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.488m	1.331ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.488m	1.331ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.488m	1.331ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.250s	65.002us	3	3	100.00
		flash_ctrl_wr_intg	15.290s	163.371us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.696m	833.984us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.315m	41.125us	79	80	98.75
		flash_ctrl_disable	23.260s	24.963us	50	50	100.00
		flash_ctrl_sec_info_access	1.666m	42.779ms	50	50	100.00
		flash_ctrl_connect	16.460s	69.656us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.780s	21.128us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.590s	53.885us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.260s	23.652us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.590s	53.885us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.260s	23.652us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.590s	53.885us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.260s	23.652us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.260s	24.963us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.250s	65.002us	3	3	100.00
		flash_ctrl_access_after_disable	13.950s	14.223us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	31.870s	64.268us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.260s	24.963us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.390s	472.021us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.183m	4.750ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	5.592m	29.727ms	10	10	100.00
		flash_ctrl_rw_derr	4.245m	3.185ms	9	10	90.00
		flash_ctrl_integrity	13.360m	4.569ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.008m	337.777ms	2	3	66.67
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.329h	2.693ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.329h	2.693ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.329h	2.693ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.329h	2.693ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.680s	896.418us	4	5	80.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.400s	28.175us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.640s	156.672us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.329h	2.693ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.329h	2.693ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.329h	2.693ms	5	5	100.00
V2S		TOTAL			145	147	98.64
V3	asymmetric_read_path	flash_ctrl_rd_ooo	47.150s	231.728us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1267	1281	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	46	83.64
V2S	13	13	11	84.62
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.25	95.73	93.96	98.31	92.52	98.25	96.89	98.12

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 2 failures:

  • Test flash_ctrl_lcmgr_intg has 2 failures.

    • 1.flash_ctrl_lcmgr_intg.90367551438306556725509896678166282520718184540435637046661977002813706346222
      Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest/run.log

        UVM_ERROR @ 6425.3 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
        UVM_INFO @ 6425.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.flash_ctrl_lcmgr_intg.90142485191533402494517312048164794060634492849730205769927518722143923104773
      Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest/run.log

        UVM_ERROR @ 27331.7 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
        UVM_INFO @ 27331.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:

  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 2.flash_ctrl_rw_evict_all_en.214795578511748235669398674477379815034042707657269231065093295269109028932
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 24758.9 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 24758.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw_evict has 1 failures.

    • 12.flash_ctrl_rw_evict.76590076541485581680764275299164529606587423778776677534765578939242431459479
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 9898.3 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 9898.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 2 failures:

  • Test flash_ctrl_phy_arb_redun has 1 failures.

    • 2.flash_ctrl_phy_arb_redun.69556199075558886790917754637078937119129830396867434107875587057900837225000
      Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest/run.log

        UVM_ERROR @ 75089.7 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x5c)
        UVM_INFO @ 75089.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_phy_ack_consistency has 1 failures.

    • 3.flash_ctrl_phy_ack_consistency.20302932317087216324955670630399608797888642530290497112185488210332836596168
      Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest/run.log

        UVM_ERROR @ 20665.9 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x58)
        UVM_INFO @ 20665.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 2 failures:

  • Test flash_ctrl_rw has 1 failures.

    • 4.flash_ctrl_rw.84357949075386927290007992891015471029004771531030298497345331741978344750653
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest/run.log

        UVM_ERROR @ 1738558.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
        UVM_INFO @ 1738558.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_ro has 1 failures.

    • 10.flash_ctrl_ro.38491903048135668310199792483130317672063425701773547920442202063754969688615
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest/run.log

        UVM_ERROR @ 368317.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
        UVM_INFO @ 368317.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '$fell(src_ack_o)' has 1 failures:

  • Test flash_ctrl_hw_rma has 1 failures.

    • 0.flash_ctrl_hw_rma.108543477888399167872537683453436775446758611831615596069680155888987845875495
      Line 345, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest/run.log

            Offending '$fell(src_ack_o)'
        UVM_ERROR @ 44258634.7 ns: (prim_sync_reqack.sv:349) [ASSERT FAILED] SyncReqAckHoldReq
        UVM_INFO @ 44258634.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:

  • Test flash_ctrl_rw_derr has 1 failures.

    • 2.flash_ctrl_rw_derr.69425456615049377617785522546153395688043089922303768567579274516560182945658
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log

        UVM_ERROR @ 1337509.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002c68
        UVM_INFO @ 1337509.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_rw has 1 failures.

    • 14.flash_ctrl_rw.58215957627068127376875532095396257941520165764166003222017049839618655717173
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest/run.log

        UVM_ERROR @ 1716612.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 1716612.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *edd6_7f7ed292:ffffffff_7f7ed* mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 34.flash_ctrl_intr_rd.108093805045015601040304633859277824245730739744796847247661646455709097009972
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 75040.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    2259edd6_7f7ed292:ffffffff_7f7ed292  mismatch!!
        UVM_INFO @ 75040.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e3de78_35eadb0f:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 35.flash_ctrl_intr_rd.44659607930410304220729137416019681928841469113901970367309643946371901106696
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 8096776.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    41e3de78_35eadb0f:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 8096776.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'dst_req_o' has 1 failures:

  • Test flash_ctrl_otp_reset has 1 failures.

    • 43.flash_ctrl_otp_reset.59031203211789813013461306354130998755118812668845054616722964227467781631557
      Line 354, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest/run.log

            Offending 'dst_req_o'
        UVM_ERROR @ 63799.5 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
        UVM_INFO @ 63799.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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