FLASH_CTRL Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.303m	37.505us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.820s	55.557us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	38.860s	112.624us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.890s	212.401us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.276m	2.197ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.141m	1.762ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.750s	1.026ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.890s	212.401us	20	20	100.00
		flash_ctrl_csr_aliasing	1.141m	1.762ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.890s	30.181us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.790s	28.284us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.990s	30.046us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.069m	234.637us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.993m	334.238ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.224m	380.282ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.140s	177.247us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	44.483m	272.113ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.255m	7.976ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.361m	9.964ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.089h	49.894ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	1.975m	756.514us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	33.150s	75.271us	38	40	95.00
		flash_ctrl_rw_evict_all_en	33.540s	112.365us	40	40	100.00
		flash_ctrl_re_evict	36.670s	438.479us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.159m	2.790ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.159m	2.790ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.759m	67.455ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.710s	1.881ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	19.754m	12.340ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.780m	5.600ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.014m	376.276us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	45.968m	11.455ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.420s	18.103us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.193m	15.718ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.730s	11.478us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.510s	22.670us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	29.347m	1.856ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.112m	2.991ms	50	50	100.00
		flash_ctrl_otp_reset	2.280m	141.332us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.993m	334.238ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.010m	5.723ms	38	40	95.00
		flash_ctrl_intr_wr	1.741m	29.197ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.644m	133.580ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.934m	57.217ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.609m	3.877ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.240m	3.457ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.870s	77.784us	5	5	100.00
		flash_ctrl_ro_derr	2.820m	2.192ms	10	10	100.00
		flash_ctrl_rw_derr	4.982m	7.016ms	7	10	70.00
		flash_ctrl_derr_detect	3.989m	3.812ms	5	5	100.00
		flash_ctrl_integrity	13.748m	10.415ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.180s	44.377us	5	5	100.00
		flash_ctrl_ro_serr	3.079m	7.592ms	10	10	100.00
		flash_ctrl_rw_serr	4.288m	8.674ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.584m	897.222us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.509m	2.248ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.244m	5.904ms	20	20	100.00
		flash_ctrl_write_word_sweep	14.750s	41.260us	1	1	100.00
		flash_ctrl_read_word_sweep	14.530s	29.437us	1	1	100.00
		flash_ctrl_ro	2.478m	739.096us	20	20	100.00
		flash_ctrl_rw	11.601m	5.856ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	45.850s	345.237us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.522m	153.801ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	6.145m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.400s	41.825us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.230s	16.699us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.450s	83.807us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.450s	83.807us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	38.860s	112.624us	5	5	100.00
		flash_ctrl_csr_rw	17.890s	212.401us	20	20	100.00
		flash_ctrl_csr_aliasing	1.141m	1.762ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.440s	124.524us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	38.860s	112.624us	5	5	100.00
		flash_ctrl_csr_rw	17.890s	212.401us	20	20	100.00
		flash_ctrl_csr_aliasing	1.141m	1.762ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.440s	124.524us	20	20	100.00
V2		TOTAL			1004	1013	99.11
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.170s	13.642us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.170s	13.642us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.170s	13.642us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.170s	13.642us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.270s	36.318us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.337h	6.108ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.323m	3.247ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.323m	3.247ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.323m	3.247ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	33.040s	64.914us	3	3	100.00
		flash_ctrl_wr_intg	15.440s	162.967us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.303m	37.505us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.280m	141.332us	80	80	100.00
		flash_ctrl_disable	22.730s	11.478us	50	50	100.00
		flash_ctrl_sec_info_access	1.733m	33.971ms	50	50	100.00
		flash_ctrl_connect	16.510s	22.670us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.920s	37.397us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.890s	212.401us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.170s	13.642us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.890s	212.401us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.170s	13.642us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.890s	212.401us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.170s	13.642us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.730s	11.478us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	33.040s	64.914us	3	3	100.00
		flash_ctrl_access_after_disable	13.740s	48.894us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.780s	66.767us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.730s	11.478us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.710s	1.881ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.601m	5.856ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.288m	8.674ms	9	10	90.00
		flash_ctrl_rw_derr	4.982m	7.016ms	7	10	70.00
		flash_ctrl_integrity	13.748m	10.415ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.993m	334.238ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.108ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.108ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.108ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.337h	6.108ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	24.960s	836.103us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.500s	25.000us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.590s	190.585us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.337h	6.108ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.108ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.337h	6.108ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	47.320s	108.211us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1272	1281	99.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	50	90.91
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.31	95.74	93.97	98.31	92.52	98.27	97.18	98.18

Failure Buckets

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:

  • Test flash_ctrl_rw_derr has 3 failures.

    • 4.flash_ctrl_rw_derr.47150104395898821474616057996477847363274934663834818903488803401612964698403
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log

        UVM_ERROR @ 4587470.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00004400
        UVM_INFO @ 4587470.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.flash_ctrl_rw_derr.91523220496340667697423902453087226925494379985322763601875984968209113110014
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest/run.log

        UVM_ERROR @ 1038724.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002600
        UVM_INFO @ 1038724.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:

  • Test flash_ctrl_lcmgr_intg has 1 failures.

    • 1.flash_ctrl_lcmgr_intg.66243652706749709174984540144201376240961177183063339863144418222920847252017
      Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest/run.log

        UVM_ERROR @ 14837.3 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
        UVM_INFO @ 14837.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_rw_serr has 1 failures.

    • 8.flash_ctrl_rw_serr.114094858824265462151821036515860728016612254470995310513258501970242796971802
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log

        UVM_ERROR @ 1071868.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 1071868.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *ed38_130cacf9:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 12.flash_ctrl_intr_rd.18953412316407177550908849236330898812087698884861798110226254727505054652215
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 229281.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    8618ed38_130cacf9:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 229281.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 34.flash_ctrl_rw_evict.109842323666455188886086386865941505348616994983093870077037893540713488290846
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 25423.4 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 25423.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp b0d51a3f_cd914f5b:ffffffff_cd914f5b mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 37.flash_ctrl_intr_rd.41731319287664274751868163058657765982365502140200653012900142430163406403843
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 2148625.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    b0d51a3f_cd914f5b:ffffffff_cd914f5b  mismatch!!
        UVM_INFO @ 2148625.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 38.flash_ctrl_rw_evict.84225630339307102225885926421739727927708072513534433883729587167192867200564
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 9635.6 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 9635.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.07.30_09.44.48
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• 2024.07.28_11.10.11
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