FLASH_CTRL Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.690m	134.814us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.660s	16.402us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.580s	341.052us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.050s	97.051us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.520m	17.209ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	54.120s	2.123ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.280s	419.058us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.050s	97.051us	20	20	100.00
		flash_ctrl_csr_aliasing	54.120s	2.123ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.790s	52.922us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.870s	19.341us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.250s	23.267us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.070m	491.575us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	53.015m	1.319s	3	3	100.00
		flash_ctrl_hw_rma_reset	17.434m	380.237ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.940s	17.399us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	42.309m	229.024ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.126m	2.810ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.852m	11.262ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.195h	203.473ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.559m	706.124us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.640s	115.683us	39	40	97.50
		flash_ctrl_rw_evict_all_en	33.350s	35.379us	37	40	92.50
		flash_ctrl_re_evict	36.740s	134.466us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.766m	3.416ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.766m	3.416ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	8.042m	16.910ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.200s	2.193ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.627m	3.451ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	40.446m	46.744ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.839m	1.652ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	51.212m	1.353ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.730s	15.695us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.653m	5.611ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.610s	14.633us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.500s	109.090us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	26.003m	1.648ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.183m	11.650ms	50	50	100.00
		flash_ctrl_otp_reset	2.255m	74.842us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	53.015m	1.319s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.159m	3.243ms	39	40	97.50
		flash_ctrl_intr_wr	1.367m	8.155ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.471m	51.175ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.930m	84.307ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.501m	4.066ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.207m	947.158us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.540s	48.569us	5	5	100.00
		flash_ctrl_ro_derr	2.806m	7.926ms	10	10	100.00
		flash_ctrl_rw_derr	4.737m	8.418ms	10	10	100.00
		flash_ctrl_derr_detect	3.494m	3.606ms	5	5	100.00
		flash_ctrl_integrity	11.208m	4.317ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.060s	40.609us	5	5	100.00
		flash_ctrl_ro_serr	2.669m	1.320ms	10	10	100.00
		flash_ctrl_rw_serr	4.421m	8.064ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.280m	1.518ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.329m	1.464ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.785m	43.011ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.440s	152.293us	1	1	100.00
		flash_ctrl_read_word_sweep	14.460s	76.392us	1	1	100.00
		flash_ctrl_ro	2.224m	1.769ms	19	20	95.00
		flash_ctrl_rw	10.524m	17.393ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	42.470s	1.428ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.717m	80.352ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.659m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.900s	197.324us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.040s	32.430us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.790s	256.004us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.790s	256.004us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.580s	341.052us	5	5	100.00
		flash_ctrl_csr_rw	18.050s	97.051us	20	20	100.00
		flash_ctrl_csr_aliasing	54.120s	2.123ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.010s	206.679us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.580s	341.052us	5	5	100.00
		flash_ctrl_csr_rw	18.050s	97.051us	20	20	100.00
		flash_ctrl_csr_aliasing	54.120s	2.123ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.010s	206.679us	20	20	100.00
V2		TOTAL			1005	1013	99.21
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.860s	14.363us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.860s	14.363us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.860s	14.363us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.860s	14.363us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.040s	32.579us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.335h	2.182ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.998m	1.104ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.998m	1.104ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.998m	1.104ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.450s	188.605us	3	3	100.00
		flash_ctrl_wr_intg	15.000s	61.150us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.690m	134.814us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.255m	74.842us	80	80	100.00
		flash_ctrl_disable	22.610s	14.633us	50	50	100.00
		flash_ctrl_sec_info_access	1.573m	20.578ms	50	50	100.00
		flash_ctrl_connect	16.500s	109.090us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.930s	131.812us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.050s	97.051us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	14.363us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.050s	97.051us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	14.363us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.050s	97.051us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	14.363us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.610s	14.633us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.450s	188.605us	3	3	100.00
		flash_ctrl_access_after_disable	13.990s	21.392us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.900s	78.093us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.610s	14.633us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.200s	2.193ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.524m	17.393ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.421m	8.064ms	9	10	90.00
		flash_ctrl_rw_derr	4.737m	8.418ms	10	10	100.00
		flash_ctrl_integrity	11.208m	4.317ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	53.015m	1.319s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.335h	2.182ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.335h	2.182ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.335h	2.182ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.335h	2.182ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.210s	914.644us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.370s	26.340us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.240s	15.815us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.335h	2.182ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.335h	2.182ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.335h	2.182ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.440s	65.384us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1272	1281	99.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	49	89.09
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.96	95.24	93.94	98.31	91.84	97.16	96.99	98.21

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 4 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 4.flash_ctrl_rw_evict.92552684320909718197033574438784493792960575374340809094301131799528624674418
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 35526.3 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 35526.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict_all_en has 3 failures.
  - 28.flash_ctrl_rw_evict_all_en.74290313472250950433719498638025459169646058425115256595237806827411670168608
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 40187.3 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 40187.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.flash_ctrl_rw_evict_all_en.3993439456046492190587134520861814212576525896958962169584864686011928920405
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 8004.2 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 8004.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 4.flash_ctrl_rw_serr.15876746243040668936574327076779897017683051608383427012049373588339727119049
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 1514488.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1514488.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw has 1 failures.
  - 8.flash_ctrl_rw.32082675322315181744596383659180002099419372471325291285606709695543301640947
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 320523.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 320523.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 1.flash_ctrl_phy_ack_consistency.103869275794678993312566510002116457740158144049692534606076876931990138212938
    Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 10239.4 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x3)
  UVM_INFO @ 10239.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp b8dda33b_ad11a790:ffffffff_ad11a* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 2.flash_ctrl_intr_rd.76751694927154514346539801290640844880736763858264370818944614006716070354388
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 857286.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    b8dda33b_ad11a790:ffffffff_ad11a790  mismatch!!
  UVM_INFO @ 857286.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 11.flash_ctrl_ro.47216150402573589463083672753639964853763990822013460365926110477335130722285
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 6460.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 6460.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e9b7e615a7`