FLASH_CTRL Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.661m	29.460us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.710s	14.884us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.800s	406.392us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.630s	113.739us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.403m	3.410ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.110m	7.124ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.200s	108.159us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.630s	113.739us	20	20	100.00
		flash_ctrl_csr_aliasing	1.110m	7.124ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.290s	16.630us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.890s	16.430us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.670s	351.691us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.017m	273.642us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.408m	129.714ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.671m	160.193ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.800s	25.935us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.032m	282.344ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	6.135m	2.847ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.704m	2.728ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.229h	203.470ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.072m	5.639ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.520s	47.202us	40	40	100.00
		flash_ctrl_rw_evict_all_en	31.800s	57.856us	39	40	97.50
		flash_ctrl_re_evict	36.300s	141.233us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.673m	29.094ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.673m	29.094ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.843m	107.883ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	31.010s	2.344ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.122m	867.456us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	45.165m	52.531ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.428m	747.530us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	48.721m	1.114ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.850s	17.064us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.430m	6.020ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.670s	20.489us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.350s	15.372us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.850m	6.284ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.133m	9.393ms	50	50	100.00
		flash_ctrl_otp_reset	2.246m	39.294us	79	80	98.75
V2	isolation_partition	flash_ctrl_hw_rma	36.408m	129.714ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.705m	10.906ms	39	40	97.50
		flash_ctrl_intr_wr	1.625m	26.374ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.283m	26.473ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.607m	142.857ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.644m	23.154ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.233m	1.287ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.110s	64.792us	5	5	100.00
		flash_ctrl_ro_derr	2.782m	4.051ms	10	10	100.00
		flash_ctrl_rw_derr	4.985m	5.561ms	10	10	100.00
		flash_ctrl_derr_detect	3.548m	3.420ms	5	5	100.00
		flash_ctrl_integrity	11.691m	5.897ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.520s	96.371us	5	5	100.00
		flash_ctrl_ro_serr	2.606m	1.072ms	10	10	100.00
		flash_ctrl_rw_serr	4.268m	8.721ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.447m	764.265us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.461m	957.742us	5	5	100.00
V2	scramble	flash_ctrl_wo	4.113m	53.928ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.650s	143.063us	1	1	100.00
		flash_ctrl_read_word_sweep	14.370s	47.234us	1	1	100.00
		flash_ctrl_ro	2.368m	4.127ms	20	20	100.00
		flash_ctrl_rw	12.426m	18.356ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	43.490s	327.744us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.935m	262.269ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.880m	10.019ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.500s	76.980us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.020s	29.004us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.090s	684.588us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.090s	684.588us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.800s	406.392us	5	5	100.00
		flash_ctrl_csr_rw	17.630s	113.739us	20	20	100.00
		flash_ctrl_csr_aliasing	1.110m	7.124ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.940s	235.761us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.800s	406.392us	5	5	100.00
		flash_ctrl_csr_rw	17.630s	113.739us	20	20	100.00
		flash_ctrl_csr_aliasing	1.110m	7.124ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.940s	235.761us	20	20	100.00
V2		TOTAL			1008	1013	99.51
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.240s	22.283us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.240s	22.283us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.240s	22.283us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.240s	22.283us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.130s	14.379us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.369h	10.647ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.161m	7.917ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.161m	7.917ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.161m	7.917ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.070s	299.370us	3	3	100.00
		flash_ctrl_wr_intg	15.110s	70.980us	2	3	66.67
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.661m	29.460us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.246m	39.294us	79	80	98.75
		flash_ctrl_disable	22.670s	20.489us	50	50	100.00
		flash_ctrl_sec_info_access	1.447m	23.939ms	50	50	100.00
		flash_ctrl_connect	16.350s	15.372us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.970s	76.092us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.630s	113.739us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.240s	22.283us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.630s	113.739us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.240s	22.283us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.630s	113.739us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.240s	22.283us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.670s	20.489us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.070s	299.370us	3	3	100.00
		flash_ctrl_access_after_disable	13.770s	17.321us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.630s	27.186us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.670s	20.489us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	31.010s	2.344ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.426m	18.356ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.268m	8.721ms	9	10	90.00
		flash_ctrl_rw_derr	4.985m	5.561ms	10	10	100.00
		flash_ctrl_integrity	11.691m	5.897ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.408m	129.714ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.369h	10.647ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.369h	10.647ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.369h	10.647ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.369h	10.647ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.340s	791.221us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.080s	24.206us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	13.810s	16.739us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.369h	10.647ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.369h	10.647ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.369h	10.647ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.520s	859.103us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1275	1281	99.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	50	90.91
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.28	95.74	94.04	98.31	92.52	98.29	96.89	98.18

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:

  • Test flash_ctrl_rw_serr has 1 failures.

    • 5.flash_ctrl_rw_serr.81320475745897432103634754875217863630627297347818654420906452216139171764992
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log

        UVM_ERROR @ 482983.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 482983.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw has 1 failures.

    • 12.flash_ctrl_rw.113263498157367701695665517238676903134417008731895416266427390978513900793820
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest/run.log

        UVM_ERROR @ 1884601.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 1884601.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank0] *: obs:exp *_*_422f7fd9_cf98142f:3e_*_e9de9e1e_9480dc* mismatch!! has 1 failures:

  • Test flash_ctrl_wr_intg has 1 failures.

    • 2.flash_ctrl_wr_intg.24773705069265929949812319870067176892065168521285523218798013678007129320831
      Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest/run.log

        UVM_ERROR @ 22307.8 ns: (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank0]    0: obs:exp    32_3_422f7fd9_cf98142f:3e_3_e9de9e1e_9480dc35  mismatch!!
        UVM_INFO @ 22307.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp ab972c98_11836e7f:ffffffff_11836e7f mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 35.flash_ctrl_intr_rd.50044925640816660318067131560952822961452373367241779266087406365374401509454
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 9527490.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    ab972c98_11836e7f:ffffffff_11836e7f  mismatch!!
        UVM_INFO @ 9527490.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 36.flash_ctrl_rw_evict_all_en.105248111571513045130490819986972821629769851022370596331293919353777734983454
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 54076.7 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 54076.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'dst_req_o' has 1 failures:

  • Test flash_ctrl_otp_reset has 1 failures.

    • 76.flash_ctrl_otp_reset.26056308404100782574892519445706081293733427796094747571375970999928598639381
      Line 382, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest/run.log

            Offending 'dst_req_o'
        UVM_ERROR @ 20857.6 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
        UVM_INFO @ 20857.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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