FLASH_CTRL Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.687m	31.137us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.290s	16.804us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	44.850s	87.646us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.580s	109.557us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.176m	5.843ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.117m	4.798ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.950s	178.444us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.580s	109.557us	20	20	100.00
		flash_ctrl_csr_aliasing	1.117m	4.798ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.510s	15.493us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.650s	16.683us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.920s	247.503us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.084m	98.258us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	41.795m	1.590s	2	3	66.67
		flash_ctrl_hw_rma_reset	20.656m	380.326ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.860s	34.199us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	37.388m	325.920ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.245m	2.130ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.367m	4.587ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	53.889m	378.487ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.103m	5.523ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.370s	243.031us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.630s	122.039us	38	40	95.00
		flash_ctrl_re_evict	36.870s	112.355us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.531m	10.749ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.531m	10.749ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.523m	189.787ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.200s	1.061ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	18.684m	4.615ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.214m	99.922ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.426m	1.786ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.863m	1.125ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.980s	26.917us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.700m	24.462ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.980s	56.355us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.480s	13.816us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	27.158m	887.537us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.953m	6.020ms	50	50	100.00
		flash_ctrl_otp_reset	2.248m	38.522us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	41.795m	1.590s	2	3	66.67
V2	interrupts	flash_ctrl_intr_rd	4.590m	3.519ms	38	40	95.00
		flash_ctrl_intr_wr	1.256m	5.049ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.228m	115.091ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.474m	130.587ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.540m	2.431ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.210m	3.041ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.750s	32.150us	5	5	100.00
		flash_ctrl_ro_derr	2.923m	1.137ms	10	10	100.00
		flash_ctrl_rw_derr	4.947m	26.262ms	10	10	100.00
		flash_ctrl_derr_detect	3.685m	1.158ms	5	5	100.00
		flash_ctrl_integrity	12.748m	4.647ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.010s	60.081us	5	5	100.00
		flash_ctrl_ro_serr	2.747m	1.470ms	10	10	100.00
		flash_ctrl_rw_serr	4.242m	6.589ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.542m	14.134ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.605m	4.438ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.133m	24.281ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.470s	136.111us	1	1	100.00
		flash_ctrl_read_word_sweep	14.300s	45.448us	1	1	100.00
		flash_ctrl_ro	2.362m	2.088ms	20	20	100.00
		flash_ctrl_rw	11.732m	18.233ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	43.840s	712.101us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.212m	41.319ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.585m	10.023ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.610s	95.007us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.250s	114.316us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.320s	1.145ms	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.320s	1.145ms	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	44.850s	87.646us	5	5	100.00
		flash_ctrl_csr_rw	17.580s	109.557us	20	20	100.00
		flash_ctrl_csr_aliasing	1.117m	4.798ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.840s	209.142us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	44.850s	87.646us	5	5	100.00
		flash_ctrl_csr_rw	17.580s	109.557us	20	20	100.00
		flash_ctrl_csr_aliasing	1.117m	4.798ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.840s	209.142us	20	20	100.00
V2		TOTAL			1007	1013	99.41
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.990s	11.855us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.990s	11.855us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.990s	11.855us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.990s	11.855us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.770s	21.238us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.372h	5.343ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.077m	4.323ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.077m	4.323ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.077m	4.323ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.550s	63.192us	3	3	100.00
		flash_ctrl_wr_intg	15.140s	86.828us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.687m	31.137us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.248m	38.522us	80	80	100.00
		flash_ctrl_disable	22.980s	56.355us	50	50	100.00
		flash_ctrl_sec_info_access	1.563m	35.579ms	50	50	100.00
		flash_ctrl_connect	16.480s	13.816us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.130s	33.680us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.580s	109.557us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.990s	11.855us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.580s	109.557us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.990s	11.855us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.580s	109.557us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.990s	11.855us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.980s	56.355us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.550s	63.192us	3	3	100.00
		flash_ctrl_access_after_disable	14.020s	25.271us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.490s	26.766us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.980s	56.355us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.200s	1.061ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.732m	18.233ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.242m	6.589ms	10	10	100.00
		flash_ctrl_rw_derr	4.947m	26.262ms	10	10	100.00
		flash_ctrl_integrity	12.748m	4.647ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	41.795m	1.590s	2	3	66.67
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.372h	5.343ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.372h	5.343ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.372h	5.343ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.372h	5.343ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.900s	715.211us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.050s	15.313us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.060s	73.198us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.372h	5.343ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.372h	5.343ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.372h	5.343ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.880s	188.074us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1275	1281	99.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	51	92.73
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.24	95.73	93.83	98.31	92.52	98.23	96.89	98.15

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:

  • Test flash_ctrl_rw_evict_all_en has 2 failures.

    • 19.flash_ctrl_rw_evict_all_en.31576975794365227054335099536108812659867077409887837792991792838594831238759
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 206452.7 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 206452.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.flash_ctrl_rw_evict_all_en.35234781866270709694671025190275815861420742311803806948423657388584808513830
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 12668.0 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 12668.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '$fell(src_ack_o)' has 1 failures:

  • Test flash_ctrl_hw_rma has 1 failures.

    • 1.flash_ctrl_hw_rma.26842647934179786215406702613283920496546831444229203394757576281127621875764
      Line 358, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest/run.log

            Offending '$fell(src_ack_o)'
        UVM_ERROR @ 210470261.7 ns: (prim_sync_reqack.sv:349) [ASSERT FAILED] SyncReqAckHoldReq
        UVM_INFO @ 210470261.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 10.flash_ctrl_rw_evict.63458937971928043546639510536688827984512423557421614661783716778308487742662
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 24581.2 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 24581.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e09ae4d_ba8beb0b:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 15.flash_ctrl_intr_rd.35192239843499729805843681572291119012404256624074753768270874838342616230177
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 11003340.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    8e09ae4d_ba8beb0b:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 11003340.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *c59cb_52915f89:ffffffff_52915f* mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 35.flash_ctrl_intr_rd.30760795681666929689255901066830338620689790169818113187803488219133208172465
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 2054250.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    716c59cb_52915f89:ffffffff_52915f89  mismatch!!
        UVM_INFO @ 2054250.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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