FLASH_CTRL Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.247m	691.986us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.490s	30.090us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.170s	157.538us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.170s	758.946us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.513m	7.811ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.110m	6.410ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.770s	85.034us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.170s	758.946us	20	20	100.00
		flash_ctrl_csr_aliasing	1.110m	6.410ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.590s	17.422us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.840s	17.128us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.870s	52.561us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.073m	66.573us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.224m	552.295ms	3	3	100.00
		flash_ctrl_hw_rma_reset	25.077m	630.424ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.850s	17.624us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	41.058m	238.850ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.309m	9.313ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.691m	6.415ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.164h	195.638ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.452m	719.320us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.100s	32.870us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.320s	68.348us	38	40	95.00
		flash_ctrl_re_evict	36.170s	75.824us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.717m	2.900ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.717m	2.900ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.474m	101.159ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	31.240s	6.894ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	16.842m	183.310us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	38.976m	3.800ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.203m	709.816us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.474m	851.745us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.780s	15.167us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.683m	6.530ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.710s	92.420us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.640s	16.131us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	23.841m	310.546us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.156m	12.963ms	50	50	100.00
		flash_ctrl_otp_reset	2.264m	281.634us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.224m	552.295ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.621m	1.627ms	39	40	97.50
		flash_ctrl_intr_wr	1.500m	8.807ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.881m	121.542ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.888m	373.595ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.697m	16.146ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.291m	4.030ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.420s	60.311us	5	5	100.00
		flash_ctrl_ro_derr	2.875m	1.335ms	10	10	100.00
		flash_ctrl_rw_derr	4.609m	7.219ms	10	10	100.00
		flash_ctrl_derr_detect	3.725m	1.091ms	5	5	100.00
		flash_ctrl_integrity	10.782m	34.400ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.990s	25.431us	5	5	100.00
		flash_ctrl_ro_serr	2.674m	10.606ms	10	10	100.00
		flash_ctrl_rw_serr	4.380m	4.920ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.601m	2.064ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.855m	1.513ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.059m	11.576ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.580s	108.267us	1	1	100.00
		flash_ctrl_read_word_sweep	14.520s	87.278us	1	1	100.00
		flash_ctrl_ro	2.349m	2.341ms	20	20	100.00
		flash_ctrl_rw	11.003m	8.106ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	41.050s	328.223us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.226m	265.298ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.530m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.380s	89.715us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.980s	45.649us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.760s	247.420us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.760s	247.420us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.170s	157.538us	5	5	100.00
		flash_ctrl_csr_rw	18.170s	758.946us	20	20	100.00
		flash_ctrl_csr_aliasing	1.110m	6.410ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	37.010s	958.096us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.170s	157.538us	5	5	100.00
		flash_ctrl_csr_rw	18.170s	758.946us	20	20	100.00
		flash_ctrl_csr_aliasing	1.110m	6.410ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	37.010s	958.096us	20	20	100.00
V2		TOTAL			1007	1013	99.41
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.530s	50.548us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.530s	50.548us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.530s	50.548us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.530s	50.548us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.020s	14.654us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.376h	8.345ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.266m	3.077ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.266m	3.077ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.266m	3.077ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	29.690s	229.495us	3	3	100.00
		flash_ctrl_wr_intg	15.100s	46.697us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.247m	691.986us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.264m	281.634us	80	80	100.00
		flash_ctrl_disable	22.710s	92.420us	50	50	100.00
		flash_ctrl_sec_info_access	1.529m	8.664ms	50	50	100.00
		flash_ctrl_connect	17.640s	16.131us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.100s	70.820us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.170s	758.946us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.530s	50.548us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.170s	758.946us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.530s	50.548us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.170s	758.946us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.530s	50.548us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.710s	92.420us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	29.690s	229.495us	3	3	100.00
		flash_ctrl_access_after_disable	13.710s	40.018us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.870s	39.519us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.710s	92.420us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	31.240s	6.894ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.003m	8.106ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.380m	4.920ms	9	10	90.00
		flash_ctrl_rw_derr	4.609m	7.219ms	10	10	100.00
		flash_ctrl_integrity	10.782m	34.400ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.224m	552.295ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.376h	8.345ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.376h	8.345ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.376h	8.345ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.376h	8.345ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.630s	726.045us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.190s	16.089us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	13.810s	45.359us	3	5	60.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.376h	8.345ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.376h	8.345ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.376h	8.345ms	5	5	100.00
V2S		TOTAL			145	147	98.64
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.770s	187.820us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1281	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	50	90.91
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.94	95.25	93.96	98.31	91.84	97.21	96.89	98.12

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 8.flash_ctrl_rw_evict.48735117090724072425463558656387753374742369708044125313174107320125882360692
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 58497.0 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 58497.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw_evict_all_en has 2 failures.

    • 16.flash_ctrl_rw_evict_all_en.69172908389857362778808539321493066699464464821863392968277979589467905378249
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 9419.2 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 9419.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.flash_ctrl_rw_evict_all_en.45736957003162452392380394468217275708468071487420576920099253710047167819485
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 23543.9 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 23543.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:

  • Test flash_ctrl_rw has 1 failures.

    • 0.flash_ctrl_rw.20778177365310126622664803009300085284984798475907451626610538464167560479126
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest/run.log

        UVM_ERROR @ 735972.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 735972.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw_serr has 1 failures.

    • 2.flash_ctrl_rw_serr.2409250038197840853679625496058721961430664210545577744440298576304999718777
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log

        UVM_ERROR @ 5666423.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 5666423.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 2 failures:

  • Test flash_ctrl_phy_ack_consistency has 2 failures.

    • 1.flash_ctrl_phy_ack_consistency.104643282710525279196866728170731226683909568076336006491783971276630854736672
      Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log

        UVM_ERROR @ 5134.2 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x4b)
        UVM_INFO @ 5134.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.flash_ctrl_phy_ack_consistency.100679679099434396061224615922778643369748498067078312639099696626151514381258
      Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest/run.log

        UVM_ERROR @ 60917.0 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x2)
        UVM_INFO @ 60917.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *eeddc5_e8ebedc9:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 2.flash_ctrl_intr_rd.99984343579060457028553356600130451012804900412271001843860616979559061326268
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 4777181.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    89eeddc5_e8ebedc9:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 4777181.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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