FLASH_CTRL Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.655m	32.260us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.200s	25.738us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.440s	44.480us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.030s	216.025us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.277m	11.650ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	58.460s	5.021ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.510s	83.106us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.030s	216.025us	20	20	100.00
		flash_ctrl_csr_aliasing	58.460s	5.021ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.730s	14.733us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.880s	69.261us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.920s	22.365us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.081m	66.209us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	31.684m	105.171ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.864m	320.275ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.040s	84.606us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	44.268m	250.788ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.135m	2.812ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.189m	52.225ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.267h	97.826ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.582m	3.687ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.230s	252.119us	38	40	95.00
		flash_ctrl_rw_evict_all_en	33.170s	150.362us	37	40	92.50
		flash_ctrl_re_evict	36.500s	145.701us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	7.801m	2.865ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	7.801m	2.865ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	22.379m	45.891ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	31.310s	1.125ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	25.987m	1.594ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.477m	10.302ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.988m	942.392us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.038m	975.554us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.040s	64.606us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.069m	28.368ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.830s	16.625us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.570s	18.649us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.572m	1.791ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.532m	3.179ms	50	50	100.00
		flash_ctrl_otp_reset	2.245m	68.146us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	31.684m	105.171ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.400m	3.648ms	39	40	97.50
		flash_ctrl_intr_wr	1.568m	47.238ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.924m	12.307ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.022m	95.474ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.583m	3.875ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.192m	658.921us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.650s	59.240us	5	5	100.00
		flash_ctrl_ro_derr	2.972m	2.973ms	10	10	100.00
		flash_ctrl_rw_derr	4.134m	3.148ms	10	10	100.00
		flash_ctrl_derr_detect	3.620m	1.333ms	5	5	100.00
		flash_ctrl_integrity	11.371m	3.844ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.060s	46.569us	5	5	100.00
		flash_ctrl_ro_serr	2.772m	1.504ms	10	10	100.00
		flash_ctrl_rw_serr	4.040m	1.868ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.323m	1.419ms	4	5	80.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.600m	3.196ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.669m	12.875ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.320s	80.695us	1	1	100.00
		flash_ctrl_read_word_sweep	13.920s	24.230us	1	1	100.00
		flash_ctrl_ro	2.267m	574.498us	20	20	100.00
		flash_ctrl_rw	10.513m	13.618ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	42.850s	2.593ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.722m	166.582ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.250m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.540s	171.807us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.080s	28.066us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.340s	134.821us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.340s	134.821us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.440s	44.480us	5	5	100.00
		flash_ctrl_csr_rw	18.030s	216.025us	20	20	100.00
		flash_ctrl_csr_aliasing	58.460s	5.021ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.040s	373.328us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.440s	44.480us	5	5	100.00
		flash_ctrl_csr_rw	18.030s	216.025us	20	20	100.00
		flash_ctrl_csr_aliasing	58.460s	5.021ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.040s	373.328us	20	20	100.00
V2		TOTAL			1003	1013	99.01
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.510s	24.340us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.510s	24.340us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.510s	24.340us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.510s	24.340us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.180s	27.795us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.367h	1.597ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.158m	352.577us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.158m	352.577us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.158m	352.577us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.260s	63.542us	3	3	100.00
		flash_ctrl_wr_intg	15.330s	386.368us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.655m	32.260us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.245m	68.146us	80	80	100.00
		flash_ctrl_disable	22.830s	16.625us	50	50	100.00
		flash_ctrl_sec_info_access	1.703m	31.731ms	50	50	100.00
		flash_ctrl_connect	16.570s	18.649us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.170s	33.685us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.030s	216.025us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.510s	24.340us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.030s	216.025us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.510s	24.340us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.030s	216.025us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.510s	24.340us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.830s	16.625us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.260s	63.542us	3	3	100.00
		flash_ctrl_access_after_disable	14.220s	13.874us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	28.410s	63.715us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.830s	16.625us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	31.310s	1.125ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.513m	13.618ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.040m	1.868ms	10	10	100.00
		flash_ctrl_rw_derr	4.134m	3.148ms	10	10	100.00
		flash_ctrl_integrity	11.371m	3.844ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	31.684m	105.171ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.367h	1.597ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.367h	1.597ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.367h	1.597ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.367h	1.597ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	24.460s	895.909us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.070s	47.770us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.230s	49.941us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.367h	1.597ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.367h	1.597ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.367h	1.597ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.900s	128.970us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1271	1281	99.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	48	87.27
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.27	95.70	94.00	98.31	92.52	98.21	96.89	98.24

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 4 failures:

Test flash_ctrl_rw_evict has 2 failures.

11.flash_ctrl_rw_evict.10330154710451619041564436157763772090668293567797486374141669201398146177188
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 52188.7 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 52188.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.flash_ctrl_rw_evict.76263824829673601880285985081180171578897192932583972955527698636390620749961
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 40695.9 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 40695.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_evict_all_en has 2 failures.

25.flash_ctrl_rw_evict_all_en.69437034714895243933989848016525534265213925949007318226848830183971174165614
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 43793.1 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 43793.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.flash_ctrl_rw_evict_all_en.98474644362579398939067396101439588822244166063109630535235904271642623563255
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 39505.2 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 39505.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_serr_counter has 1 failures.
  - 4.flash_ctrl_serr_counter.70594382312213293212654545819324498321445475204532013333779120163831392453089
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest/run.log
```
  UVM_ERROR @ 1278942.8 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1278942.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw has 1 failures.
  - 14.flash_ctrl_rw.101342798162898454969967562335363219519653663186895940611468167850519410538536
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 1489693.0 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1489693.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 3.flash_ctrl_oversize_error.68395865975214163365595312562349071260553413045972200601390799346634328819842
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 325606.4 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 325606.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp f76ac398_c0903c07:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 3.flash_ctrl_intr_rd.115353119693736317980991153921787288046562662695055547548411599636853008713411
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1446024.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    f76ac398_c0903c07:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1446024.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
- Test flash_ctrl_lcmgr_intg has 1 failures.
  - 6.flash_ctrl_lcmgr_intg.28734856463699433725950680459442698397336514283408154961898720050545770516949
    Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 28618.4 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 28618.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:199) [flash_ctrl_rw_evict_vseq] Check failed (!address_in_words(bank, part, addr)) Overwriting address * in part FlashPartInfo has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 8.flash_ctrl_rw_evict_all_en.35711861427928231539994075347139904310585228168862281849642104629259064397237
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_FATAL @ 12484.3 ns: (flash_ctrl_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_in_words(bank, part, addr)) Overwriting address 0x00002100 in part FlashPartInfo
  UVM_INFO @ 12484.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```