FLASH_CTRL Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.628m	249.696us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.340s	13.791us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.210s	45.908us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.110s	252.104us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.387m	9.563ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	59.010s	1.263ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.410s	491.875us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.110s	252.104us	20	20	100.00
		flash_ctrl_csr_aliasing	59.010s	1.263ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.670s	18.005us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.750s	32.034us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.640s	22.984us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.865m	122.759us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.416m	337.791ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.379m	160.181ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.800s	95.667us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.294m	291.951ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.035m	3.078ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.532m	2.646ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.237h	50.873ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.881m	1.655ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.520s	77.683us	40	40	100.00
		flash_ctrl_rw_evict_all_en	32.160s	30.563us	40	40	100.00
		flash_ctrl_re_evict	36.500s	104.351us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.595m	2.684ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.595m	2.684ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.285m	15.440ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	25.630s	523.441us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	18.403m	2.961ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.697m	41.529ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.164m	444.547us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	39.243m	1.299ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.780s	47.388us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.682m	12.979ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.010s	14.386us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.480s	15.542us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	22.402m	1.868ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	5.131m	44.494ms	50	50	100.00
		flash_ctrl_otp_reset	2.281m	136.924us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	36.416m	337.791ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.308m	1.657ms	38	40	95.00
		flash_ctrl_intr_wr	1.246m	2.442ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.097m	12.264ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.274m	93.006ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.585m	4.056ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.232m	814.871us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.650s	94.080us	5	5	100.00
		flash_ctrl_ro_derr	3.107m	7.342ms	10	10	100.00
		flash_ctrl_rw_derr	4.702m	23.636ms	10	10	100.00
		flash_ctrl_derr_detect	3.367m	2.970ms	5	5	100.00
		flash_ctrl_integrity	11.327m	17.150ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.860s	83.769us	5	5	100.00
		flash_ctrl_ro_serr	2.671m	11.240ms	10	10	100.00
		flash_ctrl_rw_serr	4.626m	6.153ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.848m	1.071ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.330m	2.017ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.822m	10.965ms	20	20	100.00
		flash_ctrl_write_word_sweep	14.950s	73.783us	1	1	100.00
		flash_ctrl_read_word_sweep	14.720s	174.760us	1	1	100.00
		flash_ctrl_ro	2.436m	1.381ms	20	20	100.00
		flash_ctrl_rw	11.784m	17.460ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	41.820s	703.993us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.109m	166.637ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.435m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.650s	402.158us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.100s	16.978us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.250s	255.896us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.250s	255.896us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.210s	45.908us	5	5	100.00
		flash_ctrl_csr_rw	18.110s	252.104us	20	20	100.00
		flash_ctrl_csr_aliasing	59.010s	1.263ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.910s	881.664us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.210s	45.908us	5	5	100.00
		flash_ctrl_csr_rw	18.110s	252.104us	20	20	100.00
		flash_ctrl_csr_aliasing	59.010s	1.263ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.910s	881.664us	20	20	100.00
V2		TOTAL			1009	1013	99.61
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.880s	43.826us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.880s	43.826us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.880s	43.826us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.880s	43.826us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.680s	11.673us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.363h	3.938ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.197m	5.064ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.197m	5.064ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.197m	5.064ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.640s	207.368us	3	3	100.00
		flash_ctrl_wr_intg	15.320s	579.370us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.628m	249.696us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.281m	136.924us	80	80	100.00
		flash_ctrl_disable	23.010s	14.386us	50	50	100.00
		flash_ctrl_sec_info_access	1.831m	35.159ms	50	50	100.00
		flash_ctrl_connect	16.480s	15.542us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.020s	83.521us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.110s	252.104us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.880s	43.826us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.110s	252.104us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.880s	43.826us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.110s	252.104us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.880s	43.826us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.010s	14.386us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.640s	207.368us	3	3	100.00
		flash_ctrl_access_after_disable	13.900s	23.134us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	30.850s	27.691us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.010s	14.386us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	25.630s	523.441us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.784m	17.460ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.626m	6.153ms	10	10	100.00
		flash_ctrl_rw_derr	4.702m	23.636ms	10	10	100.00
		flash_ctrl_integrity	11.327m	17.150ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.416m	337.791ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.363h	3.938ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.363h	3.938ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.363h	3.938ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.363h	3.938ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.250s	777.989us	4	5	80.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.400s	67.015us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	16.380s	47.608us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.363h	3.938ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.363h	3.938ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.363h	3.938ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.410s	198.249us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1276	1281	99.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	52	94.55
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	95.23	93.81	98.31	92.52	97.12	96.89	98.15

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_phy_arb_redun has 1 failures.

    • 0.flash_ctrl_phy_arb_redun.48565370674045559175960658679230053551156101368898084636176006490682229958934
      Line 286, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest/run.log

        UVM_ERROR @ 10967.2 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
        UVM_INFO @ 10967.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *a2ea67c_6b6d1d8b:ffffffff_6b6d1d8b mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 1.flash_ctrl_intr_rd.21891434652949981602020450769604627224690437654774531818851666406820974173108
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 19406806.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    7a2ea67c_6b6d1d8b:ffffffff_6b6d1d8b  mismatch!!
        UVM_INFO @ 19406806.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:

  • Test flash_ctrl_integrity has 1 failures.

    • 4.flash_ctrl_integrity.43309650019505747847249882922504088167142205856339896716936369106882889358188
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log

        UVM_ERROR @ 2016251.3 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003a20
        UVM_INFO @ 2016251.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_rw has 1 failures.

    • 7.flash_ctrl_rw.53887352305006582614303498701597934542207427078793160218201409295843130135127
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest/run.log

        UVM_ERROR @ 3418831.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 3418831.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp ddb484e8_b7eabbac:ffffffff_b7eabbac mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 38.flash_ctrl_intr_rd.114151151354486464153428386139683137286441993679062214365458591003375657960167
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 994706.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    4: obs:exp    ddb484e8_b7eabbac:ffffffff_b7eabbac  mismatch!!
        UVM_INFO @ 994706.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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