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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.20 95.74 94.03 98.31 91.84 98.34 96.89 98.24


Total test records in report: 1271
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T487 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.2259512716 Sep 09 05:53:09 PM UTC 24 Sep 09 05:57:09 PM UTC 24 1786141300 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.159110764 Sep 09 05:55:49 PM UTC 24 Sep 09 05:57:20 PM UTC 24 10035434900 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2668328284 Sep 09 05:53:51 PM UTC 24 Sep 09 05:57:27 PM UTC 24 5188494400 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1353395887 Sep 09 05:54:31 PM UTC 24 Sep 09 05:57:31 PM UTC 24 5942326000 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.2936939876 Sep 09 05:49:22 PM UTC 24 Sep 09 05:57:37 PM UTC 24 4453060200 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1117612610 Sep 09 05:54:35 PM UTC 24 Sep 09 05:57:52 PM UTC 24 35499698200 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.2145828929 Sep 09 05:54:41 PM UTC 24 Sep 09 05:57:59 PM UTC 24 4654789800 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3328679513 Sep 09 05:53:54 PM UTC 24 Sep 09 05:58:00 PM UTC 24 789353400 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.733941178 Sep 09 05:56:38 PM UTC 24 Sep 09 05:58:04 PM UTC 24 1264660300 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.3076158832 Sep 09 05:56:08 PM UTC 24 Sep 09 05:58:18 PM UTC 24 2480044800 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.302321037 Sep 09 05:58:01 PM UTC 24 Sep 09 05:58:31 PM UTC 24 59546900 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.1419962939 Sep 09 05:56:40 PM UTC 24 Sep 09 05:58:41 PM UTC 24 635038200 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.1092185872 Sep 09 05:51:48 PM UTC 24 Sep 09 05:58:49 PM UTC 24 5572289400 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.2847986919 Sep 09 05:58:19 PM UTC 24 Sep 09 05:58:59 PM UTC 24 26479700 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.1059387671 Sep 09 05:58:05 PM UTC 24 Sep 09 05:59:06 PM UTC 24 47033600 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.55109980 Sep 09 05:41:37 PM UTC 24 Sep 09 05:59:18 PM UTC 24 545301200 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.4180569235 Sep 09 05:58:31 PM UTC 24 Sep 09 05:59:21 PM UTC 24 82409400 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.202289730 Sep 09 05:58:41 PM UTC 24 Sep 09 05:59:21 PM UTC 24 22103100 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.1443581412 Sep 09 05:57:08 PM UTC 24 Sep 09 05:59:22 PM UTC 24 2823591600 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.2126581827 Sep 09 05:56:03 PM UTC 24 Sep 09 05:59:30 PM UTC 24 39101900 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.4271096752 Sep 09 05:57:10 PM UTC 24 Sep 09 05:59:31 PM UTC 24 4434069300 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1591169371 Sep 09 05:57:38 PM UTC 24 Sep 09 05:59:33 PM UTC 24 15805786500 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1042200335 Sep 09 05:59:07 PM UTC 24 Sep 09 05:59:33 PM UTC 24 15666600 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.3087608581 Sep 09 05:59:00 PM UTC 24 Sep 09 05:59:33 PM UTC 24 15213800 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3658981865 Sep 09 05:59:19 PM UTC 24 Sep 09 05:59:39 PM UTC 24 26183200 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.1103027641 Sep 09 05:59:22 PM UTC 24 Sep 09 05:59:45 PM UTC 24 121483700 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.2406727434 Sep 09 05:56:40 PM UTC 24 Sep 09 05:59:56 PM UTC 24 18318806500 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.1827735637 Sep 09 05:56:11 PM UTC 24 Sep 09 05:59:57 PM UTC 24 87478700 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.99970491 Sep 09 05:57:53 PM UTC 24 Sep 09 06:00:21 PM UTC 24 5970022300 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.529507818 Sep 09 05:32:54 PM UTC 24 Sep 09 06:00:26 PM UTC 24 85361786500 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2601039412 Sep 09 05:59:46 PM UTC 24 Sep 09 06:00:29 PM UTC 24 3817950300 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3855240080 Sep 09 05:58:51 PM UTC 24 Sep 09 06:00:30 PM UTC 24 2641756800 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.2123802205 Sep 09 05:57:28 PM UTC 24 Sep 09 06:00:35 PM UTC 24 25366643900 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.2301098729 Sep 09 05:57:21 PM UTC 24 Sep 09 06:00:38 PM UTC 24 791494000 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3388062934 Sep 09 05:58:01 PM UTC 24 Sep 09 06:00:53 PM UTC 24 33905370200 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.987385650 Sep 09 05:57:32 PM UTC 24 Sep 09 06:00:55 PM UTC 24 2831312800 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2049090749 Sep 09 05:56:03 PM UTC 24 Sep 09 06:00:58 PM UTC 24 42884400 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2956824058 Sep 09 05:59:22 PM UTC 24 Sep 09 06:01:01 PM UTC 24 38403200 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.609416205 Sep 09 05:46:16 PM UTC 24 Sep 09 06:01:05 PM UTC 24 100158715100 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.623204253 Sep 09 05:46:32 PM UTC 24 Sep 09 06:01:14 PM UTC 24 13522858200 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2024237415 Sep 09 05:59:21 PM UTC 24 Sep 09 06:01:45 PM UTC 24 10012529800 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2258963418 Sep 09 05:45:29 PM UTC 24 Sep 09 06:01:49 PM UTC 24 62830090700 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.322062666 Sep 09 06:00:22 PM UTC 24 Sep 09 06:01:53 PM UTC 24 10510328000 ps
T509 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.207690171 Sep 09 05:59:33 PM UTC 24 Sep 09 06:01:58 PM UTC 24 3427471500 ps
T510 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.602315595 Sep 09 05:54:17 PM UTC 24 Sep 09 06:02:01 PM UTC 24 3670358900 ps
T511 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.1740652985 Sep 09 06:01:02 PM UTC 24 Sep 09 06:02:08 PM UTC 24 9063576000 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.2141033553 Sep 09 06:01:46 PM UTC 24 Sep 09 06:02:11 PM UTC 24 70662500 ps
T513 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.879789297 Sep 09 06:00:30 PM UTC 24 Sep 09 06:02:18 PM UTC 24 2226692200 ps
T514 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.4177337047 Sep 09 06:01:54 PM UTC 24 Sep 09 06:02:29 PM UTC 24 120281000 ps
T515 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.1745284686 Sep 09 06:02:12 PM UTC 24 Sep 09 06:02:38 PM UTC 24 22458700 ps
T516 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.3868218909 Sep 09 06:02:02 PM UTC 24 Sep 09 06:02:41 PM UTC 24 27937500 ps
T517 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1560941276 Sep 09 06:00:39 PM UTC 24 Sep 09 06:02:43 PM UTC 24 954372500 ps
T518 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.2845277275 Sep 09 06:02:19 PM UTC 24 Sep 09 06:02:48 PM UTC 24 47491500 ps
T519 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.1556346571 Sep 09 06:01:50 PM UTC 24 Sep 09 06:02:52 PM UTC 24 43520000 ps
T520 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2999115688 Sep 09 06:01:59 PM UTC 24 Sep 09 06:02:56 PM UTC 24 300058100 ps
T521 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.3224011903 Sep 09 05:59:40 PM UTC 24 Sep 09 06:02:57 PM UTC 24 16408364000 ps
T522 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.3796687453 Sep 09 06:02:30 PM UTC 24 Sep 09 06:02:58 PM UTC 24 25221100 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2982127734 Sep 09 05:59:34 PM UTC 24 Sep 09 06:03:05 PM UTC 24 38907500 ps
T523 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.4235511218 Sep 09 06:02:42 PM UTC 24 Sep 09 06:03:07 PM UTC 24 46237200 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.1795561225 Sep 09 06:02:09 PM UTC 24 Sep 09 06:03:20 PM UTC 24 2052574600 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1995369351 Sep 09 06:00:36 PM UTC 24 Sep 09 06:03:21 PM UTC 24 1407146000 ps
T525 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.2401372506 Sep 09 06:00:54 PM UTC 24 Sep 09 06:03:21 PM UTC 24 1246807400 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.118191990 Sep 09 06:00:59 PM UTC 24 Sep 09 06:03:30 PM UTC 24 2752473500 ps
T527 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3929991644 Sep 09 06:03:07 PM UTC 24 Sep 09 06:03:48 PM UTC 24 3561146000 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1738511988 Sep 09 06:02:39 PM UTC 24 Sep 09 06:03:52 PM UTC 24 10101298200 ps
T528 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.185956287 Sep 09 06:01:06 PM UTC 24 Sep 09 06:03:59 PM UTC 24 8080006900 ps
T529 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2150091112 Sep 09 06:00:56 PM UTC 24 Sep 09 06:04:05 PM UTC 24 1343905900 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.1083139986 Sep 09 06:03:22 PM UTC 24 Sep 09 06:04:52 PM UTC 24 6129552000 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.766914565 Sep 09 06:00:27 PM UTC 24 Sep 09 06:05:04 PM UTC 24 10427468300 ps
T532 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.2654454888 Sep 09 05:56:51 PM UTC 24 Sep 09 06:05:18 PM UTC 24 3497033300 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.2860867305 Sep 09 05:59:32 PM UTC 24 Sep 09 06:05:19 PM UTC 24 3195320400 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.1009563373 Sep 09 05:46:51 PM UTC 24 Sep 09 06:05:26 PM UTC 24 312870900 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.1764126058 Sep 09 05:32:55 PM UTC 24 Sep 09 06:05:35 PM UTC 24 1297070659400 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.1189501182 Sep 09 06:02:59 PM UTC 24 Sep 09 06:06:00 PM UTC 24 132164400 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.4000150590 Sep 09 06:02:54 PM UTC 24 Sep 09 06:06:00 PM UTC 24 150825200 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.3903741980 Sep 09 06:03:49 PM UTC 24 Sep 09 06:06:05 PM UTC 24 2759611200 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.4094784735 Sep 09 06:02:44 PM UTC 24 Sep 09 06:06:10 PM UTC 24 3586778500 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.4176190039 Sep 09 06:06:01 PM UTC 24 Sep 09 06:06:17 PM UTC 24 76127000 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.1854205569 Sep 09 06:02:57 PM UTC 24 Sep 09 06:06:26 PM UTC 24 2330728400 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.2913128674 Sep 09 06:03:59 PM UTC 24 Sep 09 06:06:28 PM UTC 24 662567900 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.2325010259 Sep 09 06:06:06 PM UTC 24 Sep 09 06:06:42 PM UTC 24 37235700 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.1139668369 Sep 09 06:04:05 PM UTC 24 Sep 09 06:06:45 PM UTC 24 1246622700 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.2150329001 Sep 09 06:06:18 PM UTC 24 Sep 09 06:06:46 PM UTC 24 28961900 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.1768277971 Sep 09 06:06:29 PM UTC 24 Sep 09 06:06:54 PM UTC 24 39843900 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.4217034777 Sep 09 06:06:02 PM UTC 24 Sep 09 06:06:57 PM UTC 24 69883900 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.3010117949 Sep 09 06:06:11 PM UTC 24 Sep 09 06:07:04 PM UTC 24 98999300 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.1211584940 Sep 09 06:05:20 PM UTC 24 Sep 09 06:07:09 PM UTC 24 4732278300 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1220699198 Sep 09 06:06:46 PM UTC 24 Sep 09 06:07:09 PM UTC 24 15149400 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2160558538 Sep 09 06:06:43 PM UTC 24 Sep 09 06:07:11 PM UTC 24 29978400 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.292664062 Sep 09 06:06:55 PM UTC 24 Sep 09 06:07:24 PM UTC 24 97230800 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.1659341065 Sep 09 06:03:31 PM UTC 24 Sep 09 06:07:34 PM UTC 24 12925007800 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.951436429 Sep 09 06:04:54 PM UTC 24 Sep 09 06:07:56 PM UTC 24 648336600 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.2696559880 Sep 09 05:51:49 PM UTC 24 Sep 09 06:07:58 PM UTC 24 50128252400 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.2194245487 Sep 09 05:45:53 PM UTC 24 Sep 09 06:07:59 PM UTC 24 1516525000 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.3455334608 Sep 09 06:06:26 PM UTC 24 Sep 09 06:08:03 PM UTC 24 1493662700 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.2826360630 Sep 09 06:05:05 PM UTC 24 Sep 09 06:08:04 PM UTC 24 1587105100 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2268417573 Sep 09 06:05:19 PM UTC 24 Sep 09 06:08:23 PM UTC 24 736906500 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3933846283 Sep 09 06:06:47 PM UTC 24 Sep 09 06:08:24 PM UTC 24 10034518800 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.4039033284 Sep 09 06:03:05 PM UTC 24 Sep 09 06:08:32 PM UTC 24 100478904600 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.621951636 Sep 09 06:07:56 PM UTC 24 Sep 09 06:08:39 PM UTC 24 423533900 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3996221053 Sep 09 06:08:05 PM UTC 24 Sep 09 06:08:59 PM UTC 24 3392081900 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.86747096 Sep 09 05:35:17 PM UTC 24 Sep 09 06:09:05 PM UTC 24 167365698300 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.446249269 Sep 09 06:07:10 PM UTC 24 Sep 09 06:09:14 PM UTC 24 3187044900 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.1861993747 Sep 09 05:51:28 PM UTC 24 Sep 09 06:09:39 PM UTC 24 479214900 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.123655665 Sep 09 06:00:30 PM UTC 24 Sep 09 06:09:47 PM UTC 24 14720577400 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.574222222 Sep 09 05:44:39 PM UTC 24 Sep 09 06:09:50 PM UTC 24 856673500 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.3963244808 Sep 09 05:32:57 PM UTC 24 Sep 09 06:09:57 PM UTC 24 194759736100 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.479098823 Sep 09 05:56:11 PM UTC 24 Sep 09 06:09:58 PM UTC 24 221737930500 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.857808351 Sep 09 06:07:35 PM UTC 24 Sep 09 06:10:02 PM UTC 24 2239607900 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3503644120 Sep 09 06:05:27 PM UTC 24 Sep 09 06:10:04 PM UTC 24 49982391400 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.4079775813 Sep 09 06:08:23 PM UTC 24 Sep 09 06:10:13 PM UTC 24 936568800 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.3760339783 Sep 09 05:52:19 PM UTC 24 Sep 09 06:10:15 PM UTC 24 3280689800 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.1955362744 Sep 09 06:10:04 PM UTC 24 Sep 09 06:10:28 PM UTC 24 27628400 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.563006603 Sep 09 06:07:25 PM UTC 24 Sep 09 06:10:33 PM UTC 24 152077500 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3918272464 Sep 09 06:08:34 PM UTC 24 Sep 09 06:10:37 PM UTC 24 494763400 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.200231776 Sep 09 06:03:53 PM UTC 24 Sep 09 06:10:38 PM UTC 24 3296955200 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3156461765 Sep 09 06:09:40 PM UTC 24 Sep 09 06:10:50 PM UTC 24 2992623300 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1715593407 Sep 09 06:10:33 PM UTC 24 Sep 09 06:10:51 PM UTC 24 25343100 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.291690988 Sep 09 06:10:29 PM UTC 24 Sep 09 06:10:55 PM UTC 24 14680700 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.3670033179 Sep 09 06:10:06 PM UTC 24 Sep 09 06:10:58 PM UTC 24 66253900 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.1133501655 Sep 09 06:10:14 PM UTC 24 Sep 09 06:11:00 PM UTC 24 27694200 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1134177993 Sep 09 06:10:06 PM UTC 24 Sep 09 06:11:02 PM UTC 24 336765100 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3096011133 Sep 09 06:10:06 PM UTC 24 Sep 09 06:11:02 PM UTC 24 99340500 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1317510005 Sep 09 06:10:37 PM UTC 24 Sep 09 06:11:06 PM UTC 24 15832800 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1718948779 Sep 09 06:08:06 PM UTC 24 Sep 09 06:11:13 PM UTC 24 3959756300 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2596720299 Sep 09 06:09:00 PM UTC 24 Sep 09 06:11:21 PM UTC 24 1634966600 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.4127446397 Sep 09 06:10:52 PM UTC 24 Sep 09 06:11:23 PM UTC 24 28645200 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.2062232809 Sep 09 06:10:16 PM UTC 24 Sep 09 06:11:31 PM UTC 24 6496875000 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.2117379103 Sep 09 06:06:58 PM UTC 24 Sep 09 06:11:46 PM UTC 24 2327565300 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.4252980585 Sep 09 06:08:40 PM UTC 24 Sep 09 06:11:49 PM UTC 24 8919936700 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2012818635 Sep 09 06:11:14 PM UTC 24 Sep 09 06:11:50 PM UTC 24 114345400 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.103788168 Sep 09 06:10:52 PM UTC 24 Sep 09 06:11:55 PM UTC 24 22527600 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.2498890933 Sep 09 05:55:15 PM UTC 24 Sep 09 06:12:03 PM UTC 24 2225297200 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1883134691 Sep 09 06:05:35 PM UTC 24 Sep 09 06:12:21 PM UTC 24 50490678100 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1797883173 Sep 09 05:50:42 PM UTC 24 Sep 09 06:12:23 PM UTC 24 458429500 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1212754083 Sep 09 06:09:48 PM UTC 24 Sep 09 06:12:29 PM UTC 24 5853185400 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.3247254418 Sep 09 05:56:10 PM UTC 24 Sep 09 06:12:41 PM UTC 24 160183253300 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2524940223 Sep 09 06:11:32 PM UTC 24 Sep 09 06:12:52 PM UTC 24 3643673700 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3616928819 Sep 09 06:09:05 PM UTC 24 Sep 09 06:12:52 PM UTC 24 5642143400 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1765693586 Sep 09 06:09:14 PM UTC 24 Sep 09 06:13:06 PM UTC 24 1754370500 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3858631373 Sep 09 06:10:38 PM UTC 24 Sep 09 06:13:16 PM UTC 24 10019366500 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.2284547097 Sep 09 06:13:07 PM UTC 24 Sep 09 06:13:32 PM UTC 24 18735500 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1769653419 Sep 09 06:11:50 PM UTC 24 Sep 09 06:14:05 PM UTC 24 1884252200 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2594455211 Sep 09 06:13:17 PM UTC 24 Sep 09 06:14:08 PM UTC 24 28364800 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.325095994 Sep 09 05:56:03 PM UTC 24 Sep 09 06:14:13 PM UTC 24 198583300 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.671015341 Sep 09 06:11:03 PM UTC 24 Sep 09 06:14:15 PM UTC 24 37635000 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.112442571 Sep 09 06:13:33 PM UTC 24 Sep 09 06:14:27 PM UTC 24 28036800 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.507485975 Sep 09 06:12:42 PM UTC 24 Sep 09 06:14:32 PM UTC 24 4894021100 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.26941223 Sep 09 06:09:51 PM UTC 24 Sep 09 06:14:43 PM UTC 24 29031089400 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.1268896753 Sep 09 06:14:16 PM UTC 24 Sep 09 06:14:44 PM UTC 24 50035600 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.2684100278 Sep 09 06:11:01 PM UTC 24 Sep 09 06:14:45 PM UTC 24 2573574300 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.3650703129 Sep 09 06:14:09 PM UTC 24 Sep 09 06:14:48 PM UTC 24 55400500 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.2470771630 Sep 09 06:14:27 PM UTC 24 Sep 09 06:14:50 PM UTC 24 148442000 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.1547816728 Sep 09 06:14:33 PM UTC 24 Sep 09 06:14:54 PM UTC 24 26941100 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2562873424 Sep 09 06:12:22 PM UTC 24 Sep 09 06:14:56 PM UTC 24 615899500 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.2665384011 Sep 09 06:11:47 PM UTC 24 Sep 09 06:15:03 PM UTC 24 4064449100 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2301736036 Sep 09 05:56:15 PM UTC 24 Sep 09 06:14:57 PM UTC 24 628087600 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.2314996571 Sep 09 06:11:55 PM UTC 24 Sep 09 06:15:00 PM UTC 24 2889478000 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.4070506194 Sep 09 06:14:06 PM UTC 24 Sep 09 06:15:05 PM UTC 24 258345900 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.3213703048 Sep 09 06:14:45 PM UTC 24 Sep 09 06:15:12 PM UTC 24 34435600 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.4262913087 Sep 09 06:14:15 PM UTC 24 Sep 09 06:15:21 PM UTC 24 1324199400 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.4062271874 Sep 09 06:12:04 PM UTC 24 Sep 09 06:15:37 PM UTC 24 1289519500 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.657185488 Sep 09 06:02:58 PM UTC 24 Sep 09 06:16:18 PM UTC 24 40125451600 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.4165316991 Sep 09 06:12:24 PM UTC 24 Sep 09 06:16:20 PM UTC 24 5301870500 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.1225011795 Sep 09 06:15:04 PM UTC 24 Sep 09 06:16:25 PM UTC 24 4035737400 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.480142472 Sep 09 06:14:56 PM UTC 24 Sep 09 06:16:27 PM UTC 24 10348320300 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.585507439 Sep 09 06:12:30 PM UTC 24 Sep 09 06:16:27 PM UTC 24 1627531200 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.3457855123 Sep 09 05:59:57 PM UTC 24 Sep 09 06:16:29 PM UTC 24 663987300 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.2794139624 Sep 09 05:59:33 PM UTC 24 Sep 09 06:16:34 PM UTC 24 80138926700 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1052345208 Sep 09 05:41:10 PM UTC 24 Sep 09 06:16:38 PM UTC 24 543581407800 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.1966197732 Sep 09 06:16:21 PM UTC 24 Sep 09 06:16:43 PM UTC 24 17603000 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.281861225 Sep 09 06:14:44 PM UTC 24 Sep 09 06:16:52 PM UTC 24 10018720800 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.2033771701 Sep 09 06:08:25 PM UTC 24 Sep 09 06:16:55 PM UTC 24 3533402600 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.214540982 Sep 09 06:16:36 PM UTC 24 Sep 09 06:17:02 PM UTC 24 18822700 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.292206915 Sep 09 06:16:30 PM UTC 24 Sep 09 06:17:06 PM UTC 24 50451500 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.3418050044 Sep 09 06:16:44 PM UTC 24 Sep 09 06:17:09 PM UTC 24 15773600 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.513761573 Sep 09 06:16:39 PM UTC 24 Sep 09 06:17:09 PM UTC 24 47666600 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.2747681995 Sep 09 06:16:27 PM UTC 24 Sep 09 06:17:12 PM UTC 24 69040700 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.89266959 Sep 09 06:16:55 PM UTC 24 Sep 09 06:17:21 PM UTC 24 158979700 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.262075243 Sep 09 06:16:28 PM UTC 24 Sep 09 06:17:26 PM UTC 24 279414800 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2309458158 Sep 09 06:16:26 PM UTC 24 Sep 09 06:17:30 PM UTC 24 47541900 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.131846103 Sep 09 06:15:13 PM UTC 24 Sep 09 06:17:33 PM UTC 24 777387700 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.157822417 Sep 09 06:12:53 PM UTC 24 Sep 09 06:17:41 PM UTC 24 49983567100 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.32419988 Sep 09 06:15:38 PM UTC 24 Sep 09 06:17:41 PM UTC 24 697670900 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.1188696459 Sep 09 06:14:58 PM UTC 24 Sep 09 06:17:43 PM UTC 24 37040800 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2159518389 Sep 09 06:16:53 PM UTC 24 Sep 09 06:17:46 PM UTC 24 10096109100 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1303716769 Sep 09 06:11:06 PM UTC 24 Sep 09 06:17:52 PM UTC 24 6163772400 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2557207388 Sep 09 06:16:34 PM UTC 24 Sep 09 06:17:52 PM UTC 24 429565200 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.4194894572 Sep 09 06:14:45 PM UTC 24 Sep 09 06:18:08 PM UTC 24 29028700 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.2594823845 Sep 09 06:15:06 PM UTC 24 Sep 09 06:18:14 PM UTC 24 2333881200 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.2425293284 Sep 09 06:14:52 PM UTC 24 Sep 09 06:18:17 PM UTC 24 3760234800 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.37721980 Sep 09 06:17:53 PM UTC 24 Sep 09 06:18:19 PM UTC 24 18957300 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3095114339 Sep 09 06:16:19 PM UTC 24 Sep 09 06:18:35 PM UTC 24 5797280600 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1644841636 Sep 09 06:17:53 PM UTC 24 Sep 09 06:18:39 PM UTC 24 28334500 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.4217699176 Sep 09 06:18:18 PM UTC 24 Sep 09 06:18:49 PM UTC 24 12969700 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1753283701 Sep 09 06:07:10 PM UTC 24 Sep 09 06:18:53 PM UTC 24 1425775800 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.1495035004 Sep 09 05:33:00 PM UTC 24 Sep 09 06:18:54 PM UTC 24 38124485200 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.1456842471 Sep 09 06:18:09 PM UTC 24 Sep 09 06:18:59 PM UTC 24 40588400 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.1156420201 Sep 09 06:18:40 PM UTC 24 Sep 09 06:18:59 PM UTC 24 26446100 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.2771754652 Sep 09 06:18:36 PM UTC 24 Sep 09 06:19:01 PM UTC 24 40287600 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.1746084873 Sep 09 06:17:31 PM UTC 24 Sep 09 06:19:07 PM UTC 24 5045444700 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2575722396 Sep 09 06:17:42 PM UTC 24 Sep 09 06:19:07 PM UTC 24 1286366000 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.4217191438 Sep 09 06:18:50 PM UTC 24 Sep 09 06:19:13 PM UTC 24 26783700 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.3984049661 Sep 09 06:14:49 PM UTC 24 Sep 09 06:19:16 PM UTC 24 46292000 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.516942472 Sep 09 06:18:55 PM UTC 24 Sep 09 06:19:20 PM UTC 24 60965600 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3174911007 Sep 09 06:18:15 PM UTC 24 Sep 09 06:19:24 PM UTC 24 148355800 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1999056195 Sep 09 06:11:51 PM UTC 24 Sep 09 06:19:29 PM UTC 24 3386660300 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2255032564 Sep 09 06:10:59 PM UTC 24 Sep 09 06:19:32 PM UTC 24 13569495600 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.2729522148 Sep 09 06:17:34 PM UTC 24 Sep 09 06:19:41 PM UTC 24 1925552000 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1017702409 Sep 09 06:18:21 PM UTC 24 Sep 09 06:20:02 PM UTC 24 11289839200 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3171210379 Sep 09 06:12:53 PM UTC 24 Sep 09 06:20:03 PM UTC 24 344411942100 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3303991323 Sep 09 06:03:21 PM UTC 24 Sep 09 06:20:05 PM UTC 24 373881200 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.2952463781 Sep 09 06:18:59 PM UTC 24 Sep 09 06:20:26 PM UTC 24 60720700 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.4274124431 Sep 09 05:59:30 PM UTC 24 Sep 09 06:20:27 PM UTC 24 1511023900 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.135472797 Sep 09 06:17:03 PM UTC 24 Sep 09 06:20:43 PM UTC 24 86021800 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2726508069 Sep 09 06:07:12 PM UTC 24 Sep 09 06:20:48 PM UTC 24 80149172300 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.502522743 Sep 09 06:19:20 PM UTC 24 Sep 09 06:20:50 PM UTC 24 1730964700 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.881135421 Sep 09 06:15:01 PM UTC 24 Sep 09 06:20:51 PM UTC 24 9601595900 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.1411103907 Sep 09 06:17:43 PM UTC 24 Sep 09 06:20:52 PM UTC 24 744151000 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3149863273 Sep 09 06:17:22 PM UTC 24 Sep 09 06:20:57 PM UTC 24 79008500 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.687474242 Sep 09 06:20:05 PM UTC 24 Sep 09 06:21:08 PM UTC 24 33435200 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.54420773 Sep 09 06:20:27 PM UTC 24 Sep 09 06:21:09 PM UTC 24 156589600 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.2423447632 Sep 09 06:20:44 PM UTC 24 Sep 09 06:21:13 PM UTC 24 34722800 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.1669092229 Sep 09 06:20:53 PM UTC 24 Sep 09 06:21:19 PM UTC 24 98930200 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1028799862 Sep 09 06:20:51 PM UTC 24 Sep 09 06:21:19 PM UTC 24 40363700 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2160015562 Sep 09 06:20:28 PM UTC 24 Sep 09 06:21:21 PM UTC 24 176132300 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.437832481 Sep 09 06:20:53 PM UTC 24 Sep 09 06:21:23 PM UTC 24 206036700 ps
T647 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.2689500118 Sep 09 06:17:09 PM UTC 24 Sep 09 06:21:31 PM UTC 24 12901454400 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2504664496 Sep 09 06:18:54 PM UTC 24 Sep 09 06:21:33 PM UTC 24 10012366900 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1975905596 Sep 09 06:21:09 PM UTC 24 Sep 09 06:21:34 PM UTC 24 55924700 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.405421377 Sep 09 06:19:02 PM UTC 24 Sep 09 06:21:36 PM UTC 24 31877900 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.4018302626 Sep 09 06:19:30 PM UTC 24 Sep 09 06:21:49 PM UTC 24 1178994000 ps
T652 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.1480831783 Sep 09 06:19:24 PM UTC 24 Sep 09 06:22:15 PM UTC 24 1984047900 ps
T653 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3189360610 Sep 09 06:19:08 PM UTC 24 Sep 09 06:22:30 PM UTC 24 16967659800 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.3843925604 Sep 09 06:20:49 PM UTC 24 Sep 09 06:22:30 PM UTC 24 3415561500 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.3537578557 Sep 09 06:19:14 PM UTC 24 Sep 09 06:22:39 PM UTC 24 126311100 ps
T655 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.774885624 Sep 09 06:17:46 PM UTC 24 Sep 09 06:22:47 PM UTC 24 31151929600 ps
T656 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3529640086 Sep 09 06:21:34 PM UTC 24 Sep 09 06:22:57 PM UTC 24 5113193200 ps
T657 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2269441818 Sep 09 06:20:04 PM UTC 24 Sep 09 06:23:17 PM UTC 24 2144363900 ps
T658 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.1751802011 Sep 09 06:22:40 PM UTC 24 Sep 09 06:23:24 PM UTC 24 30953100 ps
T659 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.831292486 Sep 09 06:22:48 PM UTC 24 Sep 09 06:23:28 PM UTC 24 62564400 ps
T660 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.2479957901 Sep 09 06:10:56 PM UTC 24 Sep 09 06:23:36 PM UTC 24 70968500 ps
T661 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3568331904 Sep 09 06:20:03 PM UTC 24 Sep 09 06:23:44 PM UTC 24 72428947800 ps
T662 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.503748849 Sep 09 06:19:42 PM UTC 24 Sep 09 06:23:47 PM UTC 24 15688114500 ps
T663 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.474811414 Sep 09 06:22:58 PM UTC 24 Sep 09 06:23:54 PM UTC 24 110938400 ps
T664 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.2146091925 Sep 09 06:23:18 PM UTC 24 Sep 09 06:23:58 PM UTC 24 17904700 ps
T665 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.1499152575 Sep 09 06:23:29 PM UTC 24 Sep 09 06:23:58 PM UTC 24 22983000 ps
T666 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2766714525 Sep 09 06:20:59 PM UTC 24 Sep 09 06:23:59 PM UTC 24 10011572900 ps
T667 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.4100099072 Sep 09 06:23:37 PM UTC 24 Sep 09 06:24:00 PM UTC 24 27101800 ps
T668 /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1489698672 Sep 09 06:21:37 PM UTC 24 Sep 09 06:24:01 PM UTC 24 1495272200 ps
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