| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.3590332270 |
|
|
Sep 09 06:50:06 PM UTC 24 |
Sep 09 06:50:40 PM UTC 24 |
22640300 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.1283231354 |
|
|
Sep 09 06:50:22 PM UTC 24 |
Sep 09 06:50:42 PM UTC 24 |
47792600 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.1023585905 |
|
|
Sep 09 06:50:14 PM UTC 24 |
Sep 09 06:50:42 PM UTC 24 |
30367800 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.2476960825 |
|
|
Sep 09 06:45:51 PM UTC 24 |
Sep 09 06:50:43 PM UTC 24 |
51884200 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.910327668 |
|
|
Sep 09 06:50:25 PM UTC 24 |
Sep 09 06:50:45 PM UTC 24 |
117923900 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.163035866 |
|
|
Sep 09 06:45:08 PM UTC 24 |
Sep 09 06:50:53 PM UTC 24 |
12131742500 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.3389798249 |
|
|
Sep 09 06:47:17 PM UTC 24 |
Sep 09 06:50:59 PM UTC 24 |
99402800 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.3939191168 |
|
|
Sep 09 05:56:31 PM UTC 24 |
Sep 09 06:51:00 PM UTC 24 |
6064844300 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.2001527172 |
|
|
Sep 09 06:47:57 PM UTC 24 |
Sep 09 06:51:05 PM UTC 24 |
82518600 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.3770079992 |
|
|
Sep 09 06:23:59 PM UTC 24 |
Sep 09 06:51:06 PM UTC 24 |
656929800 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.2204076369 |
|
|
Sep 09 06:48:04 PM UTC 24 |
Sep 09 06:51:07 PM UTC 24 |
96547400 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.196290997 |
|
|
Sep 09 06:48:32 PM UTC 24 |
Sep 09 06:51:09 PM UTC 24 |
40959100 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1125525548 |
|
|
Sep 09 06:45:57 PM UTC 24 |
Sep 09 06:51:11 PM UTC 24 |
12500399100 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1364052124 |
|
|
Sep 09 06:48:57 PM UTC 24 |
Sep 09 06:51:16 PM UTC 24 |
69133100 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.2993863035 |
|
|
Sep 09 06:48:17 PM UTC 24 |
Sep 09 06:51:22 PM UTC 24 |
69727200 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.1217375636 |
|
|
Sep 09 06:49:00 PM UTC 24 |
Sep 09 06:51:29 PM UTC 24 |
60685700 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3287243814 |
|
|
Sep 09 06:49:04 PM UTC 24 |
Sep 09 06:51:30 PM UTC 24 |
84316100 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.67350381 |
|
|
Sep 09 06:48:58 PM UTC 24 |
Sep 09 06:51:42 PM UTC 24 |
84221400 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.1500778671 |
|
|
Sep 09 06:49:15 PM UTC 24 |
Sep 09 06:51:43 PM UTC 24 |
78018500 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.3767061985 |
|
|
Sep 09 06:48:46 PM UTC 24 |
Sep 09 06:51:50 PM UTC 24 |
464839100 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.175128372 |
|
|
Sep 09 06:49:03 PM UTC 24 |
Sep 09 06:51:51 PM UTC 24 |
127915000 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2044561546 |
|
|
Sep 09 06:49:34 PM UTC 24 |
Sep 09 06:51:53 PM UTC 24 |
151210300 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1504271591 |
|
|
Sep 09 06:49:15 PM UTC 24 |
Sep 09 06:51:58 PM UTC 24 |
39122000 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.871128974 |
|
|
Sep 09 06:49:37 PM UTC 24 |
Sep 09 06:52:00 PM UTC 24 |
61855200 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.72572881 |
|
|
Sep 09 06:49:41 PM UTC 24 |
Sep 09 06:52:05 PM UTC 24 |
39350400 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.1611042825 |
|
|
Sep 09 06:49:30 PM UTC 24 |
Sep 09 06:52:11 PM UTC 24 |
157113400 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.1347186153 |
|
|
Sep 09 06:49:14 PM UTC 24 |
Sep 09 06:52:13 PM UTC 24 |
201525000 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.2271509386 |
|
|
Sep 09 06:49:23 PM UTC 24 |
Sep 09 06:52:14 PM UTC 24 |
137696800 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.160816838 |
|
|
Sep 09 06:49:39 PM UTC 24 |
Sep 09 06:52:19 PM UTC 24 |
35462100 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1987631663 |
|
|
Sep 09 06:49:32 PM UTC 24 |
Sep 09 06:52:22 PM UTC 24 |
72979900 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2874929465 |
|
|
Sep 09 06:49:18 PM UTC 24 |
Sep 09 06:52:24 PM UTC 24 |
138675400 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.437242497 |
|
|
Sep 09 06:50:06 PM UTC 24 |
Sep 09 06:52:25 PM UTC 24 |
41256500 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.1914197277 |
|
|
Sep 09 06:49:34 PM UTC 24 |
Sep 09 06:52:25 PM UTC 24 |
133376400 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.4162464463 |
|
|
Sep 09 06:49:45 PM UTC 24 |
Sep 09 06:52:27 PM UTC 24 |
42569800 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.1600049057 |
|
|
Sep 09 06:50:03 PM UTC 24 |
Sep 09 06:52:32 PM UTC 24 |
79985500 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.3732366530 |
|
|
Sep 09 06:48:42 PM UTC 24 |
Sep 09 06:52:33 PM UTC 24 |
446760300 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.2754768641 |
|
|
Sep 09 06:49:44 PM UTC 24 |
Sep 09 06:52:34 PM UTC 24 |
160784000 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.3737725582 |
|
|
Sep 09 06:50:00 PM UTC 24 |
Sep 09 06:52:36 PM UTC 24 |
47042900 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.3716159848 |
|
|
Sep 09 06:50:16 PM UTC 24 |
Sep 09 06:52:37 PM UTC 24 |
130714500 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.4058081661 |
|
|
Sep 09 06:50:08 PM UTC 24 |
Sep 09 06:52:44 PM UTC 24 |
371459000 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.292149964 |
|
|
Sep 09 06:49:49 PM UTC 24 |
Sep 09 06:52:45 PM UTC 24 |
76934400 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.2334021869 |
|
|
Sep 09 06:49:54 PM UTC 24 |
Sep 09 06:52:48 PM UTC 24 |
79843500 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.3521271581 |
|
|
Sep 09 06:03:22 PM UTC 24 |
Sep 09 06:52:50 PM UTC 24 |
4925273300 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.1828844334 |
|
|
Sep 09 06:49:53 PM UTC 24 |
Sep 09 06:52:52 PM UTC 24 |
73693000 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.2743816138 |
|
|
Sep 09 06:50:11 PM UTC 24 |
Sep 09 06:53:03 PM UTC 24 |
184251300 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2294326730 |
|
|
Sep 09 06:50:19 PM UTC 24 |
Sep 09 06:53:08 PM UTC 24 |
77908100 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.3942749713 |
|
|
Sep 09 06:50:24 PM UTC 24 |
Sep 09 06:53:12 PM UTC 24 |
92220300 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.1481911925 |
|
|
Sep 09 06:48:29 PM UTC 24 |
Sep 09 06:53:13 PM UTC 24 |
26765448600 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.677185139 |
|
|
Sep 09 05:52:08 PM UTC 24 |
Sep 09 06:53:40 PM UTC 24 |
125212840700 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.2190958778 |
|
|
Sep 09 06:11:23 PM UTC 24 |
Sep 09 07:00:26 PM UTC 24 |
17146415300 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.2181430858 |
|
|
Sep 09 06:08:00 PM UTC 24 |
Sep 09 07:02:05 PM UTC 24 |
31489369200 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.870293537 |
|
|
Sep 09 05:44:27 PM UTC 24 |
Sep 09 07:26:50 PM UTC 24 |
4889889400 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.4290880825 |
|
|
Sep 09 05:39:31 PM UTC 24 |
Sep 09 07:29:25 PM UTC 24 |
3135814600 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2867594089 |
|
|
Sep 09 05:33:50 PM UTC 24 |
Sep 09 07:29:30 PM UTC 24 |
1945077700 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.934097974 |
|
|
Sep 09 05:50:20 PM UTC 24 |
Sep 09 07:34:18 PM UTC 24 |
3962915600 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.2556556510 |
|
|
Sep 09 05:55:08 PM UTC 24 |
Sep 09 07:44:08 PM UTC 24 |
3750303300 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.620669932 |
|
|
Sep 09 05:29:45 PM UTC 24 |
Sep 09 05:30:02 PM UTC 24 |
27151400 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.410689845 |
|
|
Sep 09 05:29:45 PM UTC 24 |
Sep 09 05:30:08 PM UTC 24 |
274529800 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1250176619 |
|
|
Sep 09 05:29:47 PM UTC 24 |
Sep 09 05:30:08 PM UTC 24 |
74481200 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.194447666 |
|
|
Sep 09 05:29:52 PM UTC 24 |
Sep 09 05:30:12 PM UTC 24 |
47350400 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.490963841 |
|
|
Sep 09 05:29:45 PM UTC 24 |
Sep 09 05:30:13 PM UTC 24 |
15684000 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3953465280 |
|
|
Sep 09 05:29:48 PM UTC 24 |
Sep 09 05:30:14 PM UTC 24 |
106982300 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2325408885 |
|
|
Sep 09 05:29:45 PM UTC 24 |
Sep 09 05:30:14 PM UTC 24 |
27788400 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3354742508 |
|
|
Sep 09 05:29:45 PM UTC 24 |
Sep 09 05:30:14 PM UTC 24 |
60686100 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3822853289 |
|
|
Sep 09 05:29:47 PM UTC 24 |
Sep 09 05:30:15 PM UTC 24 |
19980700 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2986601089 |
|
|
Sep 09 05:29:50 PM UTC 24 |
Sep 09 05:30:20 PM UTC 24 |
36557800 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.4082942056 |
|
|
Sep 09 05:29:58 PM UTC 24 |
Sep 09 05:30:21 PM UTC 24 |
29921700 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2080496316 |
|
|
Sep 09 05:30:02 PM UTC 24 |
Sep 09 05:30:22 PM UTC 24 |
19962500 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2674728810 |
|
|
Sep 09 05:29:57 PM UTC 24 |
Sep 09 05:30:23 PM UTC 24 |
12759800 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3025139238 |
|
|
Sep 09 05:29:48 PM UTC 24 |
Sep 09 05:30:26 PM UTC 24 |
318150500 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2318526888 |
|
|
Sep 09 05:29:47 PM UTC 24 |
Sep 09 05:30:31 PM UTC 24 |
21027100 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.1554701921 |
|
|
Sep 09 05:30:15 PM UTC 24 |
Sep 09 05:30:33 PM UTC 24 |
25771800 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4038798724 |
|
|
Sep 09 05:30:10 PM UTC 24 |
Sep 09 05:30:35 PM UTC 24 |
43437000 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1975354945 |
|
|
Sep 09 05:30:09 PM UTC 24 |
Sep 09 05:30:35 PM UTC 24 |
55936800 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2307416966 |
|
|
Sep 09 05:30:15 PM UTC 24 |
Sep 09 05:30:37 PM UTC 24 |
15233400 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.4286345876 |
|
|
Sep 09 05:30:13 PM UTC 24 |
Sep 09 05:30:37 PM UTC 24 |
25445600 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4132266172 |
|
|
Sep 09 05:30:15 PM UTC 24 |
Sep 09 05:30:41 PM UTC 24 |
75288700 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.882676224 |
|
|
Sep 09 05:30:16 PM UTC 24 |
Sep 09 05:30:41 PM UTC 24 |
31682500 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2248169285 |
|
|
Sep 09 05:30:13 PM UTC 24 |
Sep 09 05:30:42 PM UTC 24 |
62025400 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3629713433 |
|
|
Sep 09 05:30:15 PM UTC 24 |
Sep 09 05:30:43 PM UTC 24 |
15125400 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3972067917 |
|
|
Sep 09 05:30:28 PM UTC 24 |
Sep 09 05:30:46 PM UTC 24 |
43779300 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2381453683 |
|
|
Sep 09 05:30:14 PM UTC 24 |
Sep 09 05:30:48 PM UTC 24 |
226200900 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4077841063 |
|
|
Sep 09 05:30:24 PM UTC 24 |
Sep 09 05:30:49 PM UTC 24 |
182202800 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2070942315 |
|
|
Sep 09 05:30:32 PM UTC 24 |
Sep 09 05:30:50 PM UTC 24 |
54759800 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1094094184 |
|
|
Sep 09 05:30:22 PM UTC 24 |
Sep 09 05:30:50 PM UTC 24 |
57768300 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3381752525 |
|
|
Sep 09 05:30:27 PM UTC 24 |
Sep 09 05:30:51 PM UTC 24 |
204783500 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1332096789 |
|
|
Sep 09 05:30:34 PM UTC 24 |
Sep 09 05:30:51 PM UTC 24 |
16863000 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.609211848 |
|
|
Sep 09 05:29:48 PM UTC 24 |
Sep 09 05:30:52 PM UTC 24 |
845019400 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1023470652 |
|
|
Sep 09 05:30:09 PM UTC 24 |
Sep 09 05:30:53 PM UTC 24 |
133504700 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2395400691 |
|
|
Sep 09 05:30:31 PM UTC 24 |
Sep 09 05:30:55 PM UTC 24 |
23885800 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2817523686 |
|
|
Sep 09 05:30:38 PM UTC 24 |
Sep 09 05:31:00 PM UTC 24 |
24571800 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3423303255 |
|
|
Sep 09 05:30:43 PM UTC 24 |
Sep 09 05:31:02 PM UTC 24 |
25091700 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1212236792 |
|
|
Sep 09 05:30:39 PM UTC 24 |
Sep 09 05:31:02 PM UTC 24 |
115170800 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3629020459 |
|
|
Sep 09 05:30:43 PM UTC 24 |
Sep 09 05:31:02 PM UTC 24 |
11728000 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.221794680 |
|
|
Sep 09 05:30:44 PM UTC 24 |
Sep 09 05:31:02 PM UTC 24 |
18576700 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.534475474 |
|
|
Sep 09 05:30:36 PM UTC 24 |
Sep 09 05:31:05 PM UTC 24 |
28405900 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.546552720 |
|
|
Sep 09 05:31:16 PM UTC 24 |
Sep 09 05:31:45 PM UTC 24 |
55789300 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1915518937 |
|
|
Sep 09 05:30:49 PM UTC 24 |
Sep 09 05:31:07 PM UTC 24 |
16338000 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.624314458 |
|
|
Sep 09 05:30:42 PM UTC 24 |
Sep 09 05:31:10 PM UTC 24 |
57484200 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4110605019 |
|
|
Sep 09 05:30:39 PM UTC 24 |
Sep 09 05:31:11 PM UTC 24 |
92055400 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1522925840 |
|
|
Sep 09 05:30:12 PM UTC 24 |
Sep 09 05:31:13 PM UTC 24 |
893651200 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3552954418 |
|
|
Sep 09 05:30:47 PM UTC 24 |
Sep 09 05:31:14 PM UTC 24 |
29243100 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1303751097 |
|
|
Sep 09 05:30:23 PM UTC 24 |
Sep 09 05:31:15 PM UTC 24 |
241691900 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1404179010 |
|
|
Sep 09 05:30:52 PM UTC 24 |
Sep 09 05:31:16 PM UTC 24 |
132573600 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4253435587 |
|
|
Sep 09 05:30:56 PM UTC 24 |
Sep 09 05:31:17 PM UTC 24 |
43200700 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3231902517 |
|
|
Sep 09 05:29:47 PM UTC 24 |
Sep 09 05:31:17 PM UTC 24 |
9217520600 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1144189584 |
|
|
Sep 09 05:30:22 PM UTC 24 |
Sep 09 05:31:20 PM UTC 24 |
67452000 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.51551912 |
|
|
Sep 09 05:31:03 PM UTC 24 |
Sep 09 05:31:21 PM UTC 24 |
14251100 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3953646449 |
|
|
Sep 09 05:30:52 PM UTC 24 |
Sep 09 05:31:23 PM UTC 24 |
48838300 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.679025548 |
|
|
Sep 09 05:31:03 PM UTC 24 |
Sep 09 05:31:23 PM UTC 24 |
32630800 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2204462477 |
|
|
Sep 09 05:30:51 PM UTC 24 |
Sep 09 05:31:23 PM UTC 24 |
29755600 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.107407463 |
|
|
Sep 09 05:31:03 PM UTC 24 |
Sep 09 05:31:26 PM UTC 24 |
39667900 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2444969514 |
|
|
Sep 09 05:31:08 PM UTC 24 |
Sep 09 05:31:26 PM UTC 24 |
16385700 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.1230069661 |
|
|
Sep 09 05:31:08 PM UTC 24 |
Sep 09 05:31:26 PM UTC 24 |
15261800 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.203753756 |
|
|
Sep 09 05:31:01 PM UTC 24 |
Sep 09 05:31:27 PM UTC 24 |
42817500 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2793307766 |
|
|
Sep 09 05:30:52 PM UTC 24 |
Sep 09 05:31:27 PM UTC 24 |
166620300 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.457092272 |
|
|
Sep 09 05:31:08 PM UTC 24 |
Sep 09 05:31:28 PM UTC 24 |
114076400 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2232079820 |
|
|
Sep 09 05:31:03 PM UTC 24 |
Sep 09 05:31:29 PM UTC 24 |
162851500 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3313981238 |
|
|
Sep 09 05:31:05 PM UTC 24 |
Sep 09 05:31:31 PM UTC 24 |
40843900 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2680993726 |
|
|
Sep 09 05:31:03 PM UTC 24 |
Sep 09 05:31:36 PM UTC 24 |
233810500 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.885285102 |
|
|
Sep 09 05:31:12 PM UTC 24 |
Sep 09 05:31:37 PM UTC 24 |
78939700 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1220473187 |
|
|
Sep 09 05:31:17 PM UTC 24 |
Sep 09 05:31:37 PM UTC 24 |
69737200 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1296613144 |
|
|
Sep 09 05:31:16 PM UTC 24 |
Sep 09 05:31:38 PM UTC 24 |
68669100 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2777609693 |
|
|
Sep 09 05:31:18 PM UTC 24 |
Sep 09 05:31:39 PM UTC 24 |
138060500 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2855094441 |
|
|
Sep 09 05:30:38 PM UTC 24 |
Sep 09 05:31:41 PM UTC 24 |
5176474100 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3033899840 |
|
|
Sep 09 05:31:18 PM UTC 24 |
Sep 09 05:31:42 PM UTC 24 |
65922300 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.888240498 |
|
|
Sep 09 05:31:11 PM UTC 24 |
Sep 09 05:31:43 PM UTC 24 |
383129600 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.32172055 |
|
|
Sep 09 05:30:23 PM UTC 24 |
Sep 09 05:31:43 PM UTC 24 |
25092463800 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1712534942 |
|
|
Sep 09 05:31:24 PM UTC 24 |
Sep 09 05:31:45 PM UTC 24 |
37301000 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2391256190 |
|
|
Sep 09 05:30:36 PM UTC 24 |
Sep 09 05:31:49 PM UTC 24 |
26119900 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.879424189 |
|
|
Sep 09 05:31:16 PM UTC 24 |
Sep 09 05:31:45 PM UTC 24 |
11297000 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1595398716 |
|
|
Sep 09 05:31:23 PM UTC 24 |
Sep 09 05:31:47 PM UTC 24 |
38143900 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2648195023 |
|
|
Sep 09 05:31:27 PM UTC 24 |
Sep 09 05:31:49 PM UTC 24 |
161518600 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.930496597 |
|
|
Sep 09 05:31:20 PM UTC 24 |
Sep 09 05:31:50 PM UTC 24 |
121359200 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2952766079 |
|
|
Sep 09 05:31:29 PM UTC 24 |
Sep 09 05:31:51 PM UTC 24 |
34384700 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2320424793 |
|
|
Sep 09 05:31:29 PM UTC 24 |
Sep 09 05:31:51 PM UTC 24 |
35297700 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2071597295 |
|
|
Sep 09 05:31:27 PM UTC 24 |
Sep 09 05:31:51 PM UTC 24 |
170497600 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1688017482 |
|
|
Sep 09 05:30:51 PM UTC 24 |
Sep 09 05:31:51 PM UTC 24 |
19924093200 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1300180977 |
|
|
Sep 09 05:31:24 PM UTC 24 |
Sep 09 05:31:51 PM UTC 24 |
34198700 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2196968061 |
|
|
Sep 09 05:31:30 PM UTC 24 |
Sep 09 05:31:53 PM UTC 24 |
39796500 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1763495433 |
|
|
Sep 09 05:30:50 PM UTC 24 |
Sep 09 05:31:53 PM UTC 24 |
43420400 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.2312229664 |
|
|
Sep 09 05:31:24 PM UTC 24 |
Sep 09 05:31:53 PM UTC 24 |
91210300 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2814974810 |
|
|
Sep 09 05:31:29 PM UTC 24 |
Sep 09 05:31:54 PM UTC 24 |
83163600 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3307507537 |
|
|
Sep 09 05:31:10 PM UTC 24 |
Sep 09 05:31:54 PM UTC 24 |
1122144800 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.783079651 |
|
|
Sep 09 05:31:32 PM UTC 24 |
Sep 09 05:31:56 PM UTC 24 |
39380400 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3914102558 |
|
|
Sep 09 05:31:37 PM UTC 24 |
Sep 09 05:31:58 PM UTC 24 |
24788000 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1439615024 |
|
|
Sep 09 05:31:27 PM UTC 24 |
Sep 09 05:31:58 PM UTC 24 |
67643700 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4215715390 |
|
|
Sep 09 05:31:30 PM UTC 24 |
Sep 09 05:31:59 PM UTC 24 |
107824900 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3210940126 |
|
|
Sep 09 05:31:43 PM UTC 24 |
Sep 09 05:32:00 PM UTC 24 |
27365400 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1559320769 |
|
|
Sep 09 05:31:37 PM UTC 24 |
Sep 09 05:32:00 PM UTC 24 |
24313000 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3360854568 |
|
|
Sep 09 05:30:51 PM UTC 24 |
Sep 09 05:32:01 PM UTC 24 |
4969467400 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3448680838 |
|
|
Sep 09 05:31:38 PM UTC 24 |
Sep 09 05:32:02 PM UTC 24 |
53742900 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3115838422 |
|
|
Sep 09 05:31:34 PM UTC 24 |
Sep 09 05:32:03 PM UTC 24 |
35194000 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2400121954 |
|
|
Sep 09 05:31:39 PM UTC 24 |
Sep 09 05:32:03 PM UTC 24 |
50893800 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2147010019 |
|
|
Sep 09 05:30:22 PM UTC 24 |
Sep 09 05:32:05 PM UTC 24 |
16340100400 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1814793551 |
|
|
Sep 09 05:31:38 PM UTC 24 |
Sep 09 05:32:05 PM UTC 24 |
487652100 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.716186207 |
|
|
Sep 09 05:31:43 PM UTC 24 |
Sep 09 05:32:06 PM UTC 24 |
30828400 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.171681327 |
|
|
Sep 09 05:30:38 PM UTC 24 |
Sep 09 05:32:07 PM UTC 24 |
5754304100 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.515208078 |
|
|
Sep 09 05:31:41 PM UTC 24 |
Sep 09 05:32:07 PM UTC 24 |
67403800 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3529961989 |
|
|
Sep 09 05:31:39 PM UTC 24 |
Sep 09 05:32:07 PM UTC 24 |
297755800 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.387453283 |
|
|
Sep 09 05:31:46 PM UTC 24 |
Sep 09 05:32:09 PM UTC 24 |
40342200 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3382807577 |
|
|
Sep 09 05:31:44 PM UTC 24 |
Sep 09 05:32:09 PM UTC 24 |
69510200 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3684161154 |
|
|
Sep 09 05:31:51 PM UTC 24 |
Sep 09 05:32:09 PM UTC 24 |
26037900 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1022497825 |
|
|
Sep 09 05:31:46 PM UTC 24 |
Sep 09 05:32:10 PM UTC 24 |
25899300 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2023603738 |
|
|
Sep 09 05:31:46 PM UTC 24 |
Sep 09 05:32:10 PM UTC 24 |
175404100 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2931172740 |
|
|
Sep 09 05:31:52 PM UTC 24 |
Sep 09 05:32:11 PM UTC 24 |
113353900 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2579129524 |
|
|
Sep 09 05:31:51 PM UTC 24 |
Sep 09 05:32:11 PM UTC 24 |
14105000 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.75582770 |
|
|
Sep 09 05:30:11 PM UTC 24 |
Sep 09 05:32:11 PM UTC 24 |
20999776300 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.4014061292 |
|
|
Sep 09 05:31:51 PM UTC 24 |
Sep 09 05:32:13 PM UTC 24 |
58733800 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1653634491 |
|
|
Sep 09 05:31:54 PM UTC 24 |
Sep 09 05:32:15 PM UTC 24 |
57831000 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3775003343 |
|
|
Sep 09 05:31:53 PM UTC 24 |
Sep 09 05:32:16 PM UTC 24 |
14519600 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.854913799 |
|
|
Sep 09 05:31:54 PM UTC 24 |
Sep 09 05:32:16 PM UTC 24 |
21180600 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1359126749 |
|
|
Sep 09 05:31:52 PM UTC 24 |
Sep 09 05:32:16 PM UTC 24 |
223307200 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1675325187 |
|
|
Sep 09 05:31:52 PM UTC 24 |
Sep 09 05:32:16 PM UTC 24 |
312085500 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.314987224 |
|
|
Sep 09 05:31:48 PM UTC 24 |
Sep 09 05:32:17 PM UTC 24 |
97748600 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1830048990 |
|
|
Sep 09 05:31:53 PM UTC 24 |
Sep 09 05:32:17 PM UTC 24 |
13926500 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3284613962 |
|
|
Sep 09 05:32:00 PM UTC 24 |
Sep 09 05:32:19 PM UTC 24 |
29723500 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3426535429 |
|
|
Sep 09 05:31:57 PM UTC 24 |
Sep 09 05:32:19 PM UTC 24 |
181888500 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2020102700 |
|
|
Sep 09 05:32:00 PM UTC 24 |
Sep 09 05:32:19 PM UTC 24 |
104604400 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2374549642 |
|
|
Sep 09 05:31:52 PM UTC 24 |
Sep 09 05:32:19 PM UTC 24 |
42330800 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1688576061 |
|
|
Sep 09 05:31:59 PM UTC 24 |
Sep 09 05:32:21 PM UTC 24 |
15780100 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1320721389 |
|
|
Sep 09 05:32:02 PM UTC 24 |
Sep 09 05:32:24 PM UTC 24 |
195803100 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.110655735 |
|
|
Sep 09 05:32:18 PM UTC 24 |
Sep 09 05:32:38 PM UTC 24 |
13081000 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3970289001 |
|
|
Sep 09 05:31:55 PM UTC 24 |
Sep 09 05:32:24 PM UTC 24 |
70484200 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3836170336 |
|
|
Sep 09 05:32:05 PM UTC 24 |
Sep 09 05:32:26 PM UTC 24 |
14537400 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2239360963 |
|
|
Sep 09 05:31:58 PM UTC 24 |
Sep 09 05:32:27 PM UTC 24 |
67698500 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1377455028 |
|
|
Sep 09 05:32:06 PM UTC 24 |
Sep 09 05:32:29 PM UTC 24 |
145651900 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.260454705 |
|
|
Sep 09 05:32:01 PM UTC 24 |
Sep 09 05:32:29 PM UTC 24 |
105223300 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3702703632 |
|
|
Sep 09 05:32:06 PM UTC 24 |
Sep 09 05:32:29 PM UTC 24 |
16569600 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4165171287 |
|
|
Sep 09 05:32:08 PM UTC 24 |
Sep 09 05:32:30 PM UTC 24 |
17055000 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.876632969 |
|
|
Sep 09 05:32:07 PM UTC 24 |
Sep 09 05:32:30 PM UTC 24 |
160955700 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4075302487 |
|
|
Sep 09 05:32:02 PM UTC 24 |
Sep 09 05:32:30 PM UTC 24 |
217114000 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1100528691 |
|
|
Sep 09 05:32:03 PM UTC 24 |
Sep 09 05:32:31 PM UTC 24 |
64472800 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1576129146 |
|
|
Sep 09 05:32:10 PM UTC 24 |
Sep 09 05:32:32 PM UTC 24 |
16482800 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2817881557 |
|
|
Sep 09 05:32:10 PM UTC 24 |
Sep 09 05:32:32 PM UTC 24 |
24541500 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3367444625 |
|
|
Sep 09 05:32:05 PM UTC 24 |
Sep 09 05:32:33 PM UTC 24 |
12355900 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.782150716 |
|
|
Sep 09 05:32:10 PM UTC 24 |
Sep 09 05:32:33 PM UTC 24 |
109320100 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1385177357 |
|
|
Sep 09 05:32:07 PM UTC 24 |
Sep 09 05:32:35 PM UTC 24 |
334201500 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.500951300 |
|
|
Sep 09 05:32:12 PM UTC 24 |
Sep 09 05:32:36 PM UTC 24 |
110472100 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1772966868 |
|
|
Sep 09 05:32:13 PM UTC 24 |
Sep 09 05:32:36 PM UTC 24 |
77892800 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2440556494 |
|
|
Sep 09 05:32:12 PM UTC 24 |
Sep 09 05:32:36 PM UTC 24 |
142706300 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2153891784 |
|
|
Sep 09 05:32:15 PM UTC 24 |
Sep 09 05:32:37 PM UTC 24 |
344823100 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3792650064 |
|
|
Sep 09 05:32:12 PM UTC 24 |
Sep 09 05:32:38 PM UTC 24 |
239674400 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4283130396 |
|
|
Sep 09 05:32:08 PM UTC 24 |
Sep 09 05:32:39 PM UTC 24 |
241047600 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3048465211 |
|
|
Sep 09 05:32:16 PM UTC 24 |
Sep 09 05:32:39 PM UTC 24 |
361836600 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1493088256 |
|
|
Sep 09 05:32:18 PM UTC 24 |
Sep 09 05:32:40 PM UTC 24 |
28581900 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2292540125 |
|
|
Sep 09 05:32:22 PM UTC 24 |
Sep 09 05:32:40 PM UTC 24 |
43173300 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1152888181 |
|
|
Sep 09 05:32:14 PM UTC 24 |
Sep 09 05:32:41 PM UTC 24 |
57612200 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2875074380 |
|
|
Sep 09 05:32:12 PM UTC 24 |
Sep 09 05:32:41 PM UTC 24 |
33482300 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2982636488 |
|
|
Sep 09 05:32:26 PM UTC 24 |
Sep 09 05:32:44 PM UTC 24 |
13579800 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3895434091 |
|
|
Sep 09 05:32:16 PM UTC 24 |
Sep 09 05:32:44 PM UTC 24 |
417838100 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.148621790 |
|
|
Sep 09 05:32:20 PM UTC 24 |
Sep 09 05:32:44 PM UTC 24 |
37174400 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2517111346 |
|
|
Sep 09 05:32:19 PM UTC 24 |
Sep 09 05:32:44 PM UTC 24 |
70783700 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3700140187 |
|
|
Sep 09 05:32:18 PM UTC 24 |
Sep 09 05:32:44 PM UTC 24 |
42571000 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.179570331 |
|
|
Sep 09 05:32:20 PM UTC 24 |
Sep 09 05:32:45 PM UTC 24 |
185400200 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2926029189 |
|
|
Sep 09 05:32:20 PM UTC 24 |
Sep 09 05:32:46 PM UTC 24 |
132742200 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1709798540 |
|
|
Sep 09 05:32:30 PM UTC 24 |
Sep 09 05:32:49 PM UTC 24 |
73696600 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.2576642467 |
|
|
Sep 09 05:32:30 PM UTC 24 |
Sep 09 05:32:49 PM UTC 24 |
45872400 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.2740461148 |
|
|
Sep 09 05:32:26 PM UTC 24 |
Sep 09 05:32:50 PM UTC 24 |
42355500 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1565431472 |
|
|
Sep 09 05:32:28 PM UTC 24 |
Sep 09 05:32:51 PM UTC 24 |
95523200 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.2160135327 |
|
|
Sep 09 05:32:32 PM UTC 24 |
Sep 09 05:32:51 PM UTC 24 |
35850400 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.1264528824 |
|
|
Sep 09 05:32:32 PM UTC 24 |
Sep 09 05:32:52 PM UTC 24 |
54419100 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1623960270 |
|
|
Sep 09 05:32:30 PM UTC 24 |
Sep 09 05:32:52 PM UTC 24 |
45086100 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.3095606709 |
|
|
Sep 09 05:32:34 PM UTC 24 |
Sep 09 05:32:53 PM UTC 24 |
122311900 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.1920435258 |
|
|
Sep 09 05:32:34 PM UTC 24 |
Sep 09 05:32:54 PM UTC 24 |
17009300 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.37753002 |
|
|
Sep 09 05:32:34 PM UTC 24 |
Sep 09 05:32:54 PM UTC 24 |
15823700 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1631714421 |
|
|
Sep 09 05:32:28 PM UTC 24 |
Sep 09 05:32:56 PM UTC 24 |
78391600 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.637075127 |
|
|
Sep 09 05:32:30 PM UTC 24 |
Sep 09 05:32:56 PM UTC 24 |
101086500 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2643963984 |
|
|
Sep 09 05:32:32 PM UTC 24 |
Sep 09 05:32:56 PM UTC 24 |
55588200 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.687371573 |
|
|
Sep 09 05:32:37 PM UTC 24 |
Sep 09 05:32:56 PM UTC 24 |
41823000 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.1915870717 |
|
|
Sep 09 05:32:37 PM UTC 24 |
Sep 09 05:32:57 PM UTC 24 |
26288600 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2571043532 |
|
|
Sep 09 05:32:37 PM UTC 24 |
Sep 09 05:32:58 PM UTC 24 |
18869200 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.996812166 |
|
|
Sep 09 05:32:34 PM UTC 24 |
Sep 09 05:32:58 PM UTC 24 |
221542300 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1587752824 |
|
|
Sep 09 05:32:37 PM UTC 24 |
Sep 09 05:32:59 PM UTC 24 |
15679500 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2734308269 |
|
|
Sep 09 05:32:39 PM UTC 24 |
Sep 09 05:32:59 PM UTC 24 |
27860300 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2905720762 |
|
|
Sep 09 05:32:39 PM UTC 24 |
Sep 09 05:33:00 PM UTC 24 |
37428600 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.1752921189 |
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Sep 09 05:32:41 PM UTC 24 |
Sep 09 05:33:00 PM UTC 24 |
20204400 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.957837461 |
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|
Sep 09 05:32:39 PM UTC 24 |
Sep 09 05:33:01 PM UTC 24 |
43601000 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2460814603 |
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|
Sep 09 05:32:12 PM UTC 24 |
Sep 09 05:33:01 PM UTC 24 |
206536400 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.647585063 |
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|
Sep 09 05:32:41 PM UTC 24 |
Sep 09 05:33:01 PM UTC 24 |
165818000 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.2987715070 |
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|
Sep 09 05:32:41 PM UTC 24 |
Sep 09 05:33:03 PM UTC 24 |
48989800 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2945730601 |
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|
Sep 09 05:32:44 PM UTC 24 |
Sep 09 05:33:04 PM UTC 24 |
37497900 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.3500533748 |
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|
Sep 09 05:32:44 PM UTC 24 |
Sep 09 05:33:05 PM UTC 24 |
18953800 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.1983998195 |
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|
Sep 09 05:32:41 PM UTC 24 |
Sep 09 05:33:06 PM UTC 24 |
46828900 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.1896923140 |
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|
Sep 09 05:32:47 PM UTC 24 |
Sep 09 05:33:06 PM UTC 24 |
54257000 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.54009979 |
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|
Sep 09 05:32:47 PM UTC 24 |
Sep 09 05:33:06 PM UTC 24 |
47732800 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.759927686 |
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Sep 09 05:32:47 PM UTC 24 |
Sep 09 05:33:07 PM UTC 24 |
18258500 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.2075093435 |
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Sep 09 05:32:44 PM UTC 24 |
Sep 09 05:33:07 PM UTC 24 |
35761900 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.3949538627 |
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|
Sep 09 05:32:47 PM UTC 24 |
Sep 09 05:33:08 PM UTC 24 |
14834100 ps |
| T1268 |
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1052090107 |
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Sep 09 05:32:47 PM UTC 24 |
Sep 09 05:33:09 PM UTC 24 |
69387800 ps |