| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.20 | 95.74 | 94.03 | 98.31 | 91.84 | 98.34 | 96.89 | 98.24 |
| T1269 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2646249567 | Sep 09 05:32:47 PM UTC 24 | Sep 09 05:33:12 PM UTC 24 | 44355700 ps | ||
| T248 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2044961451 | Sep 09 05:31:52 PM UTC 24 | Sep 09 05:40:09 PM UTC 24 | 1598775000 ps | ||
| T249 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3036075140 | Sep 09 05:31:42 PM UTC 24 | Sep 09 05:40:46 PM UTC 24 | 1244764700 ps | ||
| T250 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.81193823 | Sep 09 05:32:08 PM UTC 24 | Sep 09 05:41:24 PM UTC 24 | 472269200 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.525827642 | Sep 09 05:32:21 PM UTC 24 | Sep 09 05:41:30 PM UTC 24 | 728597500 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1071098066 | Sep 09 05:29:45 PM UTC 24 | Sep 09 05:41:42 PM UTC 24 | 1702781700 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3354587161 | Sep 09 05:31:59 PM UTC 24 | Sep 09 05:42:13 PM UTC 24 | 660046800 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1156504367 | Sep 09 05:32:17 PM UTC 24 | Sep 09 05:43:17 PM UTC 24 | 184140500 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2380994710 | Sep 09 05:30:54 PM UTC 24 | Sep 09 05:43:22 PM UTC 24 | 439518500 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3787215812 | Sep 09 05:32:12 PM UTC 24 | Sep 09 05:44:18 PM UTC 24 | 4166436200 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4236721658 | Sep 09 05:32:03 PM UTC 24 | Sep 09 05:48:37 PM UTC 24 | 2765802500 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.429975817 | Sep 09 05:31:22 PM UTC 24 | Sep 09 05:49:29 PM UTC 24 | 2800353800 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2628875100 | Sep 09 05:30:15 PM UTC 24 | Sep 09 05:49:30 PM UTC 24 | 9401847000 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3402364058 | Sep 09 05:31:29 PM UTC 24 | Sep 09 05:49:47 PM UTC 24 | 1285321400 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3777333796 | Sep 09 05:30:27 PM UTC 24 | Sep 09 05:51:23 PM UTC 24 | 708330500 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2981638514 | Sep 09 05:31:13 PM UTC 24 | Sep 09 05:52:53 PM UTC 24 | 697336800 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3896772948 | Sep 09 05:30:42 PM UTC 24 | Sep 09 05:53:00 PM UTC 24 | 692596300 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.770517876 | Sep 09 05:29:51 PM UTC 24 | Sep 09 05:53:01 PM UTC 24 | 1296619800 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2456106567 | Sep 09 05:31:34 PM UTC 24 | Sep 09 05:53:39 PM UTC 24 | 721932900 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2682621881 | Sep 09 05:31:05 PM UTC 24 | Sep 09 05:54:30 PM UTC 24 | 763845600 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.500245331 | Sep 09 05:31:51 PM UTC 24 | Sep 09 05:55:06 PM UTC 24 | 1536606100 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3199175620 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 252939800 ps |
| CPU time | 36.44 seconds |
| Started | Sep 09 05:32:57 PM UTC 24 |
| Finished | Sep 09 05:33:35 PM UTC 24 |
| Peak memory | 274544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 99175620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc h_code.3199175620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.3386694143 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 6073274600 ps |
| CPU time | 107.63 seconds |
| Started | Sep 09 05:32:57 PM UTC 24 |
| Finished | Sep 09 05:34:47 PM UTC 24 |
| Peak memory | 274536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3386694143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.3386694143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3025139238 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 318150500 ps |
| CPU time | 36.41 seconds |
| Started | Sep 09 05:29:48 PM UTC 24 |
| Finished | Sep 09 05:30:26 PM UTC 24 |
| Peak memory | 284504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3025139238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3025139238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.247990062 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 90012000 ps |
| CPU time | 234.17 seconds |
| Started | Sep 09 05:35:33 PM UTC 24 |
| Finished | Sep 09 05:39:31 PM UTC 24 |
| Peak memory | 270796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247990062 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.247990062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.1926195226 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 28907600 ps |
| CPU time | 55.58 seconds |
| Started | Sep 09 05:33:33 PM UTC 24 |
| Finished | Sep 09 05:34:31 PM UTC 24 |
| Peak memory | 285376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926195226 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.1926195226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.888240498 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 383129600 ps |
| CPU time | 29.75 seconds |
| Started | Sep 09 05:31:11 PM UTC 24 |
| Finished | Sep 09 05:31:43 PM UTC 24 |
| Peak memory | 284504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=888240498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.888240498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.870293537 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4889889400 ps |
| CPU time | 6082.85 seconds |
| Started | Sep 09 05:44:27 PM UTC 24 |
| Finished | Sep 09 07:26:50 PM UTC 24 |
| Peak memory | 320292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870293537 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.870293537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.3264676531 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 83106124400 ps |
| CPU time | 864.26 seconds |
| Started | Sep 09 05:34:46 PM UTC 24 |
| Finished | Sep 09 05:49:21 PM UTC 24 |
| Peak memory | 272924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3264676531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. flash_ctrl_rma_err.3264676531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.2893528581 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 493948600 ps |
| CPU time | 66.92 seconds |
| Started | Sep 09 05:33:06 PM UTC 24 |
| Finished | Sep 09 05:34:15 PM UTC 24 |
| Peak memory | 275136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289 3528581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser r_address.2893528581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2130553357 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7495078000 ps |
| CPU time | 120.77 seconds |
| Started | Sep 09 05:33:00 PM UTC 24 |
| Finished | Sep 09 05:35:03 PM UTC 24 |
| Peak memory | 270636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130553357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2130553357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.3676583535 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 9810457600 ps |
| CPU time | 198.97 seconds |
| Started | Sep 09 05:33:06 PM UTC 24 |
| Finished | Sep 09 05:36:28 PM UTC 24 |
| Peak memory | 305852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3676583535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.3676583535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3231902517 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 9217520600 ps |
| CPU time | 88.27 seconds |
| Started | Sep 09 05:29:47 PM UTC 24 |
| Finished | Sep 09 05:31:17 PM UTC 24 |
| Peak memory | 272100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231902517 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.3231902517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.2392082646 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1969915100 ps |
| CPU time | 87.88 seconds |
| Started | Sep 09 05:47:32 PM UTC 24 |
| Finished | Sep 09 05:49:02 PM UTC 24 |
| Peak memory | 270636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392082646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.2392082646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.2983577582 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 15113100 ps |
| CPU time | 22.01 seconds |
| Started | Sep 09 05:45:09 PM UTC 24 |
| Finished | Sep 09 05:45:33 PM UTC 24 |
| Peak memory | 273168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2983577582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2983577582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.953586226 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1181722000 ps |
| CPU time | 105.95 seconds |
| Started | Sep 09 05:32:52 PM UTC 24 |
| Finished | Sep 09 05:34:40 PM UTC 24 |
| Peak memory | 275036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953586226 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.953586226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3381752525 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 204783500 ps |
| CPU time | 22.63 seconds |
| Started | Sep 09 05:30:27 PM UTC 24 |
| Finished | Sep 09 05:30:51 PM UTC 24 |
| Peak memory | 274228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381752525 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.3381752525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2857095289 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 16651596000 ps |
| CPU time | 251.3 seconds |
| Started | Sep 09 05:33:22 PM UTC 24 |
| Finished | Sep 09 05:37:37 PM UTC 24 |
| Peak memory | 301668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2857095289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_intr_rd_slow_flash.2857095289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.86747096 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 167365698300 ps |
| CPU time | 2006.08 seconds |
| Started | Sep 09 05:35:17 PM UTC 24 |
| Finished | Sep 09 06:09:05 PM UTC 24 |
| Peak memory | 277460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86747096 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.86747096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.1938708451 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 48201800 ps |
| CPU time | 26.39 seconds |
| Started | Sep 09 05:34:32 PM UTC 24 |
| Finished | Sep 09 05:35:00 PM UTC 24 |
| Peak memory | 270980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938708451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_wr_intg.1938708451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.563006603 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 152077500 ps |
| CPU time | 184.31 seconds |
| Started | Sep 09 06:07:25 PM UTC 24 |
| Finished | Sep 09 06:10:33 PM UTC 24 |
| Peak memory | 271044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563006603 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.563006603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.546552720 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 55789300 ps |
| CPU time | 27.96 seconds |
| Started | Sep 09 05:31:16 PM UTC 24 |
| Finished | Sep 09 05:31:45 PM UTC 24 |
| Peak memory | 271968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546552720 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.546552720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.3716159848 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 130714500 ps |
| CPU time | 138.31 seconds |
| Started | Sep 09 06:50:16 PM UTC 24 |
| Finished | Sep 09 06:52:37 PM UTC 24 |
| Peak memory | 270640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716159848 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.3716159848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4236721658 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2765802500 ps |
| CPU time | 983.1 seconds |
| Started | Sep 09 05:32:03 PM UTC 24 |
| Finished | Sep 09 05:48:37 PM UTC 24 |
| Peak memory | 274208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236721658 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.4236721658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.2625821658 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7228523100 ps |
| CPU time | 77.34 seconds |
| Started | Sep 09 05:39:32 PM UTC 24 |
| Finished | Sep 09 05:40:51 PM UTC 24 |
| Peak memory | 275040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625821658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2625821658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.749817179 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3229933700 ps |
| CPU time | 193.54 seconds |
| Started | Sep 09 05:33:09 PM UTC 24 |
| Finished | Sep 09 05:36:25 PM UTC 24 |
| Peak memory | 295624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=749817179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.flash_ctrl_rw_derr.749817179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.680726535 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 30946578800 ps |
| CPU time | 356.82 seconds |
| Started | Sep 09 05:35:34 PM UTC 24 |
| Finished | Sep 09 05:41:36 PM UTC 24 |
| Peak memory | 283072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=680726535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_mp_regions.680726535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2906666777 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 138513100 ps |
| CPU time | 26.41 seconds |
| Started | Sep 09 05:35:03 PM UTC 24 |
| Finished | Sep 09 05:35:31 PM UTC 24 |
| Peak memory | 268932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906666777 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2906666777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.3076158832 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2480044800 ps |
| CPU time | 127.76 seconds |
| Started | Sep 09 05:56:08 PM UTC 24 |
| Finished | Sep 09 05:58:18 PM UTC 24 |
| Peak memory | 273056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076158832 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.3076158832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.620289488 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 74965200 ps |
| CPU time | 50.43 seconds |
| Started | Sep 09 05:33:39 PM UTC 24 |
| Finished | Sep 09 05:34:31 PM UTC 24 |
| Peak memory | 287416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620289488 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.620289488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.898300605 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 53711000 ps |
| CPU time | 182.65 seconds |
| Started | Sep 09 06:32:20 PM UTC 24 |
| Finished | Sep 09 06:35:25 PM UTC 24 |
| Peak memory | 271044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898300605 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.898300605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.2334021869 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 79843500 ps |
| CPU time | 171.29 seconds |
| Started | Sep 09 06:49:54 PM UTC 24 |
| Finished | Sep 09 06:52:48 PM UTC 24 |
| Peak memory | 271224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334021869 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.2334021869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.3704917737 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3742333700 ps |
| CPU time | 76.48 seconds |
| Started | Sep 09 05:36:21 PM UTC 24 |
| Finished | Sep 09 05:37:39 PM UTC 24 |
| Peak memory | 270640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704917737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3704917737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.1082570313 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 248426826800 ps |
| CPU time | 2994.37 seconds |
| Started | Sep 09 05:51:53 PM UTC 24 |
| Finished | Sep 09 06:42:19 PM UTC 24 |
| Peak memory | 277820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082570313 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.1082570313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.609211848 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 845019400 ps |
| CPU time | 62.41 seconds |
| Started | Sep 09 05:29:48 PM UTC 24 |
| Finished | Sep 09 05:30:52 PM UTC 24 |
| Peak memory | 272160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609211848 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.609211848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.882676224 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 31682500 ps |
| CPU time | 23.79 seconds |
| Started | Sep 09 05:30:16 PM UTC 24 |
| Finished | Sep 09 05:30:41 PM UTC 24 |
| Peak memory | 274136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882676224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.882676224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.1763793742 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 5754409100 ps |
| CPU time | 196.28 seconds |
| Started | Sep 09 05:35:15 PM UTC 24 |
| Finished | Sep 09 05:38:34 PM UTC 24 |
| Peak memory | 272908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763793742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.1763793742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.1727579998 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 30201192700 ps |
| CPU time | 277.8 seconds |
| Started | Sep 09 05:43:33 PM UTC 24 |
| Finished | Sep 09 05:48:14 PM UTC 24 |
| Peak memory | 293580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727579998 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.1727579998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3714441726 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 10039161300 ps |
| CPU time | 60.83 seconds |
| Started | Sep 09 05:40:32 PM UTC 24 |
| Finished | Sep 09 05:41:36 PM UTC 24 |
| Peak memory | 291800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3714441726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.3714441726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1715593407 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 25343100 ps |
| CPU time | 16.62 seconds |
| Started | Sep 09 06:10:33 PM UTC 24 |
| Finished | Sep 09 06:10:51 PM UTC 24 |
| Peak memory | 275140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1715593407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_lcmgr_intg.1715593407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2999247206 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 6937988600 ps |
| CPU time | 172.49 seconds |
| Started | Sep 09 05:33:09 PM UTC 24 |
| Finished | Sep 09 05:36:04 PM UTC 24 |
| Peak memory | 301768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2999247206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.2999247206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3354742508 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 60686100 ps |
| CPU time | 27.51 seconds |
| Started | Sep 09 05:29:45 PM UTC 24 |
| Finished | Sep 09 05:30:14 PM UTC 24 |
| Peak memory | 272052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354742508 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3354742508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.2867479541 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 14298095100 ps |
| CPU time | 120.18 seconds |
| Started | Sep 09 05:33:00 PM UTC 24 |
| Finished | Sep 09 05:35:02 PM UTC 24 |
| Peak memory | 272704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867479541 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.2867479541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3402364058 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1285321400 ps |
| CPU time | 1085.64 seconds |
| Started | Sep 09 05:31:29 PM UTC 24 |
| Finished | Sep 09 05:49:47 PM UTC 24 |
| Peak memory | 272268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402364058 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.3402364058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.624314458 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 57484200 ps |
| CPU time | 27.08 seconds |
| Started | Sep 09 05:30:42 PM UTC 24 |
| Finished | Sep 09 05:31:10 PM UTC 24 |
| Peak memory | 274152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624314458 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.624314458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.2814285857 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5330306200 ps |
| CPU time | 204.17 seconds |
| Started | Sep 09 05:43:05 PM UTC 24 |
| Finished | Sep 09 05:46:32 PM UTC 24 |
| Peak memory | 297668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2814285857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.flash_ctrl_rw_derr.2814285857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.1097048969 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 37476400 ps |
| CPU time | 25.41 seconds |
| Started | Sep 09 05:55:35 PM UTC 24 |
| Finished | Sep 09 05:56:02 PM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1097048969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1097048969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.609416205 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 100158715100 ps |
| CPU time | 877.89 seconds |
| Started | Sep 09 05:46:16 PM UTC 24 |
| Finished | Sep 09 06:01:05 PM UTC 24 |
| Peak memory | 274748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609416205 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.609416205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.1694877633 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 167172200 ps |
| CPU time | 29.82 seconds |
| Started | Sep 09 05:34:45 PM UTC 24 |
| Finished | Sep 09 05:35:16 PM UTC 24 |
| Peak memory | 273432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694877633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.1694877633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1768169245 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 462703400 ps |
| CPU time | 43.4 seconds |
| Started | Sep 09 05:55:22 PM UTC 24 |
| Finished | Sep 09 05:56:07 PM UTC 24 |
| Peak memory | 272996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768169 245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_f s_sup.1768169245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.2345370290 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 15185600 ps |
| CPU time | 36.58 seconds |
| Started | Sep 09 06:31:38 PM UTC 24 |
| Finished | Sep 09 06:32:16 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2345370290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ ctrl_disable.2345370290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2576296948 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 68948200 ps |
| CPU time | 45.47 seconds |
| Started | Sep 09 05:34:24 PM UTC 24 |
| Finished | Sep 09 05:35:11 PM UTC 24 |
| Peak memory | 285372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257629694 8 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.2576296948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2682621881 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 763845600 ps |
| CPU time | 1388.85 seconds |
| Started | Sep 09 05:31:05 PM UTC 24 |
| Finished | Sep 09 05:54:30 PM UTC 24 |
| Peak memory | 276288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682621881 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.2682621881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.677485512 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 865393500 ps |
| CPU time | 34.92 seconds |
| Started | Sep 09 05:45:07 PM UTC 24 |
| Finished | Sep 09 05:45:43 PM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=677485512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.677485512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.4058362743 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3209556200 ps |
| CPU time | 485.8 seconds |
| Started | Sep 09 05:33:02 PM UTC 24 |
| Finished | Sep 09 05:41:14 PM UTC 24 |
| Peak memory | 320144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058362743 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.4058362743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.4262920892 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 948456800 ps |
| CPU time | 3448.05 seconds |
| Started | Sep 09 05:35:44 PM UTC 24 |
| Finished | Sep 09 06:33:50 PM UTC 24 |
| Peak memory | 277740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 62920892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl _error_prog_type.4262920892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.4166578093 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5725894200 ps |
| CPU time | 150.83 seconds |
| Started | Sep 09 05:54:17 PM UTC 24 |
| Finished | Sep 09 05:56:50 PM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166578093 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.4166578093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1522925840 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 893651200 ps |
| CPU time | 59.12 seconds |
| Started | Sep 09 05:30:12 PM UTC 24 |
| Finished | Sep 09 05:31:13 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522925840 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.1522925840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.500245331 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1536606100 ps |
| CPU time | 1380.08 seconds |
| Started | Sep 09 05:31:51 PM UTC 24 |
| Finished | Sep 09 05:55:06 PM UTC 24 |
| Peak memory | 276348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500245331 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.500245331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1134177993 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 336765100 ps |
| CPU time | 54.64 seconds |
| Started | Sep 09 06:10:06 PM UTC 24 |
| Finished | Sep 09 06:11:02 PM UTC 24 |
| Peak memory | 287780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134177993 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.1134177993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.1768277971 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 39843900 ps |
| CPU time | 23.57 seconds |
| Started | Sep 09 06:06:29 PM UTC 24 |
| Finished | Sep 09 06:06:54 PM UTC 24 |
| Peak memory | 294812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768277971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1768277971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.865922735 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1104735000 ps |
| CPU time | 42.15 seconds |
| Started | Sep 09 05:35:36 PM UTC 24 |
| Finished | Sep 09 05:36:20 PM UTC 24 |
| Peak memory | 272900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86 5922735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch _code.865922735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.4081478633 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 742991700 ps |
| CPU time | 1075.79 seconds |
| Started | Sep 09 05:32:58 PM UTC 24 |
| Finished | Sep 09 05:51:04 PM UTC 24 |
| Peak memory | 285156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081478633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.4081478633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.291812739 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 54223700 ps |
| CPU time | 17 seconds |
| Started | Sep 09 05:51:05 PM UTC 24 |
| Finished | Sep 09 05:51:23 PM UTC 24 |
| Peak memory | 271044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=291812739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash _ctrl_lcmgr_intg.291812739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2504664496 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 10012366900 ps |
| CPU time | 156 seconds |
| Started | Sep 09 06:18:54 PM UTC 24 |
| Finished | Sep 09 06:21:33 PM UTC 24 |
| Peak memory | 338960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2504664496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2504664496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2552572478 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 15681600 ps |
| CPU time | 28.97 seconds |
| Started | Sep 09 05:34:40 PM UTC 24 |
| Finished | Sep 09 05:35:11 PM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2552572478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2552572478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.1827735637 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 87478700 ps |
| CPU time | 222.22 seconds |
| Started | Sep 09 05:56:11 PM UTC 24 |
| Finished | Sep 09 05:59:57 PM UTC 24 |
| Peak memory | 270636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827735637 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.1827735637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.2150329001 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 28961900 ps |
| CPU time | 26.92 seconds |
| Started | Sep 09 06:06:18 PM UTC 24 |
| Finished | Sep 09 06:06:46 PM UTC 24 |
| Peak memory | 275440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2150329001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_c trl_disable.2150329001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.2227090079 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12724700 ps |
| CPU time | 22.11 seconds |
| Started | Sep 09 05:34:32 PM UTC 24 |
| Finished | Sep 09 05:34:56 PM UTC 24 |
| Peak memory | 275108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2227090079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.2227090079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3205806279 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 10012972700 ps |
| CPU time | 265.06 seconds |
| Started | Sep 09 05:34:57 PM UTC 24 |
| Finished | Sep 09 05:39:25 PM UTC 24 |
| Peak memory | 342984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3205806279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3205806279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1813969164 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 48987800 ps |
| CPU time | 23.43 seconds |
| Started | Sep 09 05:34:50 PM UTC 24 |
| Finished | Sep 09 05:35:14 PM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1813969164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1813969164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3702703632 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 16569600 ps |
| CPU time | 21.89 seconds |
| Started | Sep 09 05:32:06 PM UTC 24 |
| Finished | Sep 09 05:32:29 PM UTC 24 |
| Peak memory | 272048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702703632 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.3702703632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1156504367 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 184140500 ps |
| CPU time | 651.74 seconds |
| Started | Sep 09 05:32:17 PM UTC 24 |
| Finished | Sep 09 05:43:17 PM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156504367 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.1156504367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.3502968244 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1890281800 ps |
| CPU time | 92.11 seconds |
| Started | Sep 09 05:34:02 PM UTC 24 |
| Finished | Sep 09 05:35:36 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502968244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3502968244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.1456842471 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 40588400 ps |
| CPU time | 48.14 seconds |
| Started | Sep 09 06:18:09 PM UTC 24 |
| Finished | Sep 09 06:18:59 PM UTC 24 |
| Peak memory | 287776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1456842471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c trl_rw_evict_all_en.1456842471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1017702409 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 11289839200 ps |
| CPU time | 99.43 seconds |
| Started | Sep 09 06:18:21 PM UTC 24 |
| Finished | Sep 09 06:20:02 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017702409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1017702409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.43970977 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 90535100 ps |
| CPU time | 46.19 seconds |
| Started | Sep 09 06:36:17 PM UTC 24 |
| Finished | Sep 09 06:37:05 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=43970977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctr l_rw_evict_all_en.43970977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.2976322900 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1192006800 ps |
| CPU time | 98.05 seconds |
| Started | Sep 09 06:39:59 PM UTC 24 |
| Finished | Sep 09 06:41:40 PM UTC 24 |
| Peak memory | 275040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976322900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.2976322900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.3595356841 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1395460500 ps |
| CPU time | 431.07 seconds |
| Started | Sep 09 05:32:54 PM UTC 24 |
| Finished | Sep 09 05:40:10 PM UTC 24 |
| Peak memory | 274908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595356841 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3595356841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.789692692 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4248710100 ps |
| CPU time | 155.82 seconds |
| Started | Sep 09 06:28:27 PM UTC 24 |
| Finished | Sep 09 06:31:06 PM UTC 24 |
| Peak memory | 274776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789692692 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.789692692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.1462123476 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 43340700 ps |
| CPU time | 56.25 seconds |
| Started | Sep 09 05:39:06 PM UTC 24 |
| Finished | Sep 09 05:40:04 PM UTC 24 |
| Peak memory | 287456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462123476 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.1462123476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.3420118129 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 816359600 ps |
| CPU time | 28.8 seconds |
| Started | Sep 09 05:34:38 PM UTC 24 |
| Finished | Sep 09 05:35:09 PM UTC 24 |
| Peak memory | 275456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3420118129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3420118129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.1240076788 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 15105500 ps |
| CPU time | 16.22 seconds |
| Started | Sep 09 05:40:11 PM UTC 24 |
| Finished | Sep 09 05:40:28 PM UTC 24 |
| Peak memory | 282628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240076788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1240076788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.4290880825 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3135814600 ps |
| CPU time | 6528.11 seconds |
| Started | Sep 09 05:39:31 PM UTC 24 |
| Finished | Sep 09 07:29:25 PM UTC 24 |
| Peak memory | 316224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290880825 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.4290880825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.3009267976 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1757609900 ps |
| CPU time | 56.35 seconds |
| Started | Sep 09 05:34:34 PM UTC 24 |
| Finished | Sep 09 05:35:32 PM UTC 24 |
| Peak memory | 273356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009267 976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_f s_sup.3009267976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.3963244808 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 194759736100 ps |
| CPU time | 2197.09 seconds |
| Started | Sep 09 05:32:57 PM UTC 24 |
| Finished | Sep 09 06:09:57 PM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963244808 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.3963244808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4283130396 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 241047600 ps |
| CPU time | 29.07 seconds |
| Started | Sep 09 05:32:08 PM UTC 24 |
| Finished | Sep 09 05:32:39 PM UTC 24 |
| Peak memory | 274160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283130396 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.4283130396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.4056994345 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 163717400 ps |
| CPU time | 25.09 seconds |
| Started | Sep 09 05:39:59 PM UTC 24 |
| Finished | Sep 09 05:40:25 PM UTC 24 |
| Peak memory | 275076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056994345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_wr_intg.4056994345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.1309816142 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 11761225600 ps |
| CPU time | 199.55 seconds |
| Started | Sep 09 05:53:44 PM UTC 24 |
| Finished | Sep 09 05:57:07 PM UTC 24 |
| Peak memory | 291764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309816142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.1309816142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.518145303 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13139200 ps |
| CPU time | 38.86 seconds |
| Started | Sep 09 05:33:42 PM UTC 24 |
| Finished | Sep 09 05:34:23 PM UTC 24 |
| Peak memory | 285428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=518145303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct rl_disable.518145303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2237006450 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 77240600 ps |
| CPU time | 27.89 seconds |
| Started | Sep 09 05:34:45 PM UTC 24 |
| Finished | Sep 09 05:35:14 PM UTC 24 |
| Peak memory | 272952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237006450 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.2237006450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2557207388 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 429565200 ps |
| CPU time | 76.87 seconds |
| Started | Sep 09 06:16:34 PM UTC 24 |
| Finished | Sep 09 06:17:52 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557207388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2557207388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.4217191438 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 26783700 ps |
| CPU time | 22.04 seconds |
| Started | Sep 09 06:18:50 PM UTC 24 |
| Finished | Sep 09 06:19:13 PM UTC 24 |
| Peak memory | 271020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4217191438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.4217191438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.2423447632 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 34722800 ps |
| CPU time | 27.05 seconds |
| Started | Sep 09 06:20:44 PM UTC 24 |
| Finished | Sep 09 06:21:13 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2423447632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ ctrl_disable.2423447632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.980722312 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1871326200 ps |
| CPU time | 82.67 seconds |
| Started | Sep 09 06:25:53 PM UTC 24 |
| Finished | Sep 09 06:27:17 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980722312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.980722312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.135910862 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 16433400 ps |
| CPU time | 41.7 seconds |
| Started | Sep 09 06:27:44 PM UTC 24 |
| Finished | Sep 09 06:28:27 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=135910862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c trl_disable.135910862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.640321200 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 30494100 ps |
| CPU time | 26 seconds |
| Started | Sep 09 06:35:34 PM UTC 24 |
| Finished | Sep 09 06:36:01 PM UTC 24 |
| Peak memory | 285332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=640321200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c trl_disable.640321200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.407280344 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 20595300 ps |
| CPU time | 33.32 seconds |
| Started | Sep 09 06:37:56 PM UTC 24 |
| Finished | Sep 09 06:38:31 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=407280344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_c trl_disable.407280344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.211468712 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 387983800 ps |
| CPU time | 57.92 seconds |
| Started | Sep 09 06:38:05 PM UTC 24 |
| Finished | Sep 09 06:39:05 PM UTC 24 |
| Peak memory | 274784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211468712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.211468712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.2233386206 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4863236800 ps |
| CPU time | 68.71 seconds |
| Started | Sep 09 06:47:20 PM UTC 24 |
| Finished | Sep 09 06:48:32 PM UTC 24 |
| Peak memory | 272868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233386206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2233386206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1935464315 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2163487400 ps |
| CPU time | 100.87 seconds |
| Started | Sep 09 05:33:13 PM UTC 24 |
| Finished | Sep 09 05:34:56 PM UTC 24 |
| Peak memory | 271100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935464315 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.1935464315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.1100043867 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2627612600 ps |
| CPU time | 140.2 seconds |
| Started | Sep 09 05:32:52 PM UTC 24 |
| Finished | Sep 09 05:35:14 PM UTC 24 |
| Peak memory | 272704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100043867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1100043867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.1335105355 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 130156782100 ps |
| CPU time | 916.93 seconds |
| Started | Sep 09 06:34:06 PM UTC 24 |
| Finished | Sep 09 06:49:34 PM UTC 24 |
| Peak memory | 274736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335105355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_res et.1335105355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.1210476561 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 894006600 ps |
| CPU time | 18.19 seconds |
| Started | Sep 09 05:55:31 PM UTC 24 |
| Finished | Sep 09 05:55:51 PM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1210476561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.1210476561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3339464122 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 12084050300 ps |
| CPU time | 228.91 seconds |
| Started | Sep 09 06:27:15 PM UTC 24 |
| Finished | Sep 09 06:31:07 PM UTC 24 |
| Peak memory | 303744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3339464122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_intr_rd_slow_flash.3339464122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.1495035004 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 38124485200 ps |
| CPU time | 2727.42 seconds |
| Started | Sep 09 05:33:00 PM UTC 24 |
| Finished | Sep 09 06:18:54 PM UTC 24 |
| Peak memory | 277852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495035004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.1495035004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.1791407686 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 345467474800 ps |
| CPU time | 2576.52 seconds |
| Started | Sep 09 05:41:25 PM UTC 24 |
| Finished | Sep 09 06:24:48 PM UTC 24 |
| Peak memory | 277804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791407686 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.1791407686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.807383684 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 954730000 ps |
| CPU time | 138.53 seconds |
| Started | Sep 09 05:54:16 PM UTC 24 |
| Finished | Sep 09 05:56:37 PM UTC 24 |
| Peak memory | 291528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=807383684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_oversize_error.807383684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2318526888 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 21027100 ps |
| CPU time | 42.71 seconds |
| Started | Sep 09 05:29:47 PM UTC 24 |
| Finished | Sep 09 05:30:31 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318526888 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.2318526888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1250176619 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 74481200 ps |
| CPU time | 20.53 seconds |
| Started | Sep 09 05:29:47 PM UTC 24 |
| Finished | Sep 09 05:30:08 PM UTC 24 |
| Peak memory | 274140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250176619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.1250176619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3822853289 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 19980700 ps |
| CPU time | 27.31 seconds |
| Started | Sep 09 05:29:47 PM UTC 24 |
| Finished | Sep 09 05:30:15 PM UTC 24 |
| Peak memory | 272092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822853289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.3822853289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.620669932 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 27151400 ps |
| CPU time | 15.49 seconds |
| Started | Sep 09 05:29:45 PM UTC 24 |
| Finished | Sep 09 05:30:02 PM UTC 24 |
| Peak memory | 272284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620669932 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.620669932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3953465280 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 106982300 ps |
| CPU time | 24.57 seconds |
| Started | Sep 09 05:29:48 PM UTC 24 |
| Finished | Sep 09 05:30:14 PM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3953465280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ same_csr_outstanding.3953465280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.490963841 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 15684000 ps |
| CPU time | 26.73 seconds |
| Started | Sep 09 05:29:45 PM UTC 24 |
| Finished | Sep 09 05:30:13 PM UTC 24 |
| Peak memory | 261164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490 963841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shad ow_reg_errors.490963841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2325408885 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 27788400 ps |
| CPU time | 27.17 seconds |
| Started | Sep 09 05:29:45 PM UTC 24 |
| Finished | Sep 09 05:30:14 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2325408885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2325408885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.410689845 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 274529800 ps |
| CPU time | 21.12 seconds |
| Started | Sep 09 05:29:45 PM UTC 24 |
| Finished | Sep 09 05:30:08 PM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410689845 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.410689845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1071098066 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1702781700 ps |
| CPU time | 707.74 seconds |
| Started | Sep 09 05:29:45 PM UTC 24 |
| Finished | Sep 09 05:41:42 PM UTC 24 |
| Peak memory | 275608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071098066 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.1071098066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.75582770 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 20999776300 ps |
| CPU time | 116.89 seconds |
| Started | Sep 09 05:30:11 PM UTC 24 |
| Finished | Sep 09 05:32:11 PM UTC 24 |
| Peak memory | 272160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75582770 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.75582770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1023470652 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 133504700 ps |
| CPU time | 42.61 seconds |
| Started | Sep 09 05:30:09 PM UTC 24 |
| Finished | Sep 09 05:30:53 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023470652 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.1023470652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.4286345876 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 25445600 ps |
| CPU time | 23.23 seconds |
| Started | Sep 09 05:30:13 PM UTC 24 |
| Finished | Sep 09 05:30:37 PM UTC 24 |
| Peak memory | 284504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4286345876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.4286345876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4038798724 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 43437000 ps |
| CPU time | 23.58 seconds |
| Started | Sep 09 05:30:10 PM UTC 24 |
| Finished | Sep 09 05:30:35 PM UTC 24 |
| Peak memory | 272088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038798724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.4038798724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.4082942056 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 29921700 ps |
| CPU time | 21.7 seconds |
| Started | Sep 09 05:29:58 PM UTC 24 |
| Finished | Sep 09 05:30:21 PM UTC 24 |
| Peak memory | 271988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082942056 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.4082942056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1975354945 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 55936800 ps |
| CPU time | 24.44 seconds |
| Started | Sep 09 05:30:09 PM UTC 24 |
| Finished | Sep 09 05:30:35 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975354945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.1975354945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2080496316 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 19962500 ps |
| CPU time | 18.29 seconds |
| Started | Sep 09 05:30:02 PM UTC 24 |
| Finished | Sep 09 05:30:22 PM UTC 24 |
| Peak memory | 272160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080496316 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.2080496316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2248169285 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 62025400 ps |
| CPU time | 27.4 seconds |
| Started | Sep 09 05:30:13 PM UTC 24 |
| Finished | Sep 09 05:30:42 PM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2248169285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ same_csr_outstanding.2248169285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.194447666 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 47350400 ps |
| CPU time | 18.75 seconds |
| Started | Sep 09 05:29:52 PM UTC 24 |
| Finished | Sep 09 05:30:12 PM UTC 24 |
| Peak memory | 261856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194 447666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shad ow_reg_errors.194447666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2674728810 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 12759800 ps |
| CPU time | 24.45 seconds |
| Started | Sep 09 05:29:57 PM UTC 24 |
| Finished | Sep 09 05:30:23 PM UTC 24 |
| Peak memory | 261852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2674728810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2674728810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2986601089 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 36557800 ps |
| CPU time | 28.92 seconds |
| Started | Sep 09 05:29:50 PM UTC 24 |
| Finished | Sep 09 05:30:20 PM UTC 24 |
| Peak memory | 274164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986601089 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2986601089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.770517876 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1296619800 ps |
| CPU time | 1373.58 seconds |
| Started | Sep 09 05:29:51 PM UTC 24 |
| Finished | Sep 09 05:53:01 PM UTC 24 |
| Peak memory | 276356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770517876 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.770517876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2400121954 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 50893800 ps |
| CPU time | 22.41 seconds |
| Started | Sep 09 05:31:39 PM UTC 24 |
| Finished | Sep 09 05:32:03 PM UTC 24 |
| Peak memory | 286556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2400121954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.2400121954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1814793551 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 487652100 ps |
| CPU time | 25.64 seconds |
| Started | Sep 09 05:31:38 PM UTC 24 |
| Finished | Sep 09 05:32:05 PM UTC 24 |
| Peak memory | 274140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814793551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.1814793551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3448680838 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 53742900 ps |
| CPU time | 22.04 seconds |
| Started | Sep 09 05:31:38 PM UTC 24 |
| Finished | Sep 09 05:32:02 PM UTC 24 |
| Peak memory | 271988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448680838 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.3448680838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3529961989 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 297755800 ps |
| CPU time | 26.65 seconds |
| Started | Sep 09 05:31:39 PM UTC 24 |
| Finished | Sep 09 05:32:07 PM UTC 24 |
| Peak memory | 272088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3529961989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl _same_csr_outstanding.3529961989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1559320769 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 24313000 ps |
| CPU time | 21.92 seconds |
| Started | Sep 09 05:31:37 PM UTC 24 |
| Finished | Sep 09 05:32:00 PM UTC 24 |
| Peak memory | 261852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155 9320769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sh adow_reg_errors.1559320769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3914102558 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 24788000 ps |
| CPU time | 19.55 seconds |
| Started | Sep 09 05:31:37 PM UTC 24 |
| Finished | Sep 09 05:31:58 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3914102558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.f lash_ctrl_shadow_reg_errors_with_csr_rw.3914102558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3115838422 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 35194000 ps |
| CPU time | 27.33 seconds |
| Started | Sep 09 05:31:34 PM UTC 24 |
| Finished | Sep 09 05:32:03 PM UTC 24 |
| Peak memory | 274088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115838422 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.3115838422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2456106567 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 721932900 ps |
| CPU time | 1310.82 seconds |
| Started | Sep 09 05:31:34 PM UTC 24 |
| Finished | Sep 09 05:53:39 PM UTC 24 |
| Peak memory | 276348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456106567 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.2456106567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1022497825 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 25899300 ps |
| CPU time | 22.04 seconds |
| Started | Sep 09 05:31:46 PM UTC 24 |
| Finished | Sep 09 05:32:10 PM UTC 24 |
| Peak memory | 284512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1022497825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1022497825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.387453283 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 40342200 ps |
| CPU time | 21.13 seconds |
| Started | Sep 09 05:31:46 PM UTC 24 |
| Finished | Sep 09 05:32:09 PM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387453283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.387453283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3382807577 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 69510200 ps |
| CPU time | 23.44 seconds |
| Started | Sep 09 05:31:44 PM UTC 24 |
| Finished | Sep 09 05:32:09 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382807577 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.3382807577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2023603738 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 175404100 ps |
| CPU time | 22.7 seconds |
| Started | Sep 09 05:31:46 PM UTC 24 |
| Finished | Sep 09 05:32:10 PM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2023603738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl _same_csr_outstanding.2023603738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3210940126 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 27365400 ps |
| CPU time | 15.55 seconds |
| Started | Sep 09 05:31:43 PM UTC 24 |
| Finished | Sep 09 05:32:00 PM UTC 24 |
| Peak memory | 261756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321 0940126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh adow_reg_errors.3210940126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.716186207 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 30828400 ps |
| CPU time | 21.99 seconds |
| Started | Sep 09 05:31:43 PM UTC 24 |
| Finished | Sep 09 05:32:06 PM UTC 24 |
| Peak memory | 261848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=716186207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_shadow_reg_errors_with_csr_rw.716186207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.515208078 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 67403800 ps |
| CPU time | 24.74 seconds |
| Started | Sep 09 05:31:41 PM UTC 24 |
| Finished | Sep 09 05:32:07 PM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515208078 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.515208078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3036075140 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1244764700 ps |
| CPU time | 538.04 seconds |
| Started | Sep 09 05:31:42 PM UTC 24 |
| Finished | Sep 09 05:40:46 PM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036075140 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.3036075140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2374549642 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 42330800 ps |
| CPU time | 26.21 seconds |
| Started | Sep 09 05:31:52 PM UTC 24 |
| Finished | Sep 09 05:32:19 PM UTC 24 |
| Peak memory | 290656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2374549642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2374549642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2931172740 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 113353900 ps |
| CPU time | 17.68 seconds |
| Started | Sep 09 05:31:52 PM UTC 24 |
| Finished | Sep 09 05:32:11 PM UTC 24 |
| Peak memory | 273988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931172740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.2931172740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.4014061292 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 58733800 ps |
| CPU time | 20.9 seconds |
| Started | Sep 09 05:31:51 PM UTC 24 |
| Finished | Sep 09 05:32:13 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014061292 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.4014061292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1675325187 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 312085500 ps |
| CPU time | 23.28 seconds |
| Started | Sep 09 05:31:52 PM UTC 24 |
| Finished | Sep 09 05:32:16 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1675325187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl _same_csr_outstanding.1675325187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2579129524 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 14105000 ps |
| CPU time | 18.87 seconds |
| Started | Sep 09 05:31:51 PM UTC 24 |
| Finished | Sep 09 05:32:11 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257 9129524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sh adow_reg_errors.2579129524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3684161154 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 26037900 ps |
| CPU time | 17.28 seconds |
| Started | Sep 09 05:31:51 PM UTC 24 |
| Finished | Sep 09 05:32:09 PM UTC 24 |
| Peak memory | 261856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3684161154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f lash_ctrl_shadow_reg_errors_with_csr_rw.3684161154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.314987224 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 97748600 ps |
| CPU time | 26.96 seconds |
| Started | Sep 09 05:31:48 PM UTC 24 |
| Finished | Sep 09 05:32:17 PM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314987224 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.314987224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3426535429 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 181888500 ps |
| CPU time | 20.91 seconds |
| Started | Sep 09 05:31:57 PM UTC 24 |
| Finished | Sep 09 05:32:19 PM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3426535429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3426535429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.854913799 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 21180600 ps |
| CPU time | 20.4 seconds |
| Started | Sep 09 05:31:54 PM UTC 24 |
| Finished | Sep 09 05:32:16 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854913799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.854913799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1653634491 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 57831000 ps |
| CPU time | 19.83 seconds |
| Started | Sep 09 05:31:54 PM UTC 24 |
| Finished | Sep 09 05:32:15 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653634491 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.1653634491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3970289001 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 70484200 ps |
| CPU time | 27.27 seconds |
| Started | Sep 09 05:31:55 PM UTC 24 |
| Finished | Sep 09 05:32:24 PM UTC 24 |
| Peak memory | 274208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3970289001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl _same_csr_outstanding.3970289001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3775003343 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 14519600 ps |
| CPU time | 21.38 seconds |
| Started | Sep 09 05:31:53 PM UTC 24 |
| Finished | Sep 09 05:32:16 PM UTC 24 |
| Peak memory | 261792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377 5003343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sh adow_reg_errors.3775003343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1830048990 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 13926500 ps |
| CPU time | 22.77 seconds |
| Started | Sep 09 05:31:53 PM UTC 24 |
| Finished | Sep 09 05:32:17 PM UTC 24 |
| Peak memory | 261792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1830048990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.f lash_ctrl_shadow_reg_errors_with_csr_rw.1830048990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1359126749 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 223307200 ps |
| CPU time | 23.11 seconds |
| Started | Sep 09 05:31:52 PM UTC 24 |
| Finished | Sep 09 05:32:16 PM UTC 24 |
| Peak memory | 274156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359126749 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.1359126749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2044961451 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1598775000 ps |
| CPU time | 490.79 seconds |
| Started | Sep 09 05:31:52 PM UTC 24 |
| Finished | Sep 09 05:40:09 PM UTC 24 |
| Peak memory | 274208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044961451 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.2044961451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1320721389 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 195803100 ps |
| CPU time | 20.33 seconds |
| Started | Sep 09 05:32:02 PM UTC 24 |
| Finished | Sep 09 05:32:24 PM UTC 24 |
| Peak memory | 273984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1320721389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1320721389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.260454705 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 105223300 ps |
| CPU time | 26.53 seconds |
| Started | Sep 09 05:32:01 PM UTC 24 |
| Finished | Sep 09 05:32:29 PM UTC 24 |
| Peak memory | 274132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260454705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.260454705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3284613962 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 29723500 ps |
| CPU time | 17.42 seconds |
| Started | Sep 09 05:32:00 PM UTC 24 |
| Finished | Sep 09 05:32:19 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284613962 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.3284613962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4075302487 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 217114000 ps |
| CPU time | 26.55 seconds |
| Started | Sep 09 05:32:02 PM UTC 24 |
| Finished | Sep 09 05:32:30 PM UTC 24 |
| Peak memory | 271644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4075302487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl _same_csr_outstanding.4075302487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1688576061 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 15780100 ps |
| CPU time | 20.99 seconds |
| Started | Sep 09 05:31:59 PM UTC 24 |
| Finished | Sep 09 05:32:21 PM UTC 24 |
| Peak memory | 261792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168 8576061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh adow_reg_errors.1688576061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2020102700 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 104604400 ps |
| CPU time | 17.68 seconds |
| Started | Sep 09 05:32:00 PM UTC 24 |
| Finished | Sep 09 05:32:19 PM UTC 24 |
| Peak memory | 261840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2020102700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.f lash_ctrl_shadow_reg_errors_with_csr_rw.2020102700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2239360963 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 67698500 ps |
| CPU time | 28.08 seconds |
| Started | Sep 09 05:31:58 PM UTC 24 |
| Finished | Sep 09 05:32:27 PM UTC 24 |
| Peak memory | 274160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239360963 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.2239360963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3354587161 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 660046800 ps |
| CPU time | 607.35 seconds |
| Started | Sep 09 05:31:59 PM UTC 24 |
| Finished | Sep 09 05:42:13 PM UTC 24 |
| Peak memory | 274280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354587161 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.3354587161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.876632969 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 160955700 ps |
| CPU time | 21.49 seconds |
| Started | Sep 09 05:32:07 PM UTC 24 |
| Finished | Sep 09 05:32:30 PM UTC 24 |
| Peak memory | 290652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=876632969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.876632969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1377455028 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 145651900 ps |
| CPU time | 21.37 seconds |
| Started | Sep 09 05:32:06 PM UTC 24 |
| Finished | Sep 09 05:32:29 PM UTC 24 |
| Peak memory | 274136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377455028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.1377455028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1385177357 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 334201500 ps |
| CPU time | 26.26 seconds |
| Started | Sep 09 05:32:07 PM UTC 24 |
| Finished | Sep 09 05:32:35 PM UTC 24 |
| Peak memory | 274140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1385177357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl _same_csr_outstanding.1385177357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3836170336 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 14537400 ps |
| CPU time | 19.51 seconds |
| Started | Sep 09 05:32:05 PM UTC 24 |
| Finished | Sep 09 05:32:26 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383 6170336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sh adow_reg_errors.3836170336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3367444625 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 12355900 ps |
| CPU time | 26.59 seconds |
| Started | Sep 09 05:32:05 PM UTC 24 |
| Finished | Sep 09 05:32:33 PM UTC 24 |
| Peak memory | 261920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3367444625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.f lash_ctrl_shadow_reg_errors_with_csr_rw.3367444625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1100528691 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 64472800 ps |
| CPU time | 25.85 seconds |
| Started | Sep 09 05:32:03 PM UTC 24 |
| Finished | Sep 09 05:32:31 PM UTC 24 |
| Peak memory | 274152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100528691 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.1100528691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3792650064 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 239674400 ps |
| CPU time | 24.78 seconds |
| Started | Sep 09 05:32:12 PM UTC 24 |
| Finished | Sep 09 05:32:38 PM UTC 24 |
| Peak memory | 288164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3792650064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3792650064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.782150716 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 109320100 ps |
| CPU time | 22.29 seconds |
| Started | Sep 09 05:32:10 PM UTC 24 |
| Finished | Sep 09 05:32:33 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782150716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.782150716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1576129146 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 16482800 ps |
| CPU time | 21.18 seconds |
| Started | Sep 09 05:32:10 PM UTC 24 |
| Finished | Sep 09 05:32:32 PM UTC 24 |
| Peak memory | 271984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576129146 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.1576129146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2460814603 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 206536400 ps |
| CPU time | 48.19 seconds |
| Started | Sep 09 05:32:12 PM UTC 24 |
| Finished | Sep 09 05:33:01 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2460814603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl _same_csr_outstanding.2460814603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4165171287 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 17055000 ps |
| CPU time | 19.89 seconds |
| Started | Sep 09 05:32:08 PM UTC 24 |
| Finished | Sep 09 05:32:30 PM UTC 24 |
| Peak memory | 261792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416 5171287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sh adow_reg_errors.4165171287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2817881557 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 24541500 ps |
| CPU time | 21.61 seconds |
| Started | Sep 09 05:32:10 PM UTC 24 |
| Finished | Sep 09 05:32:32 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2817881557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.f lash_ctrl_shadow_reg_errors_with_csr_rw.2817881557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.81193823 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 472269200 ps |
| CPU time | 549.36 seconds |
| Started | Sep 09 05:32:08 PM UTC 24 |
| Finished | Sep 09 05:41:24 PM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81193823 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.81193823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3895434091 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 417838100 ps |
| CPU time | 26.24 seconds |
| Started | Sep 09 05:32:16 PM UTC 24 |
| Finished | Sep 09 05:32:44 PM UTC 24 |
| Peak memory | 284640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3895434091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.3895434091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1152888181 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 57612200 ps |
| CPU time | 25.76 seconds |
| Started | Sep 09 05:32:14 PM UTC 24 |
| Finished | Sep 09 05:32:41 PM UTC 24 |
| Peak memory | 274140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152888181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.1152888181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1772966868 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 77892800 ps |
| CPU time | 21.93 seconds |
| Started | Sep 09 05:32:13 PM UTC 24 |
| Finished | Sep 09 05:32:36 PM UTC 24 |
| Peak memory | 271984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772966868 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.1772966868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2153891784 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 344823100 ps |
| CPU time | 20.86 seconds |
| Started | Sep 09 05:32:15 PM UTC 24 |
| Finished | Sep 09 05:32:37 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2153891784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl _same_csr_outstanding.2153891784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2875074380 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 33482300 ps |
| CPU time | 28.31 seconds |
| Started | Sep 09 05:32:12 PM UTC 24 |
| Finished | Sep 09 05:32:41 PM UTC 24 |
| Peak memory | 261856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287 5074380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sh adow_reg_errors.2875074380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2440556494 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 142706300 ps |
| CPU time | 23.18 seconds |
| Started | Sep 09 05:32:12 PM UTC 24 |
| Finished | Sep 09 05:32:36 PM UTC 24 |
| Peak memory | 261792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2440556494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.f lash_ctrl_shadow_reg_errors_with_csr_rw.2440556494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.500951300 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 110472100 ps |
| CPU time | 23.05 seconds |
| Started | Sep 09 05:32:12 PM UTC 24 |
| Finished | Sep 09 05:32:36 PM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500951300 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.500951300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3787215812 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4166436200 ps |
| CPU time | 718.31 seconds |
| Started | Sep 09 05:32:12 PM UTC 24 |
| Finished | Sep 09 05:44:18 PM UTC 24 |
| Peak memory | 273836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787215812 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.3787215812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.179570331 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 185400200 ps |
| CPU time | 23.99 seconds |
| Started | Sep 09 05:32:20 PM UTC 24 |
| Finished | Sep 09 05:32:45 PM UTC 24 |
| Peak memory | 284508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=179570331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.179570331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2517111346 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 70783700 ps |
| CPU time | 24.33 seconds |
| Started | Sep 09 05:32:19 PM UTC 24 |
| Finished | Sep 09 05:32:44 PM UTC 24 |
| Peak memory | 272092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517111346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.2517111346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1493088256 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 28581900 ps |
| CPU time | 21.1 seconds |
| Started | Sep 09 05:32:18 PM UTC 24 |
| Finished | Sep 09 05:32:40 PM UTC 24 |
| Peak memory | 271984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493088256 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.1493088256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.148621790 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 37174400 ps |
| CPU time | 23.08 seconds |
| Started | Sep 09 05:32:20 PM UTC 24 |
| Finished | Sep 09 05:32:44 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 148621790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ same_csr_outstanding.148621790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.110655735 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 13081000 ps |
| CPU time | 19.05 seconds |
| Started | Sep 09 05:32:18 PM UTC 24 |
| Finished | Sep 09 05:32:38 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110 655735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sha dow_reg_errors.110655735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3700140187 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 42571000 ps |
| CPU time | 25.6 seconds |
| Started | Sep 09 05:32:18 PM UTC 24 |
| Finished | Sep 09 05:32:44 PM UTC 24 |
| Peak memory | 261856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3700140187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.f lash_ctrl_shadow_reg_errors_with_csr_rw.3700140187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3048465211 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 361836600 ps |
| CPU time | 21.57 seconds |
| Started | Sep 09 05:32:16 PM UTC 24 |
| Finished | Sep 09 05:32:39 PM UTC 24 |
| Peak memory | 274288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048465211 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.3048465211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.637075127 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 101086500 ps |
| CPU time | 24.77 seconds |
| Started | Sep 09 05:32:30 PM UTC 24 |
| Finished | Sep 09 05:32:56 PM UTC 24 |
| Peak memory | 284500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=637075127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.637075127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1565431472 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 95523200 ps |
| CPU time | 22.15 seconds |
| Started | Sep 09 05:32:28 PM UTC 24 |
| Finished | Sep 09 05:32:51 PM UTC 24 |
| Peak memory | 272092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565431472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.1565431472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.2740461148 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 42355500 ps |
| CPU time | 22.94 seconds |
| Started | Sep 09 05:32:26 PM UTC 24 |
| Finished | Sep 09 05:32:50 PM UTC 24 |
| Peak memory | 272048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740461148 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.2740461148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1631714421 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 78391600 ps |
| CPU time | 26.46 seconds |
| Started | Sep 09 05:32:28 PM UTC 24 |
| Finished | Sep 09 05:32:56 PM UTC 24 |
| Peak memory | 272224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1631714421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl _same_csr_outstanding.1631714421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2292540125 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 43173300 ps |
| CPU time | 16.76 seconds |
| Started | Sep 09 05:32:22 PM UTC 24 |
| Finished | Sep 09 05:32:40 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229 2540125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh adow_reg_errors.2292540125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2982636488 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 13579800 ps |
| CPU time | 16.97 seconds |
| Started | Sep 09 05:32:26 PM UTC 24 |
| Finished | Sep 09 05:32:44 PM UTC 24 |
| Peak memory | 261856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2982636488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.f lash_ctrl_shadow_reg_errors_with_csr_rw.2982636488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2926029189 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 132742200 ps |
| CPU time | 24.48 seconds |
| Started | Sep 09 05:32:20 PM UTC 24 |
| Finished | Sep 09 05:32:46 PM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926029189 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.2926029189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.525827642 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 728597500 ps |
| CPU time | 543.3 seconds |
| Started | Sep 09 05:32:21 PM UTC 24 |
| Finished | Sep 09 05:41:30 PM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525827642 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.525827642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.32172055 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 25092463800 ps |
| CPU time | 78.09 seconds |
| Started | Sep 09 05:30:23 PM UTC 24 |
| Finished | Sep 09 05:31:43 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32172055 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.32172055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2147010019 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 16340100400 ps |
| CPU time | 100.64 seconds |
| Started | Sep 09 05:30:22 PM UTC 24 |
| Finished | Sep 09 05:32:05 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147010019 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.2147010019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1144189584 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 67452000 ps |
| CPU time | 56.54 seconds |
| Started | Sep 09 05:30:22 PM UTC 24 |
| Finished | Sep 09 05:31:20 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144189584 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.1144189584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4077841063 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 182202800 ps |
| CPU time | 23.65 seconds |
| Started | Sep 09 05:30:24 PM UTC 24 |
| Finished | Sep 09 05:30:49 PM UTC 24 |
| Peak memory | 284636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4077841063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.4077841063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1094094184 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 57768300 ps |
| CPU time | 27.02 seconds |
| Started | Sep 09 05:30:22 PM UTC 24 |
| Finished | Sep 09 05:30:50 PM UTC 24 |
| Peak memory | 272156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094094184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.1094094184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.1554701921 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 25771800 ps |
| CPU time | 16.09 seconds |
| Started | Sep 09 05:30:15 PM UTC 24 |
| Finished | Sep 09 05:30:33 PM UTC 24 |
| Peak memory | 272116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554701921 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.1554701921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3629713433 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 15125400 ps |
| CPU time | 25.8 seconds |
| Started | Sep 09 05:30:15 PM UTC 24 |
| Finished | Sep 09 05:30:43 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629713433 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.3629713433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1303751097 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 241691900 ps |
| CPU time | 50.29 seconds |
| Started | Sep 09 05:30:23 PM UTC 24 |
| Finished | Sep 09 05:31:15 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1303751097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ same_csr_outstanding.1303751097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4132266172 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 75288700 ps |
| CPU time | 23.85 seconds |
| Started | Sep 09 05:30:15 PM UTC 24 |
| Finished | Sep 09 05:30:41 PM UTC 24 |
| Peak memory | 261800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413 2266172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha dow_reg_errors.4132266172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2307416966 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 15233400 ps |
| CPU time | 20.11 seconds |
| Started | Sep 09 05:30:15 PM UTC 24 |
| Finished | Sep 09 05:30:37 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2307416966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2307416966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2381453683 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 226200900 ps |
| CPU time | 32.26 seconds |
| Started | Sep 09 05:30:14 PM UTC 24 |
| Finished | Sep 09 05:30:48 PM UTC 24 |
| Peak memory | 274164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381453683 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2381453683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2628875100 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 9401847000 ps |
| CPU time | 1141.57 seconds |
| Started | Sep 09 05:30:15 PM UTC 24 |
| Finished | Sep 09 05:49:30 PM UTC 24 |
| Peak memory | 276348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628875100 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.2628875100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1709798540 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 73696600 ps |
| CPU time | 17.53 seconds |
| Started | Sep 09 05:32:30 PM UTC 24 |
| Finished | Sep 09 05:32:49 PM UTC 24 |
| Peak memory | 271988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709798540 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.1709798540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1623960270 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 45086100 ps |
| CPU time | 20.95 seconds |
| Started | Sep 09 05:32:30 PM UTC 24 |
| Finished | Sep 09 05:32:52 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623960270 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.1623960270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.2576642467 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 45872400 ps |
| CPU time | 17.68 seconds |
| Started | Sep 09 05:32:30 PM UTC 24 |
| Finished | Sep 09 05:32:49 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576642467 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.2576642467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2643963984 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 55588200 ps |
| CPU time | 22.57 seconds |
| Started | Sep 09 05:32:32 PM UTC 24 |
| Finished | Sep 09 05:32:56 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643963984 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.2643963984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.1264528824 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 54419100 ps |
| CPU time | 18.73 seconds |
| Started | Sep 09 05:32:32 PM UTC 24 |
| Finished | Sep 09 05:32:52 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264528824 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.1264528824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.2160135327 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 35850400 ps |
| CPU time | 17.81 seconds |
| Started | Sep 09 05:32:32 PM UTC 24 |
| Finished | Sep 09 05:32:51 PM UTC 24 |
| Peak memory | 272112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160135327 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.2160135327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.37753002 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 15823700 ps |
| CPU time | 18.51 seconds |
| Started | Sep 09 05:32:34 PM UTC 24 |
| Finished | Sep 09 05:32:54 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37753002 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.37753002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.1920435258 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 17009300 ps |
| CPU time | 18.42 seconds |
| Started | Sep 09 05:32:34 PM UTC 24 |
| Finished | Sep 09 05:32:54 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920435258 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.1920435258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.3095606709 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 122311900 ps |
| CPU time | 17.85 seconds |
| Started | Sep 09 05:32:34 PM UTC 24 |
| Finished | Sep 09 05:32:53 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095606709 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.3095606709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.996812166 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 221542300 ps |
| CPU time | 22.06 seconds |
| Started | Sep 09 05:32:34 PM UTC 24 |
| Finished | Sep 09 05:32:58 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996812166 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.996812166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2855094441 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 5176474100 ps |
| CPU time | 61.17 seconds |
| Started | Sep 09 05:30:38 PM UTC 24 |
| Finished | Sep 09 05:31:41 PM UTC 24 |
| Peak memory | 272028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855094441 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.2855094441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.171681327 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 5754304100 ps |
| CPU time | 86.63 seconds |
| Started | Sep 09 05:30:38 PM UTC 24 |
| Finished | Sep 09 05:32:07 PM UTC 24 |
| Peak memory | 272032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171681327 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.171681327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2391256190 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 26119900 ps |
| CPU time | 71.54 seconds |
| Started | Sep 09 05:30:36 PM UTC 24 |
| Finished | Sep 09 05:31:49 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391256190 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.2391256190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1212236792 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 115170800 ps |
| CPU time | 21.63 seconds |
| Started | Sep 09 05:30:39 PM UTC 24 |
| Finished | Sep 09 05:31:02 PM UTC 24 |
| Peak memory | 284508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1212236792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1212236792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2817523686 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 24571800 ps |
| CPU time | 21.12 seconds |
| Started | Sep 09 05:30:38 PM UTC 24 |
| Finished | Sep 09 05:31:00 PM UTC 24 |
| Peak memory | 272156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817523686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.2817523686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2070942315 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 54759800 ps |
| CPU time | 17.06 seconds |
| Started | Sep 09 05:30:32 PM UTC 24 |
| Finished | Sep 09 05:30:50 PM UTC 24 |
| Peak memory | 271984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070942315 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2070942315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.534475474 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 28405900 ps |
| CPU time | 27.46 seconds |
| Started | Sep 09 05:30:36 PM UTC 24 |
| Finished | Sep 09 05:31:05 PM UTC 24 |
| Peak memory | 274136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534475474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.534475474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1332096789 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 16863000 ps |
| CPU time | 16.28 seconds |
| Started | Sep 09 05:30:34 PM UTC 24 |
| Finished | Sep 09 05:30:51 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332096789 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.1332096789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4110605019 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 92055400 ps |
| CPU time | 30.62 seconds |
| Started | Sep 09 05:30:39 PM UTC 24 |
| Finished | Sep 09 05:31:11 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4110605019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ same_csr_outstanding.4110605019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3972067917 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 43779300 ps |
| CPU time | 16.46 seconds |
| Started | Sep 09 05:30:28 PM UTC 24 |
| Finished | Sep 09 05:30:46 PM UTC 24 |
| Peak memory | 261864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397 2067917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sha dow_reg_errors.3972067917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2395400691 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 23885800 ps |
| CPU time | 21.51 seconds |
| Started | Sep 09 05:30:31 PM UTC 24 |
| Finished | Sep 09 05:30:55 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2395400691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2395400691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3777333796 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 708330500 ps |
| CPU time | 1241.69 seconds |
| Started | Sep 09 05:30:27 PM UTC 24 |
| Finished | Sep 09 05:51:23 PM UTC 24 |
| Peak memory | 276284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777333796 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.3777333796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1587752824 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 15679500 ps |
| CPU time | 21.06 seconds |
| Started | Sep 09 05:32:37 PM UTC 24 |
| Finished | Sep 09 05:32:59 PM UTC 24 |
| Peak memory | 272048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587752824 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.1587752824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2571043532 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 18869200 ps |
| CPU time | 19.78 seconds |
| Started | Sep 09 05:32:37 PM UTC 24 |
| Finished | Sep 09 05:32:58 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571043532 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.2571043532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.687371573 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 41823000 ps |
| CPU time | 18.43 seconds |
| Started | Sep 09 05:32:37 PM UTC 24 |
| Finished | Sep 09 05:32:56 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687371573 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.687371573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.1915870717 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 26288600 ps |
| CPU time | 18.85 seconds |
| Started | Sep 09 05:32:37 PM UTC 24 |
| Finished | Sep 09 05:32:57 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915870717 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.1915870717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2734308269 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 27860300 ps |
| CPU time | 19 seconds |
| Started | Sep 09 05:32:39 PM UTC 24 |
| Finished | Sep 09 05:32:59 PM UTC 24 |
| Peak memory | 271828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734308269 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.2734308269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2905720762 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 37428600 ps |
| CPU time | 19.26 seconds |
| Started | Sep 09 05:32:39 PM UTC 24 |
| Finished | Sep 09 05:33:00 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905720762 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.2905720762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.957837461 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 43601000 ps |
| CPU time | 20.55 seconds |
| Started | Sep 09 05:32:39 PM UTC 24 |
| Finished | Sep 09 05:33:01 PM UTC 24 |
| Peak memory | 271828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957837461 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.957837461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.2987715070 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 48989800 ps |
| CPU time | 20.35 seconds |
| Started | Sep 09 05:32:41 PM UTC 24 |
| Finished | Sep 09 05:33:03 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987715070 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.2987715070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.1752921189 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 20204400 ps |
| CPU time | 17.29 seconds |
| Started | Sep 09 05:32:41 PM UTC 24 |
| Finished | Sep 09 05:33:00 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752921189 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.1752921189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.1983998195 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 46828900 ps |
| CPU time | 23.14 seconds |
| Started | Sep 09 05:32:41 PM UTC 24 |
| Finished | Sep 09 05:33:06 PM UTC 24 |
| Peak memory | 271984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983998195 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.1983998195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3360854568 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 4969467400 ps |
| CPU time | 68.33 seconds |
| Started | Sep 09 05:30:51 PM UTC 24 |
| Finished | Sep 09 05:32:01 PM UTC 24 |
| Peak memory | 272228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360854568 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.3360854568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1688017482 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 19924093200 ps |
| CPU time | 58.01 seconds |
| Started | Sep 09 05:30:51 PM UTC 24 |
| Finished | Sep 09 05:31:51 PM UTC 24 |
| Peak memory | 272092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688017482 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.1688017482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1763495433 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 43420400 ps |
| CPU time | 61.12 seconds |
| Started | Sep 09 05:30:50 PM UTC 24 |
| Finished | Sep 09 05:31:53 PM UTC 24 |
| Peak memory | 272100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763495433 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.1763495433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3953646449 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 48838300 ps |
| CPU time | 28.84 seconds |
| Started | Sep 09 05:30:52 PM UTC 24 |
| Finished | Sep 09 05:31:23 PM UTC 24 |
| Peak memory | 288604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3953646449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3953646449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2204462477 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 29755600 ps |
| CPU time | 30.65 seconds |
| Started | Sep 09 05:30:51 PM UTC 24 |
| Finished | Sep 09 05:31:23 PM UTC 24 |
| Peak memory | 274140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204462477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.2204462477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.221794680 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 18576700 ps |
| CPU time | 17.52 seconds |
| Started | Sep 09 05:30:44 PM UTC 24 |
| Finished | Sep 09 05:31:02 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221794680 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.221794680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1915518937 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 16338000 ps |
| CPU time | 17.19 seconds |
| Started | Sep 09 05:30:49 PM UTC 24 |
| Finished | Sep 09 05:31:07 PM UTC 24 |
| Peak memory | 274140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915518937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.1915518937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3552954418 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 29243100 ps |
| CPU time | 26.34 seconds |
| Started | Sep 09 05:30:47 PM UTC 24 |
| Finished | Sep 09 05:31:14 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552954418 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.3552954418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2793307766 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 166620300 ps |
| CPU time | 33.55 seconds |
| Started | Sep 09 05:30:52 PM UTC 24 |
| Finished | Sep 09 05:31:27 PM UTC 24 |
| Peak memory | 272096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2793307766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ same_csr_outstanding.2793307766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3423303255 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 25091700 ps |
| CPU time | 18.39 seconds |
| Started | Sep 09 05:30:43 PM UTC 24 |
| Finished | Sep 09 05:31:02 PM UTC 24 |
| Peak memory | 261796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342 3303255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sha dow_reg_errors.3423303255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3629020459 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 11728000 ps |
| CPU time | 18.45 seconds |
| Started | Sep 09 05:30:43 PM UTC 24 |
| Finished | Sep 09 05:31:02 PM UTC 24 |
| Peak memory | 261852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3629020459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3629020459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3896772948 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 692596300 ps |
| CPU time | 1322.37 seconds |
| Started | Sep 09 05:30:42 PM UTC 24 |
| Finished | Sep 09 05:53:00 PM UTC 24 |
| Peak memory | 276484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896772948 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.3896772948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.647585063 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 165818000 ps |
| CPU time | 18.85 seconds |
| Started | Sep 09 05:32:41 PM UTC 24 |
| Finished | Sep 09 05:33:01 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647585063 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.647585063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2945730601 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 37497900 ps |
| CPU time | 19.6 seconds |
| Started | Sep 09 05:32:44 PM UTC 24 |
| Finished | Sep 09 05:33:04 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945730601 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.2945730601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.2075093435 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 35761900 ps |
| CPU time | 22.55 seconds |
| Started | Sep 09 05:32:44 PM UTC 24 |
| Finished | Sep 09 05:33:07 PM UTC 24 |
| Peak memory | 271984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075093435 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.2075093435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.3500533748 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 18953800 ps |
| CPU time | 20 seconds |
| Started | Sep 09 05:32:44 PM UTC 24 |
| Finished | Sep 09 05:33:05 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500533748 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.3500533748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.54009979 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 47732800 ps |
| CPU time | 17.71 seconds |
| Started | Sep 09 05:32:47 PM UTC 24 |
| Finished | Sep 09 05:33:06 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54009979 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.54009979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.3949538627 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 14834100 ps |
| CPU time | 19.73 seconds |
| Started | Sep 09 05:32:47 PM UTC 24 |
| Finished | Sep 09 05:33:08 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949538627 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.3949538627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1052090107 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 69387800 ps |
| CPU time | 20.42 seconds |
| Started | Sep 09 05:32:47 PM UTC 24 |
| Finished | Sep 09 05:33:09 PM UTC 24 |
| Peak memory | 272052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052090107 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.1052090107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2646249567 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 44355700 ps |
| CPU time | 23.63 seconds |
| Started | Sep 09 05:32:47 PM UTC 24 |
| Finished | Sep 09 05:33:12 PM UTC 24 |
| Peak memory | 271984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646249567 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.2646249567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.1896923140 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 54257000 ps |
| CPU time | 17.39 seconds |
| Started | Sep 09 05:32:47 PM UTC 24 |
| Finished | Sep 09 05:33:06 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896923140 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.1896923140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.759927686 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 18258500 ps |
| CPU time | 18.48 seconds |
| Started | Sep 09 05:32:47 PM UTC 24 |
| Finished | Sep 09 05:33:07 PM UTC 24 |
| Peak memory | 271976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759927686 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.759927686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.679025548 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 32630800 ps |
| CPU time | 18.33 seconds |
| Started | Sep 09 05:31:03 PM UTC 24 |
| Finished | Sep 09 05:31:23 PM UTC 24 |
| Peak memory | 284500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=679025548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.679025548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.107407463 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 39667900 ps |
| CPU time | 21.39 seconds |
| Started | Sep 09 05:31:03 PM UTC 24 |
| Finished | Sep 09 05:31:26 PM UTC 24 |
| Peak memory | 274140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107407463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.107407463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.51551912 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 14251100 ps |
| CPU time | 17.1 seconds |
| Started | Sep 09 05:31:03 PM UTC 24 |
| Finished | Sep 09 05:31:21 PM UTC 24 |
| Peak memory | 271960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51551912 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.51551912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2232079820 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 162851500 ps |
| CPU time | 24.38 seconds |
| Started | Sep 09 05:31:03 PM UTC 24 |
| Finished | Sep 09 05:31:29 PM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2232079820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ same_csr_outstanding.2232079820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4253435587 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 43200700 ps |
| CPU time | 20.21 seconds |
| Started | Sep 09 05:30:56 PM UTC 24 |
| Finished | Sep 09 05:31:17 PM UTC 24 |
| Peak memory | 261864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425 3435587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha dow_reg_errors.4253435587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.203753756 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 42817500 ps |
| CPU time | 25.21 seconds |
| Started | Sep 09 05:31:01 PM UTC 24 |
| Finished | Sep 09 05:31:27 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=203753756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_shadow_reg_errors_with_csr_rw.203753756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1404179010 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 132573600 ps |
| CPU time | 22.03 seconds |
| Started | Sep 09 05:30:52 PM UTC 24 |
| Finished | Sep 09 05:31:16 PM UTC 24 |
| Peak memory | 274292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404179010 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1404179010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2380994710 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 439518500 ps |
| CPU time | 739.6 seconds |
| Started | Sep 09 05:30:54 PM UTC 24 |
| Finished | Sep 09 05:43:22 PM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380994710 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.2380994710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.457092272 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 114076400 ps |
| CPU time | 18.97 seconds |
| Started | Sep 09 05:31:08 PM UTC 24 |
| Finished | Sep 09 05:31:28 PM UTC 24 |
| Peak memory | 272088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457092272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.457092272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.1230069661 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 15261800 ps |
| CPU time | 16.9 seconds |
| Started | Sep 09 05:31:08 PM UTC 24 |
| Finished | Sep 09 05:31:26 PM UTC 24 |
| Peak memory | 271696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230069661 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1230069661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3307507537 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1122144800 ps |
| CPU time | 42.44 seconds |
| Started | Sep 09 05:31:10 PM UTC 24 |
| Finished | Sep 09 05:31:54 PM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3307507537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ same_csr_outstanding.3307507537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3313981238 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 40843900 ps |
| CPU time | 24.58 seconds |
| Started | Sep 09 05:31:05 PM UTC 24 |
| Finished | Sep 09 05:31:31 PM UTC 24 |
| Peak memory | 261800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331 3981238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sha dow_reg_errors.3313981238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2444969514 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 16385700 ps |
| CPU time | 16.66 seconds |
| Started | Sep 09 05:31:08 PM UTC 24 |
| Finished | Sep 09 05:31:26 PM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2444969514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2444969514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2680993726 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 233810500 ps |
| CPU time | 31.25 seconds |
| Started | Sep 09 05:31:03 PM UTC 24 |
| Finished | Sep 09 05:31:36 PM UTC 24 |
| Peak memory | 274168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680993726 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2680993726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3033899840 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 65922300 ps |
| CPU time | 22.78 seconds |
| Started | Sep 09 05:31:18 PM UTC 24 |
| Finished | Sep 09 05:31:42 PM UTC 24 |
| Peak memory | 284572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3033899840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3033899840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1220473187 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 69737200 ps |
| CPU time | 19.31 seconds |
| Started | Sep 09 05:31:17 PM UTC 24 |
| Finished | Sep 09 05:31:37 PM UTC 24 |
| Peak memory | 272156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220473187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.1220473187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2777609693 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 138060500 ps |
| CPU time | 19.46 seconds |
| Started | Sep 09 05:31:18 PM UTC 24 |
| Finished | Sep 09 05:31:39 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2777609693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ same_csr_outstanding.2777609693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1296613144 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 68669100 ps |
| CPU time | 21.48 seconds |
| Started | Sep 09 05:31:16 PM UTC 24 |
| Finished | Sep 09 05:31:38 PM UTC 24 |
| Peak memory | 261864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129 6613144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sha dow_reg_errors.1296613144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.879424189 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 11297000 ps |
| CPU time | 28.08 seconds |
| Started | Sep 09 05:31:16 PM UTC 24 |
| Finished | Sep 09 05:31:45 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=879424189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_shadow_reg_errors_with_csr_rw.879424189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.885285102 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 78939700 ps |
| CPU time | 23.67 seconds |
| Started | Sep 09 05:31:12 PM UTC 24 |
| Finished | Sep 09 05:31:37 PM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885285102 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.885285102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2981638514 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 697336800 ps |
| CPU time | 1285.17 seconds |
| Started | Sep 09 05:31:13 PM UTC 24 |
| Finished | Sep 09 05:52:53 PM UTC 24 |
| Peak memory | 276284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981638514 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.2981638514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2071597295 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 170497600 ps |
| CPU time | 22.44 seconds |
| Started | Sep 09 05:31:27 PM UTC 24 |
| Finished | Sep 09 05:31:51 PM UTC 24 |
| Peak memory | 274264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2071597295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2071597295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1712534942 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 37301000 ps |
| CPU time | 19.95 seconds |
| Started | Sep 09 05:31:24 PM UTC 24 |
| Finished | Sep 09 05:31:45 PM UTC 24 |
| Peak memory | 274136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712534942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.1712534942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.2312229664 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 91210300 ps |
| CPU time | 28.1 seconds |
| Started | Sep 09 05:31:24 PM UTC 24 |
| Finished | Sep 09 05:31:53 PM UTC 24 |
| Peak memory | 271980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312229664 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.2312229664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1439615024 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 67643700 ps |
| CPU time | 29.81 seconds |
| Started | Sep 09 05:31:27 PM UTC 24 |
| Finished | Sep 09 05:31:58 PM UTC 24 |
| Peak memory | 271904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1439615024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ same_csr_outstanding.1439615024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1595398716 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 38143900 ps |
| CPU time | 23.46 seconds |
| Started | Sep 09 05:31:23 PM UTC 24 |
| Finished | Sep 09 05:31:47 PM UTC 24 |
| Peak memory | 261796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159 5398716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sha dow_reg_errors.1595398716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1300180977 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 34198700 ps |
| CPU time | 26.18 seconds |
| Started | Sep 09 05:31:24 PM UTC 24 |
| Finished | Sep 09 05:31:51 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1300180977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1300180977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.930496597 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 121359200 ps |
| CPU time | 28.24 seconds |
| Started | Sep 09 05:31:20 PM UTC 24 |
| Finished | Sep 09 05:31:50 PM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930496597 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.930496597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.429975817 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2800353800 ps |
| CPU time | 1075.27 seconds |
| Started | Sep 09 05:31:22 PM UTC 24 |
| Finished | Sep 09 05:49:29 PM UTC 24 |
| Peak memory | 274312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429975817 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.429975817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.783079651 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 39380400 ps |
| CPU time | 23.54 seconds |
| Started | Sep 09 05:31:32 PM UTC 24 |
| Finished | Sep 09 05:31:56 PM UTC 24 |
| Peak memory | 284568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=783079651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.783079651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4215715390 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 107824900 ps |
| CPU time | 28.51 seconds |
| Started | Sep 09 05:31:30 PM UTC 24 |
| Finished | Sep 09 05:31:59 PM UTC 24 |
| Peak memory | 274140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215715390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.4215715390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2320424793 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 35297700 ps |
| CPU time | 19.89 seconds |
| Started | Sep 09 05:31:29 PM UTC 24 |
| Finished | Sep 09 05:31:51 PM UTC 24 |
| Peak memory | 271984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320424793 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2320424793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2196968061 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 39796500 ps |
| CPU time | 21.5 seconds |
| Started | Sep 09 05:31:30 PM UTC 24 |
| Finished | Sep 09 05:31:53 PM UTC 24 |
| Peak memory | 274144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2196968061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ same_csr_outstanding.2196968061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2814974810 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 83163600 ps |
| CPU time | 23.3 seconds |
| Started | Sep 09 05:31:29 PM UTC 24 |
| Finished | Sep 09 05:31:54 PM UTC 24 |
| Peak memory | 261796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281 4974810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha dow_reg_errors.2814974810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2952766079 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 34384700 ps |
| CPU time | 19.85 seconds |
| Started | Sep 09 05:31:29 PM UTC 24 |
| Finished | Sep 09 05:31:51 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2952766079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fl ash_ctrl_shadow_reg_errors_with_csr_rw.2952766079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2648195023 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 161518600 ps |
| CPU time | 21.05 seconds |
| Started | Sep 09 05:31:27 PM UTC 24 |
| Finished | Sep 09 05:31:49 PM UTC 24 |
| Peak memory | 274164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648195023 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.2648195023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.3985234731 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 16291800 ps |
| CPU time | 25.17 seconds |
| Started | Sep 09 05:34:16 PM UTC 24 |
| Finished | Sep 09 05:34:42 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985234731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3985234731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3379159762 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2700729200 ps |
| CPU time | 254.67 seconds |
| Started | Sep 09 05:33:09 PM UTC 24 |
| Finished | Sep 09 05:37:27 PM UTC 24 |
| Peak memory | 289740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3379159762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_derr_detect.3379159762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.4209868870 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 27738300 ps |
| CPU time | 48.86 seconds |
| Started | Sep 09 05:35:01 PM UTC 24 |
| Finished | Sep 09 05:35:51 PM UTC 24 |
| Peak memory | 287488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420986887 0 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho st_addr_infection.4209868870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.1764126058 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1297070659400 ps |
| CPU time | 1939 seconds |
| Started | Sep 09 05:32:55 PM UTC 24 |
| Finished | Sep 09 06:05:35 PM UTC 24 |
| Peak memory | 277860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764126058 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.1764126058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.3969367004 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 39602400 ps |
| CPU time | 79.96 seconds |
| Started | Sep 09 05:32:50 PM UTC 24 |
| Finished | Sep 09 05:34:11 PM UTC 24 |
| Peak memory | 275016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969367004 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.3969367004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.529507818 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 85361786500 ps |
| CPU time | 1635.13 seconds |
| Started | Sep 09 05:32:54 PM UTC 24 |
| Finished | Sep 09 06:00:26 PM UTC 24 |
| Peak memory | 273428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529507818 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.529507818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.1805674723 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 40127253400 ps |
| CPU time | 944.21 seconds |
| Started | Sep 09 05:32:55 PM UTC 24 |
| Finished | Sep 09 05:48:50 PM UTC 24 |
| Peak memory | 274752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805674723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.1805674723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.2380296237 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3799013200 ps |
| CPU time | 426.45 seconds |
| Started | Sep 09 05:33:11 PM UTC 24 |
| Finished | Sep 09 05:40:22 PM UTC 24 |
| Peak memory | 338632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2380296237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integr ity.2380296237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3284738176 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 735164000 ps |
| CPU time | 121.17 seconds |
| Started | Sep 09 05:33:12 PM UTC 24 |
| Finished | Sep 09 05:35:15 PM UTC 24 |
| Peak memory | 306096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284738176 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.3284738176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.281289929 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 53272834000 ps |
| CPU time | 250.45 seconds |
| Started | Sep 09 05:33:22 PM UTC 24 |
| Finished | Sep 09 05:37:36 PM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281289929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.281289929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.3327513843 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 46510200 ps |
| CPU time | 18.01 seconds |
| Started | Sep 09 05:34:48 PM UTC 24 |
| Finished | Sep 09 05:35:08 PM UTC 24 |
| Peak memory | 271332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3327513843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_lcmgr_intg.3327513843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2540871239 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 75368100 ps |
| CPU time | 155.99 seconds |
| Started | Sep 09 05:32:55 PM UTC 24 |
| Finished | Sep 09 05:35:34 PM UTC 24 |
| Peak memory | 270780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540871239 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.2540871239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.625269978 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2821168600 ps |
| CPU time | 388.19 seconds |
| Started | Sep 09 05:32:52 PM UTC 24 |
| Finished | Sep 09 05:39:25 PM UTC 24 |
| Peak memory | 274944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625269978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.625269978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.2313418965 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 64454800 ps |
| CPU time | 26.96 seconds |
| Started | Sep 09 05:33:32 PM UTC 24 |
| Finished | Sep 09 05:34:01 PM UTC 24 |
| Peak memory | 275012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313418965 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.2313418965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.2611036791 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 103471800 ps |
| CPU time | 324.4 seconds |
| Started | Sep 09 05:32:50 PM UTC 24 |
| Finished | Sep 09 05:38:18 PM UTC 24 |
| Peak memory | 281100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611036791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2611036791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.2222212677 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 97676400 ps |
| CPU time | 78.86 seconds |
| Started | Sep 09 05:34:58 PM UTC 24 |
| Finished | Sep 09 05:36:18 PM UTC 24 |
| Peak memory | 287428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222212677 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.2222212677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1857817590 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 48526000 ps |
| CPU time | 17.59 seconds |
| Started | Sep 09 05:33:02 PM UTC 24 |
| Finished | Sep 09 05:33:21 PM UTC 24 |
| Peak memory | 269280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857817590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.1857817590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.398442348 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 19049800 ps |
| CPU time | 31.06 seconds |
| Started | Sep 09 05:33:06 PM UTC 24 |
| Finished | Sep 09 05:33:39 PM UTC 24 |
| Peak memory | 275064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=398442348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash _ctrl_read_word_sweep_derr.398442348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.4102734495 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 42323800 ps |
| CPU time | 37.63 seconds |
| Started | Sep 09 05:33:02 PM UTC 24 |
| Finished | Sep 09 05:33:41 PM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102734495 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.4102734495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.176654613 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1844459800 ps |
| CPU time | 100.85 seconds |
| Started | Sep 09 05:33:02 PM UTC 24 |
| Finished | Sep 09 05:34:45 PM UTC 24 |
| Peak memory | 291732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=176654613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.176654613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.3009225734 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2749574100 ps |
| CPU time | 143.54 seconds |
| Started | Sep 09 05:33:06 PM UTC 24 |
| Finished | Sep 09 05:35:33 PM UTC 24 |
| Peak memory | 291508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009225734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.3009225734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.3116835678 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3970824400 ps |
| CPU time | 102.71 seconds |
| Started | Sep 09 05:33:04 PM UTC 24 |
| Finished | Sep 09 05:34:49 PM UTC 24 |
| Peak memory | 305840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3116835678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash _ctrl_ro_serr.3116835678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.53519437 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 118092700 ps |
| CPU time | 55.41 seconds |
| Started | Sep 09 05:33:36 PM UTC 24 |
| Finished | Sep 09 05:34:34 PM UTC 24 |
| Peak memory | 281208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=53519437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _rw_evict_all_en.53519437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2867594089 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1945077700 ps |
| CPU time | 6869.32 seconds |
| Started | Sep 09 05:33:50 PM UTC 24 |
| Finished | Sep 09 07:29:30 PM UTC 24 |
| Peak memory | 314152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867594089 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.2867594089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.475596563 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1210019800 ps |
| CPU time | 89.25 seconds |
| Started | Sep 09 05:33:06 PM UTC 24 |
| Finished | Sep 09 05:34:37 PM UTC 24 |
| Peak memory | 275444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47 5596563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser r_counter.475596563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.4031768799 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 36511200 ps |
| CPU time | 59.62 seconds |
| Started | Sep 09 05:32:47 PM UTC 24 |
| Finished | Sep 09 05:33:49 PM UTC 24 |
| Peak memory | 281812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031768799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.4031768799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.3391579057 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 144894300 ps |
| CPU time | 32.72 seconds |
| Started | Sep 09 05:32:47 PM UTC 24 |
| Finished | Sep 09 05:33:22 PM UTC 24 |
| Peak memory | 268892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391579057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.3391579057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.2322899116 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 320242400 ps |
| CPU time | 462.39 seconds |
| Started | Sep 09 05:34:12 PM UTC 24 |
| Finished | Sep 09 05:42:00 PM UTC 24 |
| Peak memory | 301536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322899116 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.2322899116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.122455886 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 26783700 ps |
| CPU time | 40.81 seconds |
| Started | Sep 09 05:32:50 PM UTC 24 |
| Finished | Sep 09 05:33:32 PM UTC 24 |
| Peak memory | 270872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122455886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.122455886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.578038009 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 6475262000 ps |
| CPU time | 234.07 seconds |
| Started | Sep 09 05:33:00 PM UTC 24 |
| Finished | Sep 09 05:36:57 PM UTC 24 |
| Peak memory | 275024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =578038009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.578038009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2937732399 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 42874000 ps |
| CPU time | 27.65 seconds |
| Started | Sep 09 05:33:02 PM UTC 24 |
| Finished | Sep 09 05:33:31 PM UTC 24 |
| Peak memory | 268900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937732399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.2937732399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.1507516686 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 22940100 ps |
| CPU time | 26.73 seconds |
| Started | Sep 09 05:40:05 PM UTC 24 |
| Finished | Sep 09 05:40:33 PM UTC 24 |
| Peak memory | 275008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1507516686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1507516686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.744134193 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 66627000 ps |
| CPU time | 21.03 seconds |
| Started | Sep 09 05:40:39 PM UTC 24 |
| Finished | Sep 09 05:41:01 PM UTC 24 |
| Peak memory | 268916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744134193 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.744134193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.362808816 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 56140600 ps |
| CPU time | 28.33 seconds |
| Started | Sep 09 05:40:15 PM UTC 24 |
| Finished | Sep 09 05:40:45 PM UTC 24 |
| Peak memory | 273204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362808816 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.362808816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2079753966 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 15482800 ps |
| CPU time | 29.91 seconds |
| Started | Sep 09 05:39:43 PM UTC 24 |
| Finished | Sep 09 05:40:15 PM UTC 24 |
| Peak memory | 294676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079753966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.2079753966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.487065119 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 743629900 ps |
| CPU time | 198.87 seconds |
| Started | Sep 09 05:38:19 PM UTC 24 |
| Finished | Sep 09 05:41:41 PM UTC 24 |
| Peak memory | 291512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=487065119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_derr_detect.487065119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.390741902 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 18367700 ps |
| CPU time | 26.21 seconds |
| Started | Sep 09 05:39:26 PM UTC 24 |
| Finished | Sep 09 05:39:53 PM UTC 24 |
| Peak memory | 285332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=390741902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct rl_disable.390741902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3331916889 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 2131559600 ps |
| CPU time | 514.79 seconds |
| Started | Sep 09 05:35:16 PM UTC 24 |
| Finished | Sep 09 05:43:57 PM UTC 24 |
| Peak memory | 274900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331916889 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3331916889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.688262517 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 24060375800 ps |
| CPU time | 3173.47 seconds |
| Started | Sep 09 05:36:05 PM UTC 24 |
| Finished | Sep 09 06:29:30 PM UTC 24 |
| Peak memory | 275560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688262517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.688262517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.31844294 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 571705200 ps |
| CPU time | 1024.66 seconds |
| Started | Sep 09 05:35:52 PM UTC 24 |
| Finished | Sep 09 05:53:08 PM UTC 24 |
| Peak memory | 285156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31844294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/fla sh_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.31844294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.3708602680 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 332475400 ps |
| CPU time | 52.68 seconds |
| Started | Sep 09 05:40:07 PM UTC 24 |
| Finished | Sep 09 05:41:01 PM UTC 24 |
| Peak memory | 272996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708602 680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_f s_sup.3708602680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.4280648156 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 203465925100 ps |
| CPU time | 4090.7 seconds |
| Started | Sep 09 05:35:39 PM UTC 24 |
| Finished | Sep 09 06:44:34 PM UTC 24 |
| Peak memory | 277496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280648156 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.4280648156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2146105188 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 64320700 ps |
| CPU time | 58.52 seconds |
| Started | Sep 09 05:40:34 PM UTC 24 |
| Finished | Sep 09 05:41:34 PM UTC 24 |
| Peak memory | 281212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214610518 8 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ho st_addr_infection.2146105188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.2760592695 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 281691808500 ps |
| CPU time | 3267.44 seconds |
| Started | Sep 09 05:35:33 PM UTC 24 |
| Finished | Sep 09 06:30:34 PM UTC 24 |
| Peak memory | 278192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760592695 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.2760592695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.4118212858 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 42259500 ps |
| CPU time | 91.21 seconds |
| Started | Sep 09 05:35:12 PM UTC 24 |
| Finished | Sep 09 05:36:45 PM UTC 24 |
| Peak memory | 272896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118212858 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.4118212858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3849782107 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 25937000 ps |
| CPU time | 18.07 seconds |
| Started | Sep 09 05:40:29 PM UTC 24 |
| Finished | Sep 09 05:40:49 PM UTC 24 |
| Peak memory | 275228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3849782107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3849782107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.2363643674 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 50125545500 ps |
| CPU time | 734.8 seconds |
| Started | Sep 09 05:35:32 PM UTC 24 |
| Finished | Sep 09 05:47:55 PM UTC 24 |
| Peak memory | 274744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363643674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.2363643674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.3272686431 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 8265872100 ps |
| CPU time | 186.92 seconds |
| Started | Sep 09 05:35:16 PM UTC 24 |
| Finished | Sep 09 05:38:26 PM UTC 24 |
| Peak memory | 274776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272686431 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.3272686431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.2252446038 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5454294800 ps |
| CPU time | 494.49 seconds |
| Started | Sep 09 05:38:27 PM UTC 24 |
| Finished | Sep 09 05:46:47 PM UTC 24 |
| Peak memory | 340620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2252446038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integr ity.2252446038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.2945997567 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1529512300 ps |
| CPU time | 247.43 seconds |
| Started | Sep 09 05:38:35 PM UTC 24 |
| Finished | Sep 09 05:42:46 PM UTC 24 |
| Peak memory | 293584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945997567 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.2945997567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.349308498 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 16944272100 ps |
| CPU time | 281.94 seconds |
| Started | Sep 09 05:38:53 PM UTC 24 |
| Finished | Sep 09 05:43:39 PM UTC 24 |
| Peak memory | 301676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=349308498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_intr_rd_slow_flash.349308498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.349474850 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1740491800 ps |
| CPU time | 64.33 seconds |
| Started | Sep 09 05:38:37 PM UTC 24 |
| Finished | Sep 09 05:39:43 PM UTC 24 |
| Peak memory | 275008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349474850 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.349474850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3633403629 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 22430875100 ps |
| CPU time | 253.99 seconds |
| Started | Sep 09 05:39:00 PM UTC 24 |
| Finished | Sep 09 05:43:18 PM UTC 24 |
| Peak memory | 275060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633403629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3633403629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.9356920 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1748874100 ps |
| CPU time | 63.04 seconds |
| Started | Sep 09 05:36:20 PM UTC 24 |
| Finished | Sep 09 05:37:25 PM UTC 24 |
| Peak memory | 270668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9356920 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.9356920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.3230020156 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 22174800 ps |
| CPU time | 25.22 seconds |
| Started | Sep 09 05:40:25 PM UTC 24 |
| Finished | Sep 09 05:40:52 PM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3230020156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_lcmgr_intg.3230020156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.536616134 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2479735200 ps |
| CPU time | 188.32 seconds |
| Started | Sep 09 05:38:26 PM UTC 24 |
| Finished | Sep 09 05:41:37 PM UTC 24 |
| Peak memory | 291524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=536616134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_oversize_error.536616134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1646147595 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 45505200 ps |
| CPU time | 198.74 seconds |
| Started | Sep 09 05:35:15 PM UTC 24 |
| Finished | Sep 09 05:38:36 PM UTC 24 |
| Peak memory | 275164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646147595 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1646147595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.3804903680 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 794071900 ps |
| CPU time | 37.82 seconds |
| Started | Sep 09 05:40:09 PM UTC 24 |
| Finished | Sep 09 05:40:48 PM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3804903680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3804903680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2467173467 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 45298800 ps |
| CPU time | 20.79 seconds |
| Started | Sep 09 05:40:10 PM UTC 24 |
| Finished | Sep 09 05:40:32 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2467173467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2467173467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.185194169 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 93162200 ps |
| CPU time | 27 seconds |
| Started | Sep 09 05:39:06 PM UTC 24 |
| Finished | Sep 09 05:39:34 PM UTC 24 |
| Peak memory | 274996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185194169 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.185194169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.3730941250 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 451648900 ps |
| CPU time | 1275.28 seconds |
| Started | Sep 09 05:35:09 PM UTC 24 |
| Finished | Sep 09 05:56:39 PM UTC 24 |
| Peak memory | 291336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730941250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3730941250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.2351148993 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 115806900 ps |
| CPU time | 41.99 seconds |
| Started | Sep 09 05:39:54 PM UTC 24 |
| Finished | Sep 09 05:40:38 PM UTC 24 |
| Peak memory | 287416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235114899 3 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.2351148993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.935544876 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 722359600 ps |
| CPU time | 38.77 seconds |
| Started | Sep 09 05:39:26 PM UTC 24 |
| Finished | Sep 09 05:40:06 PM UTC 24 |
| Peak memory | 287452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935544876 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.935544876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.1283790033 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 18535700 ps |
| CPU time | 44.37 seconds |
| Started | Sep 09 05:37:38 PM UTC 24 |
| Finished | Sep 09 05:38:24 PM UTC 24 |
| Peak memory | 275376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1283790033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_read_word_sweep_derr.1283790033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3496306376 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 111900300 ps |
| CPU time | 38.33 seconds |
| Started | Sep 09 05:36:58 PM UTC 24 |
| Finished | Sep 09 05:37:38 PM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496306376 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.3496306376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.3875281456 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 41784884200 ps |
| CPU time | 822.14 seconds |
| Started | Sep 09 05:40:23 PM UTC 24 |
| Finished | Sep 09 05:54:15 PM UTC 24 |
| Peak memory | 274720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3875281456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. flash_ctrl_rma_err.3875281456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.3093025309 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 944579100 ps |
| CPU time | 139.97 seconds |
| Started | Sep 09 05:36:29 PM UTC 24 |
| Finished | Sep 09 05:38:52 PM UTC 24 |
| Peak memory | 291780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3093025309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.3093025309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.515646628 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2277934200 ps |
| CPU time | 136.36 seconds |
| Started | Sep 09 05:37:39 PM UTC 24 |
| Finished | Sep 09 05:39:58 PM UTC 24 |
| Peak memory | 291440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515646628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.515646628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3667811319 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1617932300 ps |
| CPU time | 149.01 seconds |
| Started | Sep 09 05:36:58 PM UTC 24 |
| Finished | Sep 09 05:39:30 PM UTC 24 |
| Peak memory | 301744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3667811319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_ro_serr.3667811319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.312943239 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 32748867300 ps |
| CPU time | 431.29 seconds |
| Started | Sep 09 05:36:46 PM UTC 24 |
| Finished | Sep 09 05:44:03 PM UTC 24 |
| Peak memory | 324484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312943239 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.312943239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.2636250387 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1727867200 ps |
| CPU time | 187.44 seconds |
| Started | Sep 09 05:37:40 PM UTC 24 |
| Finished | Sep 09 05:40:51 PM UTC 24 |
| Peak memory | 299628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2636250387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 1.flash_ctrl_rw_derr.2636250387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.2175339349 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 41064400 ps |
| CPU time | 44.83 seconds |
| Started | Sep 09 05:39:22 PM UTC 24 |
| Finished | Sep 09 05:40:08 PM UTC 24 |
| Peak memory | 287356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2175339349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct rl_rw_evict_all_en.2175339349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.2723204012 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4247525100 ps |
| CPU time | 219.97 seconds |
| Started | Sep 09 05:37:26 PM UTC 24 |
| Finished | Sep 09 05:41:09 PM UTC 24 |
| Peak memory | 301744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2723204012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.2723204012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1597725250 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 7806144700 ps |
| CPU time | 101.83 seconds |
| Started | Sep 09 05:37:37 PM UTC 24 |
| Finished | Sep 09 05:39:21 PM UTC 24 |
| Peak memory | 285388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159 7725250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser r_address.1597725250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3353137793 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2164500700 ps |
| CPU time | 94.95 seconds |
| Started | Sep 09 05:37:28 PM UTC 24 |
| Finished | Sep 09 05:39:05 PM UTC 24 |
| Peak memory | 285360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 53137793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se rr_counter.3353137793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.823098157 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 55164900 ps |
| CPU time | 111.72 seconds |
| Started | Sep 09 05:35:04 PM UTC 24 |
| Finished | Sep 09 05:36:58 PM UTC 24 |
| Peak memory | 287192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823098157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.823098157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.4159348001 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 14680400 ps |
| CPU time | 28.9 seconds |
| Started | Sep 09 05:35:08 PM UTC 24 |
| Finished | Sep 09 05:35:39 PM UTC 24 |
| Peak memory | 270616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159348001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.4159348001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.177448704 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 523708500 ps |
| CPU time | 174.38 seconds |
| Started | Sep 09 05:39:35 PM UTC 24 |
| Finished | Sep 09 05:42:32 PM UTC 24 |
| Peak memory | 272660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177448704 -assert nopostproc +UVM_TESTNA ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.177448704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.2392205847 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 24925800 ps |
| CPU time | 30.44 seconds |
| Started | Sep 09 05:35:11 PM UTC 24 |
| Finished | Sep 09 05:35:43 PM UTC 24 |
| Peak memory | 270620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392205847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2392205847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.564847151 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2039451900 ps |
| CPU time | 155.67 seconds |
| Started | Sep 09 05:36:26 PM UTC 24 |
| Finished | Sep 09 05:39:04 PM UTC 24 |
| Peak memory | 275280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =564847151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.564847151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.89266959 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 158979700 ps |
| CPU time | 24.95 seconds |
| Started | Sep 09 06:16:55 PM UTC 24 |
| Finished | Sep 09 06:17:21 PM UTC 24 |
| Peak memory | 275060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89266959 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.89266959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.214540982 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 18822700 ps |
| CPU time | 25.12 seconds |
| Started | Sep 09 06:16:36 PM UTC 24 |
| Finished | Sep 09 06:17:02 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214540982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.214540982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.292206915 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 50451500 ps |
| CPU time | 34.56 seconds |
| Started | Sep 09 06:16:30 PM UTC 24 |
| Finished | Sep 09 06:17:06 PM UTC 24 |
| Peak memory | 285684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=292206915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c trl_disable.292206915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2159518389 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 10096109100 ps |
| CPU time | 51.4 seconds |
| Started | Sep 09 06:16:53 PM UTC 24 |
| Finished | Sep 09 06:17:46 PM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2159518389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2159518389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.3418050044 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 15773600 ps |
| CPU time | 23.58 seconds |
| Started | Sep 09 06:16:44 PM UTC 24 |
| Finished | Sep 09 06:17:09 PM UTC 24 |
| Peak memory | 275048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3418050044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.3418050044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.871702408 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 80139500600 ps |
| CPU time | 803.26 seconds |
| Started | Sep 09 06:14:57 PM UTC 24 |
| Finished | Sep 09 06:28:29 PM UTC 24 |
| Peak memory | 274740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871702408 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_reset.871702408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.480142472 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 10348320300 ps |
| CPU time | 88.85 seconds |
| Started | Sep 09 06:14:56 PM UTC 24 |
| Finished | Sep 09 06:16:27 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480142472 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.480142472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.32419988 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 697670900 ps |
| CPU time | 121.66 seconds |
| Started | Sep 09 06:15:38 PM UTC 24 |
| Finished | Sep 09 06:17:41 PM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32419988 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.32419988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3095114339 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 5797280600 ps |
| CPU time | 133.74 seconds |
| Started | Sep 09 06:16:19 PM UTC 24 |
| Finished | Sep 09 06:18:35 PM UTC 24 |
| Peak memory | 303676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3095114339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_intr_rd_slow_flash.3095114339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.1225011795 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 4035737400 ps |
| CPU time | 79.41 seconds |
| Started | Sep 09 06:15:04 PM UTC 24 |
| Finished | Sep 09 06:16:25 PM UTC 24 |
| Peak memory | 272716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225011795 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.1225011795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.513761573 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 47666600 ps |
| CPU time | 28.43 seconds |
| Started | Sep 09 06:16:39 PM UTC 24 |
| Finished | Sep 09 06:17:09 PM UTC 24 |
| Peak memory | 270964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=513761573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flas h_ctrl_lcmgr_intg.513761573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.881135421 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 9601595900 ps |
| CPU time | 344.67 seconds |
| Started | Sep 09 06:15:01 PM UTC 24 |
| Finished | Sep 09 06:20:51 PM UTC 24 |
| Peak memory | 283412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=881135421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 10.flash_ctrl_mp_regions.881135421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.1188696459 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 37040800 ps |
| CPU time | 162.31 seconds |
| Started | Sep 09 06:14:58 PM UTC 24 |
| Finished | Sep 09 06:17:43 PM UTC 24 |
| Peak memory | 271300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188696459 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.1188696459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.2425293284 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 3760234800 ps |
| CPU time | 202.39 seconds |
| Started | Sep 09 06:14:52 PM UTC 24 |
| Finished | Sep 09 06:18:17 PM UTC 24 |
| Peak memory | 274940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425293284 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.2425293284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.1966197732 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 17603000 ps |
| CPU time | 20.93 seconds |
| Started | Sep 09 06:16:21 PM UTC 24 |
| Finished | Sep 09 06:16:43 PM UTC 24 |
| Peak memory | 268856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966197732 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.1966197732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.3984049661 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 46292000 ps |
| CPU time | 263.06 seconds |
| Started | Sep 09 06:14:49 PM UTC 24 |
| Finished | Sep 09 06:19:16 PM UTC 24 |
| Peak memory | 291608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984049661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.3984049661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.262075243 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 279414800 ps |
| CPU time | 56.1 seconds |
| Started | Sep 09 06:16:28 PM UTC 24 |
| Finished | Sep 09 06:17:26 PM UTC 24 |
| Peak memory | 287780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262075243 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.262075243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.131846103 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 777387700 ps |
| CPU time | 137.57 seconds |
| Started | Sep 09 06:15:13 PM UTC 24 |
| Finished | Sep 09 06:17:33 PM UTC 24 |
| Peak memory | 308192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=131846103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.131846103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2309458158 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 47541900 ps |
| CPU time | 61.44 seconds |
| Started | Sep 09 06:16:26 PM UTC 24 |
| Finished | Sep 09 06:17:30 PM UTC 24 |
| Peak memory | 281408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309458158 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.2309458158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.2747681995 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 69040700 ps |
| CPU time | 42.5 seconds |
| Started | Sep 09 06:16:27 PM UTC 24 |
| Finished | Sep 09 06:17:12 PM UTC 24 |
| Peak memory | 287552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2747681995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c trl_rw_evict_all_en.2747681995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.4194894572 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 29028700 ps |
| CPU time | 200.14 seconds |
| Started | Sep 09 06:14:45 PM UTC 24 |
| Finished | Sep 09 06:18:08 PM UTC 24 |
| Peak memory | 287232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194894572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.4194894572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.2594823845 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2333881200 ps |
| CPU time | 184.64 seconds |
| Started | Sep 09 06:15:06 PM UTC 24 |
| Finished | Sep 09 06:18:14 PM UTC 24 |
| Peak memory | 270940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2594823845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.2594823845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.516942472 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 60965600 ps |
| CPU time | 23.33 seconds |
| Started | Sep 09 06:18:55 PM UTC 24 |
| Finished | Sep 09 06:19:20 PM UTC 24 |
| Peak memory | 268928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516942472 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.516942472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.2771754652 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 40287600 ps |
| CPU time | 24.44 seconds |
| Started | Sep 09 06:18:36 PM UTC 24 |
| Finished | Sep 09 06:19:01 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771754652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.2771754652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.4217699176 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 12969700 ps |
| CPU time | 29.49 seconds |
| Started | Sep 09 06:18:18 PM UTC 24 |
| Finished | Sep 09 06:18:49 PM UTC 24 |
| Peak memory | 285360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4217699176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ ctrl_disable.4217699176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.3657113540 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 40125308600 ps |
| CPU time | 744.53 seconds |
| Started | Sep 09 06:17:13 PM UTC 24 |
| Finished | Sep 09 06:29:45 PM UTC 24 |
| Peak memory | 275048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657113540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res et.3657113540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.2689500118 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 12901454400 ps |
| CPU time | 257.34 seconds |
| Started | Sep 09 06:17:09 PM UTC 24 |
| Finished | Sep 09 06:21:31 PM UTC 24 |
| Peak memory | 275040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689500118 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.2689500118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.1411103907 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 744151000 ps |
| CPU time | 185.26 seconds |
| Started | Sep 09 06:17:43 PM UTC 24 |
| Finished | Sep 09 06:20:52 PM UTC 24 |
| Peak memory | 305840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411103907 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.1411103907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.774885624 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 31151929600 ps |
| CPU time | 296.49 seconds |
| Started | Sep 09 06:17:46 PM UTC 24 |
| Finished | Sep 09 06:22:47 PM UTC 24 |
| Peak memory | 301672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=774885624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 11.flash_ctrl_intr_rd_slow_flash.774885624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.1746084873 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5045444700 ps |
| CPU time | 93.56 seconds |
| Started | Sep 09 06:17:31 PM UTC 24 |
| Finished | Sep 09 06:19:07 PM UTC 24 |
| Peak memory | 272716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746084873 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1746084873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.1156420201 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 26446100 ps |
| CPU time | 18.49 seconds |
| Started | Sep 09 06:18:40 PM UTC 24 |
| Finished | Sep 09 06:18:59 PM UTC 24 |
| Peak memory | 271044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1156420201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_lcmgr_intg.1156420201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3700876681 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 11971946200 ps |
| CPU time | 619.78 seconds |
| Started | Sep 09 06:17:27 PM UTC 24 |
| Finished | Sep 09 06:27:54 PM UTC 24 |
| Peak memory | 283076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3700876681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.3700876681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3149863273 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 79008500 ps |
| CPU time | 212.38 seconds |
| Started | Sep 09 06:17:22 PM UTC 24 |
| Finished | Sep 09 06:20:57 PM UTC 24 |
| Peak memory | 270644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149863273 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.3149863273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.2844475892 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 1479950300 ps |
| CPU time | 589.16 seconds |
| Started | Sep 09 06:17:09 PM UTC 24 |
| Finished | Sep 09 06:27:05 PM UTC 24 |
| Peak memory | 275160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844475892 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2844475892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.37721980 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 18957300 ps |
| CPU time | 24.87 seconds |
| Started | Sep 09 06:17:53 PM UTC 24 |
| Finished | Sep 09 06:18:19 PM UTC 24 |
| Peak memory | 275016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37721980 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.37721980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.841895920 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 109635500 ps |
| CPU time | 745.94 seconds |
| Started | Sep 09 06:17:06 PM UTC 24 |
| Finished | Sep 09 06:29:41 PM UTC 24 |
| Peak memory | 291596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841895920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.841895920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3174911007 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 148355800 ps |
| CPU time | 66.41 seconds |
| Started | Sep 09 06:18:15 PM UTC 24 |
| Finished | Sep 09 06:19:24 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174911007 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.3174911007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2575722396 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1286366000 ps |
| CPU time | 83.53 seconds |
| Started | Sep 09 06:17:42 PM UTC 24 |
| Finished | Sep 09 06:19:07 PM UTC 24 |
| Peak memory | 291524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2575722396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.2575722396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.4238621024 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4335061100 ps |
| CPU time | 504.83 seconds |
| Started | Sep 09 06:17:42 PM UTC 24 |
| Finished | Sep 09 06:26:13 PM UTC 24 |
| Peak memory | 320152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238621024 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.4238621024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1644841636 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 28334500 ps |
| CPU time | 43.73 seconds |
| Started | Sep 09 06:17:53 PM UTC 24 |
| Finished | Sep 09 06:18:39 PM UTC 24 |
| Peak memory | 283584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644841636 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.1644841636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.135472797 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 86021800 ps |
| CPU time | 216.68 seconds |
| Started | Sep 09 06:17:03 PM UTC 24 |
| Finished | Sep 09 06:20:43 PM UTC 24 |
| Peak memory | 287248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135472797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.135472797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.2729522148 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1925552000 ps |
| CPU time | 124.37 seconds |
| Started | Sep 09 06:17:34 PM UTC 24 |
| Finished | Sep 09 06:19:41 PM UTC 24 |
| Peak memory | 271172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2729522148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.2729522148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1975905596 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 55924700 ps |
| CPU time | 23.4 seconds |
| Started | Sep 09 06:21:09 PM UTC 24 |
| Finished | Sep 09 06:21:34 PM UTC 24 |
| Peak memory | 275052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975905596 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.1975905596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1028799862 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 40363700 ps |
| CPU time | 27.02 seconds |
| Started | Sep 09 06:20:51 PM UTC 24 |
| Finished | Sep 09 06:21:19 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028799862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1028799862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2766714525 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 10011572900 ps |
| CPU time | 176.78 seconds |
| Started | Sep 09 06:20:59 PM UTC 24 |
| Finished | Sep 09 06:23:59 PM UTC 24 |
| Peak memory | 314132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2766714525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2766714525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.437832481 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 206036700 ps |
| CPU time | 28.71 seconds |
| Started | Sep 09 06:20:53 PM UTC 24 |
| Finished | Sep 09 06:21:23 PM UTC 24 |
| Peak memory | 269196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=437832481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.flash_ctrl_hw_read_seed_err.437832481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.4126689830 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 40121716000 ps |
| CPU time | 784.11 seconds |
| Started | Sep 09 06:19:08 PM UTC 24 |
| Finished | Sep 09 06:32:21 PM UTC 24 |
| Peak memory | 274984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126689830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_res et.4126689830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3189360610 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 16967659800 ps |
| CPU time | 198.35 seconds |
| Started | Sep 09 06:19:08 PM UTC 24 |
| Finished | Sep 09 06:22:30 PM UTC 24 |
| Peak memory | 275040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189360610 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.3189360610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.503748849 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 15688114500 ps |
| CPU time | 242.08 seconds |
| Started | Sep 09 06:19:42 PM UTC 24 |
| Finished | Sep 09 06:23:47 PM UTC 24 |
| Peak memory | 301736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503748849 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.503748849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3568331904 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 72428947800 ps |
| CPU time | 217.05 seconds |
| Started | Sep 09 06:20:03 PM UTC 24 |
| Finished | Sep 09 06:23:44 PM UTC 24 |
| Peak memory | 303708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3568331904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_intr_rd_slow_flash.3568331904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.502522743 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 1730964700 ps |
| CPU time | 87.78 seconds |
| Started | Sep 09 06:19:20 PM UTC 24 |
| Finished | Sep 09 06:20:50 PM UTC 24 |
| Peak memory | 274756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502522743 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.502522743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.1669092229 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 98930200 ps |
| CPU time | 25.03 seconds |
| Started | Sep 09 06:20:53 PM UTC 24 |
| Finished | Sep 09 06:21:19 PM UTC 24 |
| Peak memory | 271044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1669092229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_lcmgr_intg.1669092229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.764502893 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 15560606100 ps |
| CPU time | 987 seconds |
| Started | Sep 09 06:19:17 PM UTC 24 |
| Finished | Sep 09 06:35:56 PM UTC 24 |
| Peak memory | 283076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=764502893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 12.flash_ctrl_mp_regions.764502893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.3537578557 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 126311100 ps |
| CPU time | 201.69 seconds |
| Started | Sep 09 06:19:14 PM UTC 24 |
| Finished | Sep 09 06:22:39 PM UTC 24 |
| Peak memory | 271052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537578557 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.3537578557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.405421377 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 31877900 ps |
| CPU time | 150.66 seconds |
| Started | Sep 09 06:19:02 PM UTC 24 |
| Finished | Sep 09 06:21:36 PM UTC 24 |
| Peak memory | 274956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405421377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.405421377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2269441818 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2144363900 ps |
| CPU time | 190.22 seconds |
| Started | Sep 09 06:20:04 PM UTC 24 |
| Finished | Sep 09 06:23:17 PM UTC 24 |
| Peak memory | 275004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269441818 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.2269441818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.3631509776 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 151729900 ps |
| CPU time | 1016.56 seconds |
| Started | Sep 09 06:19:00 PM UTC 24 |
| Finished | Sep 09 06:36:08 PM UTC 24 |
| Peak memory | 293644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631509776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3631509776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2160015562 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 176132300 ps |
| CPU time | 51.12 seconds |
| Started | Sep 09 06:20:28 PM UTC 24 |
| Finished | Sep 09 06:21:21 PM UTC 24 |
| Peak memory | 289472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160015562 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.2160015562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.4018302626 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1178994000 ps |
| CPU time | 135.99 seconds |
| Started | Sep 09 06:19:30 PM UTC 24 |
| Finished | Sep 09 06:21:49 PM UTC 24 |
| Peak memory | 303728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4018302626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.4018302626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.2812350274 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3721399000 ps |
| CPU time | 461.01 seconds |
| Started | Sep 09 06:19:32 PM UTC 24 |
| Finished | Sep 09 06:27:19 PM UTC 24 |
| Peak memory | 320192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812350274 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.2812350274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.687474242 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 33435200 ps |
| CPU time | 60.98 seconds |
| Started | Sep 09 06:20:05 PM UTC 24 |
| Finished | Sep 09 06:21:08 PM UTC 24 |
| Peak memory | 287744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687474242 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.687474242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.54420773 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 156589600 ps |
| CPU time | 40.35 seconds |
| Started | Sep 09 06:20:27 PM UTC 24 |
| Finished | Sep 09 06:21:09 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=54420773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctr l_rw_evict_all_en.54420773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.3843925604 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3415561500 ps |
| CPU time | 99.35 seconds |
| Started | Sep 09 06:20:49 PM UTC 24 |
| Finished | Sep 09 06:22:30 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843925604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3843925604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.2952463781 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 60720700 ps |
| CPU time | 84.7 seconds |
| Started | Sep 09 06:18:59 PM UTC 24 |
| Finished | Sep 09 06:20:26 PM UTC 24 |
| Peak memory | 283148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952463781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2952463781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.1480831783 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1984047900 ps |
| CPU time | 167.28 seconds |
| Started | Sep 09 06:19:24 PM UTC 24 |
| Finished | Sep 09 06:22:15 PM UTC 24 |
| Peak memory | 270916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1480831783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.1480831783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.2319041482 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 65292100 ps |
| CPU time | 19.26 seconds |
| Started | Sep 09 06:23:55 PM UTC 24 |
| Finished | Sep 09 06:24:15 PM UTC 24 |
| Peak memory | 268920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319041482 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.2319041482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.1499152575 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 22983000 ps |
| CPU time | 27.48 seconds |
| Started | Sep 09 06:23:29 PM UTC 24 |
| Finished | Sep 09 06:23:58 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499152575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1499152575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.2146091925 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 17904700 ps |
| CPU time | 38.1 seconds |
| Started | Sep 09 06:23:18 PM UTC 24 |
| Finished | Sep 09 06:23:58 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2146091925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ ctrl_disable.2146091925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2828521271 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 10012691700 ps |
| CPU time | 170.05 seconds |
| Started | Sep 09 06:23:49 PM UTC 24 |
| Finished | Sep 09 06:26:42 PM UTC 24 |
| Peak memory | 365592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2828521271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2828521271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.3819937357 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 15201700 ps |
| CPU time | 19.92 seconds |
| Started | Sep 09 06:23:45 PM UTC 24 |
| Finished | Sep 09 06:24:06 PM UTC 24 |
| Peak memory | 274976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3819937357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3819937357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.1832684410 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 80148616100 ps |
| CPU time | 907.37 seconds |
| Started | Sep 09 06:21:21 PM UTC 24 |
| Finished | Sep 09 06:36:39 PM UTC 24 |
| Peak memory | 272692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832684410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_res et.1832684410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.3456460940 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 30792604300 ps |
| CPU time | 266.15 seconds |
| Started | Sep 09 06:21:20 PM UTC 24 |
| Finished | Sep 09 06:25:50 PM UTC 24 |
| Peak memory | 274768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456460940 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.3456460940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.1472193754 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 21062462900 ps |
| CPU time | 203.08 seconds |
| Started | Sep 09 06:22:16 PM UTC 24 |
| Finished | Sep 09 06:25:42 PM UTC 24 |
| Peak memory | 301748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472193754 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.1472193754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3072027910 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 53141788100 ps |
| CPU time | 275.64 seconds |
| Started | Sep 09 06:22:30 PM UTC 24 |
| Finished | Sep 09 06:27:10 PM UTC 24 |
| Peak memory | 301988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3072027910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_intr_rd_slow_flash.3072027910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3529640086 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 5113193200 ps |
| CPU time | 81.53 seconds |
| Started | Sep 09 06:21:34 PM UTC 24 |
| Finished | Sep 09 06:22:57 PM UTC 24 |
| Peak memory | 270668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529640086 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3529640086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.4100099072 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 27101800 ps |
| CPU time | 22.22 seconds |
| Started | Sep 09 06:23:37 PM UTC 24 |
| Finished | Sep 09 06:24:00 PM UTC 24 |
| Peak memory | 271040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4100099072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_lcmgr_intg.4100099072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.3021719410 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 20926728000 ps |
| CPU time | 281.98 seconds |
| Started | Sep 09 06:21:32 PM UTC 24 |
| Finished | Sep 09 06:26:18 PM UTC 24 |
| Peak memory | 283072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3021719410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.3021719410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.987163297 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 37726800 ps |
| CPU time | 198.18 seconds |
| Started | Sep 09 06:21:24 PM UTC 24 |
| Finished | Sep 09 06:24:45 PM UTC 24 |
| Peak memory | 270788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987163297 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.987163297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.1557454812 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 12105327500 ps |
| CPU time | 633.91 seconds |
| Started | Sep 09 06:21:19 PM UTC 24 |
| Finished | Sep 09 06:32:01 PM UTC 24 |
| Peak memory | 272848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557454812 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.1557454812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.3115395298 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3177864200 ps |
| CPU time | 216.99 seconds |
| Started | Sep 09 06:22:32 PM UTC 24 |
| Finished | Sep 09 06:26:12 PM UTC 24 |
| Peak memory | 270912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115395298 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.3115395298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.3487656320 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 958129800 ps |
| CPU time | 477.06 seconds |
| Started | Sep 09 06:21:14 PM UTC 24 |
| Finished | Sep 09 06:29:17 PM UTC 24 |
| Peak memory | 291660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487656320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3487656320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.474811414 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 110938400 ps |
| CPU time | 54.62 seconds |
| Started | Sep 09 06:22:58 PM UTC 24 |
| Finished | Sep 09 06:23:54 PM UTC 24 |
| Peak memory | 285732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474811414 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.474811414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1489698672 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1495272200 ps |
| CPU time | 141.34 seconds |
| Started | Sep 09 06:21:37 PM UTC 24 |
| Finished | Sep 09 06:24:01 PM UTC 24 |
| Peak memory | 301724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1489698672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.1489698672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.2998436154 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3783509400 ps |
| CPU time | 535.64 seconds |
| Started | Sep 09 06:21:50 PM UTC 24 |
| Finished | Sep 09 06:30:53 PM UTC 24 |
| Peak memory | 324272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998436154 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.2998436154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.1751802011 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 30953100 ps |
| CPU time | 42.93 seconds |
| Started | Sep 09 06:22:40 PM UTC 24 |
| Finished | Sep 09 06:23:24 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751802011 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.1751802011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.831292486 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 62564400 ps |
| CPU time | 38.98 seconds |
| Started | Sep 09 06:22:48 PM UTC 24 |
| Finished | Sep 09 06:23:28 PM UTC 24 |
| Peak memory | 281204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=831292486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ct rl_rw_evict_all_en.831292486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.3220787310 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 446090100 ps |
| CPU time | 56.23 seconds |
| Started | Sep 09 06:23:25 PM UTC 24 |
| Finished | Sep 09 06:24:23 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220787310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.3220787310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.1660197431 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 138684300 ps |
| CPU time | 172.89 seconds |
| Started | Sep 09 06:21:10 PM UTC 24 |
| Finished | Sep 09 06:24:05 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660197431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1660197431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.3183948033 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 4449053300 ps |
| CPU time | 208.86 seconds |
| Started | Sep 09 06:21:35 PM UTC 24 |
| Finished | Sep 09 06:25:07 PM UTC 24 |
| Peak memory | 275012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3183948033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.3183948033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.3238993792 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 55721900 ps |
| CPU time | 24.27 seconds |
| Started | Sep 09 06:26:27 PM UTC 24 |
| Finished | Sep 09 06:26:52 PM UTC 24 |
| Peak memory | 269236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238993792 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.3238993792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.28851525 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 170852400 ps |
| CPU time | 20.74 seconds |
| Started | Sep 09 06:26:13 PM UTC 24 |
| Finished | Sep 09 06:26:35 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28851525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.28851525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.1335836712 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 13063100 ps |
| CPU time | 32.94 seconds |
| Started | Sep 09 06:25:52 PM UTC 24 |
| Finished | Sep 09 06:26:26 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1335836712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ ctrl_disable.1335836712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1929875841 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 10017353700 ps |
| CPU time | 142.16 seconds |
| Started | Sep 09 06:26:19 PM UTC 24 |
| Finished | Sep 09 06:28:43 PM UTC 24 |
| Peak memory | 330452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1929875841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1929875841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.2117219284 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 47194600 ps |
| CPU time | 28.36 seconds |
| Started | Sep 09 06:26:19 PM UTC 24 |
| Finished | Sep 09 06:26:48 PM UTC 24 |
| Peak memory | 275116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2117219284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2117219284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.3253705782 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 80137335400 ps |
| CPU time | 813.32 seconds |
| Started | Sep 09 06:24:01 PM UTC 24 |
| Finished | Sep 09 06:37:44 PM UTC 24 |
| Peak memory | 274748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253705782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_res et.3253705782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.2935343802 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2760267700 ps |
| CPU time | 81.95 seconds |
| Started | Sep 09 06:24:01 PM UTC 24 |
| Finished | Sep 09 06:25:25 PM UTC 24 |
| Peak memory | 272984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935343802 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.2935343802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.130038154 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3000251200 ps |
| CPU time | 187.13 seconds |
| Started | Sep 09 06:24:49 PM UTC 24 |
| Finished | Sep 09 06:27:59 PM UTC 24 |
| Peak memory | 302032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130038154 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.130038154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3937717095 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 199192857700 ps |
| CPU time | 527.09 seconds |
| Started | Sep 09 06:25:03 PM UTC 24 |
| Finished | Sep 09 06:33:57 PM UTC 24 |
| Peak memory | 301924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3937717095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_intr_rd_slow_flash.3937717095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.988441047 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1497723200 ps |
| CPU time | 53.49 seconds |
| Started | Sep 09 06:24:07 PM UTC 24 |
| Finished | Sep 09 06:25:02 PM UTC 24 |
| Peak memory | 270668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988441047 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.988441047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.259821092 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 15144900 ps |
| CPU time | 23.16 seconds |
| Started | Sep 09 06:26:14 PM UTC 24 |
| Finished | Sep 09 06:26:38 PM UTC 24 |
| Peak memory | 275128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=259821092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas h_ctrl_lcmgr_intg.259821092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.1976218844 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 12118513200 ps |
| CPU time | 299.28 seconds |
| Started | Sep 09 06:24:07 PM UTC 24 |
| Finished | Sep 09 06:29:10 PM UTC 24 |
| Peak memory | 283072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1976218844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.1976218844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.1363806648 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 128777000 ps |
| CPU time | 163.15 seconds |
| Started | Sep 09 06:24:06 PM UTC 24 |
| Finished | Sep 09 06:26:52 PM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363806648 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.1363806648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.2444462209 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 11070607100 ps |
| CPU time | 518 seconds |
| Started | Sep 09 06:24:00 PM UTC 24 |
| Finished | Sep 09 06:32:45 PM UTC 24 |
| Peak memory | 274952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444462209 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.2444462209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.1301797100 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 55552600 ps |
| CPU time | 25.39 seconds |
| Started | Sep 09 06:25:07 PM UTC 24 |
| Finished | Sep 09 06:25:34 PM UTC 24 |
| Peak memory | 268852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301797100 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.1301797100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.3770079992 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 656929800 ps |
| CPU time | 1609.78 seconds |
| Started | Sep 09 06:23:59 PM UTC 24 |
| Finished | Sep 09 06:51:06 PM UTC 24 |
| Peak memory | 297804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770079992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3770079992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.692186394 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 113513000 ps |
| CPU time | 50.25 seconds |
| Started | Sep 09 06:25:43 PM UTC 24 |
| Finished | Sep 09 06:26:35 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692186394 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.692186394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.1945341999 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 550964400 ps |
| CPU time | 139.34 seconds |
| Started | Sep 09 06:24:24 PM UTC 24 |
| Finished | Sep 09 06:26:46 PM UTC 24 |
| Peak memory | 303840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1945341999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.1945341999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.4177583904 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3707616000 ps |
| CPU time | 491.9 seconds |
| Started | Sep 09 06:24:46 PM UTC 24 |
| Finished | Sep 09 06:33:04 PM UTC 24 |
| Peak memory | 324504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177583904 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.4177583904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.2643932130 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 84697100 ps |
| CPU time | 48.84 seconds |
| Started | Sep 09 06:25:27 PM UTC 24 |
| Finished | Sep 09 06:26:17 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643932130 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.2643932130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.1597677716 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 30044000 ps |
| CPU time | 60.74 seconds |
| Started | Sep 09 06:25:35 PM UTC 24 |
| Finished | Sep 09 06:26:37 PM UTC 24 |
| Peak memory | 285408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1597677716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c trl_rw_evict_all_en.1597677716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.1275473654 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 21938900 ps |
| CPU time | 160.45 seconds |
| Started | Sep 09 06:23:59 PM UTC 24 |
| Finished | Sep 09 06:26:42 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275473654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1275473654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.3124429033 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 9986210700 ps |
| CPU time | 185.39 seconds |
| Started | Sep 09 06:24:17 PM UTC 24 |
| Finished | Sep 09 06:27:25 PM UTC 24 |
| Peak memory | 270916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3124429033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.3124429033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.1033795459 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 564762700 ps |
| CPU time | 17.5 seconds |
| Started | Sep 09 06:28:23 PM UTC 24 |
| Finished | Sep 09 06:28:42 PM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033795459 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.1033795459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.3992887062 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 26996200 ps |
| CPU time | 18.09 seconds |
| Started | Sep 09 06:27:56 PM UTC 24 |
| Finished | Sep 09 06:28:15 PM UTC 24 |
| Peak memory | 294812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992887062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3992887062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.4192612153 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 10019569200 ps |
| CPU time | 104.04 seconds |
| Started | Sep 09 06:28:16 PM UTC 24 |
| Finished | Sep 09 06:30:02 PM UTC 24 |
| Peak memory | 295696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4192612153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.4192612153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.3601165341 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 51839800 ps |
| CPU time | 16.42 seconds |
| Started | Sep 09 06:28:11 PM UTC 24 |
| Finished | Sep 09 06:28:28 PM UTC 24 |
| Peak memory | 271304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3601165341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.3601165341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.4275108245 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 160183806300 ps |
| CPU time | 1027.15 seconds |
| Started | Sep 09 06:26:42 PM UTC 24 |
| Finished | Sep 09 06:44:02 PM UTC 24 |
| Peak memory | 274740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275108245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_res et.4275108245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.1875924696 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2751701600 ps |
| CPU time | 88.81 seconds |
| Started | Sep 09 06:26:39 PM UTC 24 |
| Finished | Sep 09 06:28:10 PM UTC 24 |
| Peak memory | 274908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875924696 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.1875924696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.734641676 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1436073600 ps |
| CPU time | 156.12 seconds |
| Started | Sep 09 06:27:11 PM UTC 24 |
| Finished | Sep 09 06:29:50 PM UTC 24 |
| Peak memory | 305864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734641676 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.734641676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.1264888385 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 7118811200 ps |
| CPU time | 63.1 seconds |
| Started | Sep 09 06:26:50 PM UTC 24 |
| Finished | Sep 09 06:27:54 PM UTC 24 |
| Peak memory | 274764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264888385 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1264888385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.1566776690 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 203205400 ps |
| CPU time | 24.1 seconds |
| Started | Sep 09 06:28:00 PM UTC 24 |
| Finished | Sep 09 06:28:25 PM UTC 24 |
| Peak memory | 271300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1566776690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_lcmgr_intg.1566776690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.700666415 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 41223386700 ps |
| CPU time | 300.25 seconds |
| Started | Sep 09 06:26:47 PM UTC 24 |
| Finished | Sep 09 06:31:51 PM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=700666415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 15.flash_ctrl_mp_regions.700666415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.936837964 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 37116900 ps |
| CPU time | 218.09 seconds |
| Started | Sep 09 06:26:43 PM UTC 24 |
| Finished | Sep 09 06:30:25 PM UTC 24 |
| Peak memory | 274888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936837964 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.936837964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.2539814953 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 351008000 ps |
| CPU time | 271.76 seconds |
| Started | Sep 09 06:26:38 PM UTC 24 |
| Finished | Sep 09 06:31:14 PM UTC 24 |
| Peak memory | 273224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539814953 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2539814953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.3747928728 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 64878500 ps |
| CPU time | 23.04 seconds |
| Started | Sep 09 06:27:18 PM UTC 24 |
| Finished | Sep 09 06:27:43 PM UTC 24 |
| Peak memory | 269208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747928728 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.3747928728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.2373711377 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 1532277200 ps |
| CPU time | 1027.71 seconds |
| Started | Sep 09 06:26:36 PM UTC 24 |
| Finished | Sep 09 06:43:55 PM UTC 24 |
| Peak memory | 295436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373711377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.2373711377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.2041653274 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 111333400 ps |
| CPU time | 47.2 seconds |
| Started | Sep 09 06:27:34 PM UTC 24 |
| Finished | Sep 09 06:28:23 PM UTC 24 |
| Peak memory | 287712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041653274 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.2041653274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.3600264784 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 642326900 ps |
| CPU time | 103.03 seconds |
| Started | Sep 09 06:26:54 PM UTC 24 |
| Finished | Sep 09 06:28:39 PM UTC 24 |
| Peak memory | 303764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3600264784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.3600264784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.4092938719 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4206996600 ps |
| CPU time | 392.45 seconds |
| Started | Sep 09 06:27:06 PM UTC 24 |
| Finished | Sep 09 06:33:43 PM UTC 24 |
| Peak memory | 324504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092938719 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.4092938719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.3380607213 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 39171000 ps |
| CPU time | 62.22 seconds |
| Started | Sep 09 06:27:20 PM UTC 24 |
| Finished | Sep 09 06:28:25 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380607213 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.3380607213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.452387213 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 28855000 ps |
| CPU time | 57.83 seconds |
| Started | Sep 09 06:27:26 PM UTC 24 |
| Finished | Sep 09 06:28:26 PM UTC 24 |
| Peak memory | 287416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=452387213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ct rl_rw_evict_all_en.452387213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.3940134684 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 8278977000 ps |
| CPU time | 104.17 seconds |
| Started | Sep 09 06:27:56 PM UTC 24 |
| Finished | Sep 09 06:29:42 PM UTC 24 |
| Peak memory | 275100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940134684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3940134684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.3975966678 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 110070600 ps |
| CPU time | 119.36 seconds |
| Started | Sep 09 06:26:36 PM UTC 24 |
| Finished | Sep 09 06:28:38 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975966678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.3975966678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.1050864090 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1819515800 ps |
| CPU time | 148.21 seconds |
| Started | Sep 09 06:26:53 PM UTC 24 |
| Finished | Sep 09 06:29:23 PM UTC 24 |
| Peak memory | 275012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1050864090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.1050864090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.4283042162 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 75729800 ps |
| CPU time | 15.61 seconds |
| Started | Sep 09 06:30:25 PM UTC 24 |
| Finished | Sep 09 06:30:42 PM UTC 24 |
| Peak memory | 268908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283042162 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.4283042162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.4096693120 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 159551900 ps |
| CPU time | 24.82 seconds |
| Started | Sep 09 06:29:58 PM UTC 24 |
| Finished | Sep 09 06:30:25 PM UTC 24 |
| Peak memory | 294872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096693120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.4096693120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.4161165495 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 11098400 ps |
| CPU time | 26.09 seconds |
| Started | Sep 09 06:29:46 PM UTC 24 |
| Finished | Sep 09 06:30:14 PM UTC 24 |
| Peak memory | 285492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4161165495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ ctrl_disable.4161165495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.4087509667 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 10019526500 ps |
| CPU time | 110.55 seconds |
| Started | Sep 09 06:30:14 PM UTC 24 |
| Finished | Sep 09 06:32:07 PM UTC 24 |
| Peak memory | 340688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4087509667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.4087509667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.2261312658 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 26760400 ps |
| CPU time | 19.11 seconds |
| Started | Sep 09 06:30:13 PM UTC 24 |
| Finished | Sep 09 06:30:33 PM UTC 24 |
| Peak memory | 271008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2261312658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2261312658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.3910103317 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 80137793400 ps |
| CPU time | 1051.98 seconds |
| Started | Sep 09 06:28:30 PM UTC 24 |
| Finished | Sep 09 06:46:14 PM UTC 24 |
| Peak memory | 274984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910103317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res et.3910103317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.1741968709 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 744331500 ps |
| CPU time | 146.06 seconds |
| Started | Sep 09 06:29:18 PM UTC 24 |
| Finished | Sep 09 06:31:46 PM UTC 24 |
| Peak memory | 305844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741968709 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.1741968709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3562556841 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 29880521100 ps |
| CPU time | 163.65 seconds |
| Started | Sep 09 06:29:24 PM UTC 24 |
| Finished | Sep 09 06:32:10 PM UTC 24 |
| Peak memory | 303720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3562556841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_intr_rd_slow_flash.3562556841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.3860142540 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 1935186600 ps |
| CPU time | 89.51 seconds |
| Started | Sep 09 06:28:40 PM UTC 24 |
| Finished | Sep 09 06:30:11 PM UTC 24 |
| Peak memory | 270664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860142540 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3860142540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.1333261099 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 34668200 ps |
| CPU time | 25.63 seconds |
| Started | Sep 09 06:30:03 PM UTC 24 |
| Finished | Sep 09 06:30:29 PM UTC 24 |
| Peak memory | 271044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1333261099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_lcmgr_intg.1333261099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.1345529245 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 12902791300 ps |
| CPU time | 897.08 seconds |
| Started | Sep 09 06:28:39 PM UTC 24 |
| Finished | Sep 09 06:43:46 PM UTC 24 |
| Peak memory | 285140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1345529245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.1345529245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.2341295648 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 346624300 ps |
| CPU time | 183.53 seconds |
| Started | Sep 09 06:28:31 PM UTC 24 |
| Finished | Sep 09 06:31:37 PM UTC 24 |
| Peak memory | 270968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341295648 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.2341295648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.2160728956 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1491954300 ps |
| CPU time | 704.91 seconds |
| Started | Sep 09 06:28:27 PM UTC 24 |
| Finished | Sep 09 06:40:21 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160728956 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.2160728956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.3198617153 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 35531800 ps |
| CPU time | 25.1 seconds |
| Started | Sep 09 06:29:31 PM UTC 24 |
| Finished | Sep 09 06:29:57 PM UTC 24 |
| Peak memory | 274964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198617153 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.3198617153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.1989399766 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 688465700 ps |
| CPU time | 1150.97 seconds |
| Started | Sep 09 06:28:26 PM UTC 24 |
| Finished | Sep 09 06:47:49 PM UTC 24 |
| Peak memory | 293388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989399766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1989399766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.3848944310 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 495041400 ps |
| CPU time | 43.09 seconds |
| Started | Sep 09 06:29:43 PM UTC 24 |
| Finished | Sep 09 06:30:28 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848944310 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.3848944310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.3971446420 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 1852340900 ps |
| CPU time | 113.51 seconds |
| Started | Sep 09 06:28:44 PM UTC 24 |
| Finished | Sep 09 06:30:40 PM UTC 24 |
| Peak memory | 301748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3971446420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.3971446420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.1569377633 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 10558317800 ps |
| CPU time | 429.09 seconds |
| Started | Sep 09 06:29:11 PM UTC 24 |
| Finished | Sep 09 06:36:26 PM UTC 24 |
| Peak memory | 320128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569377633 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.1569377633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.1271541667 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 30024000 ps |
| CPU time | 55.79 seconds |
| Started | Sep 09 06:29:39 PM UTC 24 |
| Finished | Sep 09 06:30:37 PM UTC 24 |
| Peak memory | 287712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271541667 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.1271541667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.3361451694 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 60515000 ps |
| CPU time | 40.62 seconds |
| Started | Sep 09 06:29:42 PM UTC 24 |
| Finished | Sep 09 06:30:24 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3361451694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c trl_rw_evict_all_en.3361451694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3869377861 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1283593000 ps |
| CPU time | 70.08 seconds |
| Started | Sep 09 06:29:50 PM UTC 24 |
| Finished | Sep 09 06:31:02 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869377861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3869377861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.4201472561 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 100007900 ps |
| CPU time | 71.21 seconds |
| Started | Sep 09 06:28:25 PM UTC 24 |
| Finished | Sep 09 06:29:38 PM UTC 24 |
| Peak memory | 285192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201472561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.4201472561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.3255917959 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 12857842600 ps |
| CPU time | 144.6 seconds |
| Started | Sep 09 06:28:43 PM UTC 24 |
| Finished | Sep 09 06:31:10 PM UTC 24 |
| Peak memory | 275032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3255917959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.3255917959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.2647138140 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 132052100 ps |
| CPU time | 22.17 seconds |
| Started | Sep 09 06:32:04 PM UTC 24 |
| Finished | Sep 09 06:32:27 PM UTC 24 |
| Peak memory | 268932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647138140 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.2647138140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.2681059625 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 198923400 ps |
| CPU time | 20.65 seconds |
| Started | Sep 09 06:31:53 PM UTC 24 |
| Finished | Sep 09 06:32:14 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681059625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2681059625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3877690011 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 10036837300 ps |
| CPU time | 117.11 seconds |
| Started | Sep 09 06:32:03 PM UTC 24 |
| Finished | Sep 09 06:34:02 PM UTC 24 |
| Peak memory | 283296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3877690011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3877690011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.4782939 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 36300600 ps |
| CPU time | 24.51 seconds |
| Started | Sep 09 06:32:02 PM UTC 24 |
| Finished | Sep 09 06:32:28 PM UTC 24 |
| Peak memory | 275116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4782939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17. flash_ctrl_hw_read_seed_err.4782939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.2394736001 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 90155018700 ps |
| CPU time | 786.83 seconds |
| Started | Sep 09 06:30:35 PM UTC 24 |
| Finished | Sep 09 06:43:50 PM UTC 24 |
| Peak memory | 274732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394736001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_res et.2394736001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.585874212 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3121439800 ps |
| CPU time | 93.6 seconds |
| Started | Sep 09 06:30:30 PM UTC 24 |
| Finished | Sep 09 06:32:06 PM UTC 24 |
| Peak memory | 270684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585874212 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.585874212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.1734563691 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 4029875000 ps |
| CPU time | 185.15 seconds |
| Started | Sep 09 06:31:03 PM UTC 24 |
| Finished | Sep 09 06:34:12 PM UTC 24 |
| Peak memory | 305844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734563691 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.1734563691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2205865072 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 24315349600 ps |
| CPU time | 148.01 seconds |
| Started | Sep 09 06:31:06 PM UTC 24 |
| Finished | Sep 09 06:33:37 PM UTC 24 |
| Peak memory | 303720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2205865072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_intr_rd_slow_flash.2205865072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.1515131470 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2381817100 ps |
| CPU time | 75.45 seconds |
| Started | Sep 09 06:30:41 PM UTC 24 |
| Finished | Sep 09 06:31:58 PM UTC 24 |
| Peak memory | 270664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515131470 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1515131470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.804765876 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 14981500 ps |
| CPU time | 18.68 seconds |
| Started | Sep 09 06:31:59 PM UTC 24 |
| Finished | Sep 09 06:32:19 PM UTC 24 |
| Peak memory | 275124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=804765876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flas h_ctrl_lcmgr_intg.804765876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.3983704005 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 68680611800 ps |
| CPU time | 640.34 seconds |
| Started | Sep 09 06:30:38 PM UTC 24 |
| Finished | Sep 09 06:41:26 PM UTC 24 |
| Peak memory | 283088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3983704005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.3983704005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.1028388271 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 63157000 ps |
| CPU time | 186.46 seconds |
| Started | Sep 09 06:30:35 PM UTC 24 |
| Finished | Sep 09 06:33:44 PM UTC 24 |
| Peak memory | 271224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028388271 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.1028388271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.2004295225 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 4057489000 ps |
| CPU time | 772.65 seconds |
| Started | Sep 09 06:30:28 PM UTC 24 |
| Finished | Sep 09 06:43:30 PM UTC 24 |
| Peak memory | 275160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004295225 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.2004295225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.1001962077 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 60254200 ps |
| CPU time | 23.64 seconds |
| Started | Sep 09 06:31:08 PM UTC 24 |
| Finished | Sep 09 06:31:33 PM UTC 24 |
| Peak memory | 275000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001962077 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.1001962077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.2867396814 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 294469400 ps |
| CPU time | 805.28 seconds |
| Started | Sep 09 06:30:26 PM UTC 24 |
| Finished | Sep 09 06:44:00 PM UTC 24 |
| Peak memory | 291340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867396814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2867396814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.2566585227 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 69802100 ps |
| CPU time | 59.9 seconds |
| Started | Sep 09 06:31:34 PM UTC 24 |
| Finished | Sep 09 06:32:36 PM UTC 24 |
| Peak memory | 283324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566585227 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.2566585227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.3802820173 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1823520200 ps |
| CPU time | 125.13 seconds |
| Started | Sep 09 06:30:50 PM UTC 24 |
| Finished | Sep 09 06:32:58 PM UTC 24 |
| Peak memory | 301788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3802820173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.3802820173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.1363741229 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 14318440100 ps |
| CPU time | 417.09 seconds |
| Started | Sep 09 06:30:53 PM UTC 24 |
| Finished | Sep 09 06:37:55 PM UTC 24 |
| Peak memory | 320160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363741229 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.1363741229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.449129580 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 27030700 ps |
| CPU time | 46.35 seconds |
| Started | Sep 09 06:31:15 PM UTC 24 |
| Finished | Sep 09 06:32:03 PM UTC 24 |
| Peak memory | 285728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=449129580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ct rl_rw_evict_all_en.449129580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.4280837774 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 2318485400 ps |
| CPU time | 109.14 seconds |
| Started | Sep 09 06:31:47 PM UTC 24 |
| Finished | Sep 09 06:33:39 PM UTC 24 |
| Peak memory | 274784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280837774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.4280837774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.3993198529 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 65856800 ps |
| CPU time | 289.46 seconds |
| Started | Sep 09 06:30:25 PM UTC 24 |
| Finished | Sep 09 06:35:19 PM UTC 24 |
| Peak memory | 291532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993198529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.3993198529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.277548379 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 13610987300 ps |
| CPU time | 157.6 seconds |
| Started | Sep 09 06:30:43 PM UTC 24 |
| Finished | Sep 09 06:33:23 PM UTC 24 |
| Peak memory | 270936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =277548379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.277548379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.3126570512 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 29458200 ps |
| CPU time | 24.51 seconds |
| Started | Sep 09 06:33:50 PM UTC 24 |
| Finished | Sep 09 06:34:16 PM UTC 24 |
| Peak memory | 269236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126570512 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.3126570512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.1064734097 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 94518900 ps |
| CPU time | 28.02 seconds |
| Started | Sep 09 06:33:38 PM UTC 24 |
| Finished | Sep 09 06:34:07 PM UTC 24 |
| Peak memory | 284568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064734097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1064734097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.1694354698 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 97100800 ps |
| CPU time | 39.27 seconds |
| Started | Sep 09 06:33:29 PM UTC 24 |
| Finished | Sep 09 06:34:10 PM UTC 24 |
| Peak memory | 285296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1694354698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ ctrl_disable.1694354698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1704858117 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 10013146700 ps |
| CPU time | 269.51 seconds |
| Started | Sep 09 06:33:45 PM UTC 24 |
| Finished | Sep 09 06:38:18 PM UTC 24 |
| Peak memory | 332452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1704858117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1704858117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.3283201947 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 46298600 ps |
| CPU time | 23.46 seconds |
| Started | Sep 09 06:33:44 PM UTC 24 |
| Finished | Sep 09 06:34:09 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3283201947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.3283201947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.148096331 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 40120862300 ps |
| CPU time | 857.49 seconds |
| Started | Sep 09 06:32:17 PM UTC 24 |
| Finished | Sep 09 06:46:44 PM UTC 24 |
| Peak memory | 274996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148096331 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_reset.148096331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.910900822 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2794804700 ps |
| CPU time | 79.14 seconds |
| Started | Sep 09 06:32:16 PM UTC 24 |
| Finished | Sep 09 06:33:36 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910900822 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.910900822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.4238767809 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1485381900 ps |
| CPU time | 156.58 seconds |
| Started | Sep 09 06:32:57 PM UTC 24 |
| Finished | Sep 09 06:35:37 PM UTC 24 |
| Peak memory | 305844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238767809 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.4238767809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.4106600101 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 24065773500 ps |
| CPU time | 275.15 seconds |
| Started | Sep 09 06:32:59 PM UTC 24 |
| Finished | Sep 09 06:37:38 PM UTC 24 |
| Peak memory | 303876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4106600101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_intr_rd_slow_flash.4106600101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.385109753 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1568973000 ps |
| CPU time | 53.93 seconds |
| Started | Sep 09 06:32:28 PM UTC 24 |
| Finished | Sep 09 06:33:23 PM UTC 24 |
| Peak memory | 274756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385109753 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.385109753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.1209389595 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 16039800 ps |
| CPU time | 25.41 seconds |
| Started | Sep 09 06:33:40 PM UTC 24 |
| Finished | Sep 09 06:34:06 PM UTC 24 |
| Peak memory | 273092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1209389595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_lcmgr_intg.1209389595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.797494618 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 42153071400 ps |
| CPU time | 349.81 seconds |
| Started | Sep 09 06:32:22 PM UTC 24 |
| Finished | Sep 09 06:38:16 PM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=797494618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_mp_regions.797494618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.3732584553 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 4905033600 ps |
| CPU time | 605.73 seconds |
| Started | Sep 09 06:32:10 PM UTC 24 |
| Finished | Sep 09 06:42:23 PM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732584553 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3732584553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.3993969940 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 44300500 ps |
| CPU time | 28.57 seconds |
| Started | Sep 09 06:32:59 PM UTC 24 |
| Finished | Sep 09 06:33:29 PM UTC 24 |
| Peak memory | 275200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993969940 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.3993969940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.150658383 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 275862300 ps |
| CPU time | 400.19 seconds |
| Started | Sep 09 06:32:07 PM UTC 24 |
| Finished | Sep 09 06:38:52 PM UTC 24 |
| Peak memory | 291344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150658383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.150658383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.423304523 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 66869900 ps |
| CPU time | 39.27 seconds |
| Started | Sep 09 06:33:24 PM UTC 24 |
| Finished | Sep 09 06:34:05 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423304523 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.423304523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.464781944 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2394654300 ps |
| CPU time | 102.24 seconds |
| Started | Sep 09 06:32:36 PM UTC 24 |
| Finished | Sep 09 06:34:20 PM UTC 24 |
| Peak memory | 301784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=464781944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.464781944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.2574018814 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 3018348800 ps |
| CPU time | 370.17 seconds |
| Started | Sep 09 06:32:45 PM UTC 24 |
| Finished | Sep 09 06:39:01 PM UTC 24 |
| Peak memory | 330692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574018814 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.2574018814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.1590793942 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 28281500 ps |
| CPU time | 43.59 seconds |
| Started | Sep 09 06:33:05 PM UTC 24 |
| Finished | Sep 09 06:33:50 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590793942 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.1590793942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.2462772387 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 86951200 ps |
| CPU time | 35.61 seconds |
| Started | Sep 09 06:33:24 PM UTC 24 |
| Finished | Sep 09 06:34:01 PM UTC 24 |
| Peak memory | 287712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2462772387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c trl_rw_evict_all_en.2462772387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.4226518216 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 4176400100 ps |
| CPU time | 67.21 seconds |
| Started | Sep 09 06:33:38 PM UTC 24 |
| Finished | Sep 09 06:34:47 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226518216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.4226518216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.2606362728 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 24710400 ps |
| CPU time | 218.35 seconds |
| Started | Sep 09 06:32:06 PM UTC 24 |
| Finished | Sep 09 06:35:48 PM UTC 24 |
| Peak memory | 289292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606362728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2606362728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.3696576997 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 31403077300 ps |
| CPU time | 180.94 seconds |
| Started | Sep 09 06:32:29 PM UTC 24 |
| Finished | Sep 09 06:35:33 PM UTC 24 |
| Peak memory | 270932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3696576997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.3696576997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.1296538512 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 48608400 ps |
| CPU time | 24.07 seconds |
| Started | Sep 09 06:36:02 PM UTC 24 |
| Finished | Sep 09 06:36:27 PM UTC 24 |
| Peak memory | 270968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296538512 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.1296538512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.523232284 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 21246400 ps |
| CPU time | 23.07 seconds |
| Started | Sep 09 06:35:41 PM UTC 24 |
| Finished | Sep 09 06:36:05 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523232284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.523232284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2493395213 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 10038926900 ps |
| CPU time | 52.02 seconds |
| Started | Sep 09 06:36:00 PM UTC 24 |
| Finished | Sep 09 06:36:53 PM UTC 24 |
| Peak memory | 275160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2493395213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2493395213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.1268856243 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 15488600 ps |
| CPU time | 17.33 seconds |
| Started | Sep 09 06:35:57 PM UTC 24 |
| Finished | Sep 09 06:36:15 PM UTC 24 |
| Peak memory | 268984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1268856243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1268856243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.966888809 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 42030014400 ps |
| CPU time | 131.78 seconds |
| Started | Sep 09 06:34:04 PM UTC 24 |
| Finished | Sep 09 06:36:18 PM UTC 24 |
| Peak memory | 272732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966888809 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.966888809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1124269741 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 504738100 ps |
| CPU time | 143.35 seconds |
| Started | Sep 09 06:34:22 PM UTC 24 |
| Finished | Sep 09 06:36:48 PM UTC 24 |
| Peak memory | 305840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124269741 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.1124269741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.792058028 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 12759496700 ps |
| CPU time | 341.04 seconds |
| Started | Sep 09 06:34:48 PM UTC 24 |
| Finished | Sep 09 06:40:33 PM UTC 24 |
| Peak memory | 301672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=792058028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 19.flash_ctrl_intr_rd_slow_flash.792058028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.448339165 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 39008492000 ps |
| CPU time | 87.96 seconds |
| Started | Sep 09 06:34:09 PM UTC 24 |
| Finished | Sep 09 06:35:40 PM UTC 24 |
| Peak memory | 270668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448339165 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.448339165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.3527228012 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 46062500 ps |
| CPU time | 25.07 seconds |
| Started | Sep 09 06:35:49 PM UTC 24 |
| Finished | Sep 09 06:36:16 PM UTC 24 |
| Peak memory | 271328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3527228012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_lcmgr_intg.3527228012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.838351725 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 22124015200 ps |
| CPU time | 396.99 seconds |
| Started | Sep 09 06:34:08 PM UTC 24 |
| Finished | Sep 09 06:40:51 PM UTC 24 |
| Peak memory | 283328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=838351725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 19.flash_ctrl_mp_regions.838351725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.1508362157 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 158047400 ps |
| CPU time | 135.71 seconds |
| Started | Sep 09 06:34:07 PM UTC 24 |
| Finished | Sep 09 06:36:25 PM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508362157 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.1508362157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.2090217066 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 4932450000 ps |
| CPU time | 305.91 seconds |
| Started | Sep 09 06:34:02 PM UTC 24 |
| Finished | Sep 09 06:39:11 PM UTC 24 |
| Peak memory | 274948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090217066 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2090217066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.1000333822 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 130899100 ps |
| CPU time | 328.08 seconds |
| Started | Sep 09 06:33:58 PM UTC 24 |
| Finished | Sep 09 06:39:31 PM UTC 24 |
| Peak memory | 291340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000333822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1000333822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.4205336616 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 63573900 ps |
| CPU time | 43.17 seconds |
| Started | Sep 09 06:35:26 PM UTC 24 |
| Finished | Sep 09 06:36:11 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205336616 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.4205336616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.1098804656 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 562992100 ps |
| CPU time | 150.12 seconds |
| Started | Sep 09 06:34:12 PM UTC 24 |
| Finished | Sep 09 06:36:45 PM UTC 24 |
| Peak memory | 291528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1098804656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.1098804656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.3221510094 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3973605000 ps |
| CPU time | 460.16 seconds |
| Started | Sep 09 06:34:16 PM UTC 24 |
| Finished | Sep 09 06:42:03 PM UTC 24 |
| Peak memory | 330300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221510094 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.3221510094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.688651550 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 235889700 ps |
| CPU time | 47.29 seconds |
| Started | Sep 09 06:35:20 PM UTC 24 |
| Finished | Sep 09 06:36:09 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688651550 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.688651550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.440390972 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 47020200 ps |
| CPU time | 36.56 seconds |
| Started | Sep 09 06:35:21 PM UTC 24 |
| Finished | Sep 09 06:35:59 PM UTC 24 |
| Peak memory | 285336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=440390972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ct rl_rw_evict_all_en.440390972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.2865093595 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3350340400 ps |
| CPU time | 85.54 seconds |
| Started | Sep 09 06:35:38 PM UTC 24 |
| Finished | Sep 09 06:37:05 PM UTC 24 |
| Peak memory | 272736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865093595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.2865093595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.3437606069 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 93588900 ps |
| CPU time | 134.41 seconds |
| Started | Sep 09 06:33:51 PM UTC 24 |
| Finished | Sep 09 06:36:08 PM UTC 24 |
| Peak memory | 277312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437606069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3437606069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.1521945463 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1892148900 ps |
| CPU time | 120.43 seconds |
| Started | Sep 09 06:34:11 PM UTC 24 |
| Finished | Sep 09 06:36:14 PM UTC 24 |
| Peak memory | 270940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1521945463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.1521945463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.4280399723 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 22787900 ps |
| CPU time | 19.51 seconds |
| Started | Sep 09 05:45:07 PM UTC 24 |
| Finished | Sep 09 05:45:28 PM UTC 24 |
| Peak memory | 273348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=4280399723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.4280399723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.540518097 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 118296200 ps |
| CPU time | 18.82 seconds |
| Started | Sep 09 05:45:46 PM UTC 24 |
| Finished | Sep 09 05:46:06 PM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540518097 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.540518097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.3087455357 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 37659600 ps |
| CPU time | 26.95 seconds |
| Started | Sep 09 05:45:19 PM UTC 24 |
| Finished | Sep 09 05:45:47 PM UTC 24 |
| Peak memory | 275256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087455357 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.3087455357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.4259215925 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 56734600 ps |
| CPU time | 19.86 seconds |
| Started | Sep 09 05:44:46 PM UTC 24 |
| Finished | Sep 09 05:45:07 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259215925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.4259215925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.227495958 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3281737100 ps |
| CPU time | 277.23 seconds |
| Started | Sep 09 05:43:18 PM UTC 24 |
| Finished | Sep 09 05:47:59 PM UTC 24 |
| Peak memory | 289456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=227495958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.flash_ctrl_derr_detect.227495958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3817247549 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 26795900 ps |
| CPU time | 33.78 seconds |
| Started | Sep 09 05:44:24 PM UTC 24 |
| Finished | Sep 09 05:45:00 PM UTC 24 |
| Peak memory | 285356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3817247549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c trl_disable.3817247549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.980328821 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 5504250900 ps |
| CPU time | 645.6 seconds |
| Started | Sep 09 05:41:02 PM UTC 24 |
| Finished | Sep 09 05:51:56 PM UTC 24 |
| Peak memory | 274908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980328821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.980328821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.3437444714 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 7475256100 ps |
| CPU time | 3189.57 seconds |
| Started | Sep 09 05:41:38 PM UTC 24 |
| Finished | Sep 09 06:35:20 PM UTC 24 |
| Peak memory | 275644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437444714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.3437444714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.3330095429 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 691100100 ps |
| CPU time | 3433.98 seconds |
| Started | Sep 09 05:41:37 PM UTC 24 |
| Finished | Sep 09 06:39:27 PM UTC 24 |
| Peak memory | 277748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33 30095429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _error_prog_type.3330095429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.55109980 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 545301200 ps |
| CPU time | 1049.29 seconds |
| Started | Sep 09 05:41:37 PM UTC 24 |
| Finished | Sep 09 05:59:18 PM UTC 24 |
| Peak memory | 285148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55109980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/fla sh_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.55109980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.8342506 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 10026941900 ps |
| CPU time | 33.02 seconds |
| Started | Sep 09 05:41:32 PM UTC 24 |
| Finished | Sep 09 05:42:07 PM UTC 24 |
| Peak memory | 272904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83 42506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.8342506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.4065995921 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1304843200 ps |
| CPU time | 49.43 seconds |
| Started | Sep 09 05:45:07 PM UTC 24 |
| Finished | Sep 09 05:45:58 PM UTC 24 |
| Peak memory | 275048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065995 921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_f s_sup.4065995921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.3285640424 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 332042887700 ps |
| CPU time | 2618 seconds |
| Started | Sep 09 05:41:35 PM UTC 24 |
| Finished | Sep 09 06:25:43 PM UTC 24 |
| Peak memory | 277696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285640424 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.3285640424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.3782333650 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 27170600 ps |
| CPU time | 31.92 seconds |
| Started | Sep 09 05:45:42 PM UTC 24 |
| Finished | Sep 09 05:46:15 PM UTC 24 |
| Peak memory | 287360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378233365 0 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ho st_addr_infection.3782333650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.4064335948 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 91033800 ps |
| CPU time | 110.84 seconds |
| Started | Sep 09 05:40:51 PM UTC 24 |
| Finished | Sep 09 05:42:44 PM UTC 24 |
| Peak memory | 272896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064335948 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.4064335948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.368733333 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 10071181200 ps |
| CPU time | 69.04 seconds |
| Started | Sep 09 05:45:40 PM UTC 24 |
| Finished | Sep 09 05:46:50 PM UTC 24 |
| Peak memory | 279276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=368733333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.368733333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3068778074 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 206975200 ps |
| CPU time | 25.13 seconds |
| Started | Sep 09 05:45:33 PM UTC 24 |
| Finished | Sep 09 05:46:00 PM UTC 24 |
| Peak memory | 275516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3068778074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3068778074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1052345208 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 543581407800 ps |
| CPU time | 2105.34 seconds |
| Started | Sep 09 05:41:10 PM UTC 24 |
| Finished | Sep 09 06:16:38 PM UTC 24 |
| Peak memory | 277652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052345208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.1052345208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.3315702952 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 40120284400 ps |
| CPU time | 749.36 seconds |
| Started | Sep 09 05:41:15 PM UTC 24 |
| Finished | Sep 09 05:53:52 PM UTC 24 |
| Peak memory | 274752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315702952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.3315702952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.2718849348 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 29819611200 ps |
| CPU time | 159.69 seconds |
| Started | Sep 09 05:41:02 PM UTC 24 |
| Finished | Sep 09 05:43:45 PM UTC 24 |
| Peak memory | 272728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718849348 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.2718849348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.525307942 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 16333814500 ps |
| CPU time | 603.3 seconds |
| Started | Sep 09 05:43:23 PM UTC 24 |
| Finished | Sep 09 05:53:35 PM UTC 24 |
| Peak memory | 347108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=525307942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integrity.525307942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3391729979 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 27627393200 ps |
| CPU time | 226.64 seconds |
| Started | Sep 09 05:43:41 PM UTC 24 |
| Finished | Sep 09 05:47:31 PM UTC 24 |
| Peak memory | 301660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3391729979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_intr_rd_slow_flash.3391729979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.2113429812 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2404681200 ps |
| CPU time | 84.49 seconds |
| Started | Sep 09 05:43:40 PM UTC 24 |
| Finished | Sep 09 05:45:06 PM UTC 24 |
| Peak memory | 275008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113429812 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.2113429812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1244170991 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 207721557700 ps |
| CPU time | 357.63 seconds |
| Started | Sep 09 05:43:46 PM UTC 24 |
| Finished | Sep 09 05:49:48 PM UTC 24 |
| Peak memory | 270976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244170991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1244170991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.3527823580 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1536205900 ps |
| CPU time | 82.3 seconds |
| Started | Sep 09 05:41:40 PM UTC 24 |
| Finished | Sep 09 05:43:04 PM UTC 24 |
| Peak memory | 272700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527823580 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3527823580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3550011449 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 29021900 ps |
| CPU time | 16.59 seconds |
| Started | Sep 09 05:45:33 PM UTC 24 |
| Finished | Sep 09 05:45:51 PM UTC 24 |
| Peak memory | 270976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3550011449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_lcmgr_intg.3550011449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.453480753 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1402141600 ps |
| CPU time | 107.67 seconds |
| Started | Sep 09 05:41:42 PM UTC 24 |
| Finished | Sep 09 05:43:32 PM UTC 24 |
| Peak memory | 270632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453480753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.453480753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.3546643645 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 26005636200 ps |
| CPU time | 279.93 seconds |
| Started | Sep 09 05:41:31 PM UTC 24 |
| Finished | Sep 09 05:46:15 PM UTC 24 |
| Peak memory | 283332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3546643645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.3546643645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.517451295 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 80202100 ps |
| CPU time | 182.62 seconds |
| Started | Sep 09 05:41:25 PM UTC 24 |
| Finished | Sep 09 05:44:30 PM UTC 24 |
| Peak memory | 271304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517451295 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.517451295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.3950700824 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3771206100 ps |
| CPU time | 129.49 seconds |
| Started | Sep 09 05:43:19 PM UTC 24 |
| Finished | Sep 09 05:45:31 PM UTC 24 |
| Peak memory | 291524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3950700824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.3950700824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2160378239 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 36525400 ps |
| CPU time | 25.23 seconds |
| Started | Sep 09 05:45:13 PM UTC 24 |
| Finished | Sep 09 05:45:40 PM UTC 24 |
| Peak memory | 292960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160378239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.2160378239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1014943127 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 773559100 ps |
| CPU time | 468.59 seconds |
| Started | Sep 09 05:40:53 PM UTC 24 |
| Finished | Sep 09 05:48:48 PM UTC 24 |
| Peak memory | 274956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014943127 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1014943127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.3004476445 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 35798000 ps |
| CPU time | 24.26 seconds |
| Started | Sep 09 05:43:58 PM UTC 24 |
| Finished | Sep 09 05:44:23 PM UTC 24 |
| Peak memory | 274972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004476445 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.3004476445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.1774167167 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 266259600 ps |
| CPU time | 815.91 seconds |
| Started | Sep 09 05:40:49 PM UTC 24 |
| Finished | Sep 09 05:54:34 PM UTC 24 |
| Peak memory | 291592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774167167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1774167167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1438490607 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 268303900 ps |
| CPU time | 120.35 seconds |
| Started | Sep 09 05:40:52 PM UTC 24 |
| Finished | Sep 09 05:42:55 PM UTC 24 |
| Peak memory | 272900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438490607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1438490607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3436437161 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 70916200 ps |
| CPU time | 36.46 seconds |
| Started | Sep 09 05:45:01 PM UTC 24 |
| Finished | Sep 09 05:45:38 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343643716 1 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.3436437161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.3106270190 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 61418800 ps |
| CPU time | 46.77 seconds |
| Started | Sep 09 05:44:23 PM UTC 24 |
| Finished | Sep 09 05:45:12 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106270190 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.3106270190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.2659766682 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 26613000 ps |
| CPU time | 43.02 seconds |
| Started | Sep 09 05:42:56 PM UTC 24 |
| Finished | Sep 09 05:43:40 PM UTC 24 |
| Peak memory | 275124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2659766682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_read_word_sweep_derr.2659766682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3747994986 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 44300400 ps |
| CPU time | 41.9 seconds |
| Started | Sep 09 05:42:14 PM UTC 24 |
| Finished | Sep 09 05:42:58 PM UTC 24 |
| Peak memory | 275120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747994986 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.3747994986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2258963418 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 62830090700 ps |
| CPU time | 969.65 seconds |
| Started | Sep 09 05:45:29 PM UTC 24 |
| Finished | Sep 09 06:01:49 PM UTC 24 |
| Peak memory | 299636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2258963418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. flash_ctrl_rma_err.2258963418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.217989448 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1365721400 ps |
| CPU time | 142.57 seconds |
| Started | Sep 09 05:42:01 PM UTC 24 |
| Finished | Sep 09 05:44:26 PM UTC 24 |
| Peak memory | 291648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=217989448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.217989448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.2607758581 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2494048100 ps |
| CPU time | 169.98 seconds |
| Started | Sep 09 05:42:59 PM UTC 24 |
| Finished | Sep 09 05:45:52 PM UTC 24 |
| Peak memory | 291532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607758581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.2607758581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.2371403695 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4869533400 ps |
| CPU time | 133.54 seconds |
| Started | Sep 09 05:42:22 PM UTC 24 |
| Finished | Sep 09 05:44:38 PM UTC 24 |
| Peak memory | 291528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2371403695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash _ctrl_ro_serr.2371403695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.1348398604 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 16923558500 ps |
| CPU time | 469.66 seconds |
| Started | Sep 09 05:42:08 PM UTC 24 |
| Finished | Sep 09 05:50:03 PM UTC 24 |
| Peak memory | 320428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348398604 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.1348398604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.10237805 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 28175400 ps |
| CPU time | 39.55 seconds |
| Started | Sep 09 05:44:04 PM UTC 24 |
| Finished | Sep 09 05:44:45 PM UTC 24 |
| Peak memory | 287452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10237805 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict.10237805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.2182496236 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 32418900 ps |
| CPU time | 39.2 seconds |
| Started | Sep 09 05:44:19 PM UTC 24 |
| Finished | Sep 09 05:45:00 PM UTC 24 |
| Peak memory | 287428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2182496236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_rw_evict_all_en.2182496236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3332433741 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2116628500 ps |
| CPU time | 196.38 seconds |
| Started | Sep 09 05:42:33 PM UTC 24 |
| Finished | Sep 09 05:45:53 PM UTC 24 |
| Peak memory | 305840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3332433741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.3332433741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.4178193890 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 14842000400 ps |
| CPU time | 126.13 seconds |
| Started | Sep 09 05:44:31 PM UTC 24 |
| Finished | Sep 09 05:46:39 PM UTC 24 |
| Peak memory | 270688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178193890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.4178193890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.1579818407 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 4483922600 ps |
| CPU time | 136.73 seconds |
| Started | Sep 09 05:42:47 PM UTC 24 |
| Finished | Sep 09 05:45:06 PM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157 9818407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ser r_address.1579818407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3059533894 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1441513500 ps |
| CPU time | 95.17 seconds |
| Started | Sep 09 05:42:46 PM UTC 24 |
| Finished | Sep 09 05:44:23 PM UTC 24 |
| Peak memory | 287428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30 59533894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se rr_counter.3059533894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.668741884 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 33871500 ps |
| CPU time | 295.35 seconds |
| Started | Sep 09 05:40:46 PM UTC 24 |
| Finished | Sep 09 05:45:45 PM UTC 24 |
| Peak memory | 291592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668741884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.668741884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.1572623676 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 22168700 ps |
| CPU time | 35.87 seconds |
| Started | Sep 09 05:40:47 PM UTC 24 |
| Finished | Sep 09 05:41:24 PM UTC 24 |
| Peak memory | 270616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572623676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1572623676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.574222222 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 856673500 ps |
| CPU time | 1494.67 seconds |
| Started | Sep 09 05:44:39 PM UTC 24 |
| Finished | Sep 09 06:09:50 PM UTC 24 |
| Peak memory | 303832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574222222 -assert nopostproc +UVM_TESTNA ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.574222222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.349387670 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 43468800 ps |
| CPU time | 48.04 seconds |
| Started | Sep 09 05:40:50 PM UTC 24 |
| Finished | Sep 09 05:41:40 PM UTC 24 |
| Peak memory | 270612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349387670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.349387670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1105906448 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2231315000 ps |
| CPU time | 200.59 seconds |
| Started | Sep 09 05:41:42 PM UTC 24 |
| Finished | Sep 09 05:45:06 PM UTC 24 |
| Peak memory | 271240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1105906448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.1105906448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3011161323 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 43721100 ps |
| CPU time | 16.39 seconds |
| Started | Sep 09 05:45:01 PM UTC 24 |
| Finished | Sep 09 05:45:18 PM UTC 24 |
| Peak memory | 271332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011161323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_wr_intg.3011161323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.764525307 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 23829400 ps |
| CPU time | 23.26 seconds |
| Started | Sep 09 06:36:28 PM UTC 24 |
| Finished | Sep 09 06:36:53 PM UTC 24 |
| Peak memory | 268920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764525307 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.764525307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.713922335 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 16322700 ps |
| CPU time | 23.29 seconds |
| Started | Sep 09 06:36:26 PM UTC 24 |
| Finished | Sep 09 06:36:51 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713922335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.713922335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.1790071999 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 61983600 ps |
| CPU time | 26.67 seconds |
| Started | Sep 09 06:36:19 PM UTC 24 |
| Finished | Sep 09 06:36:47 PM UTC 24 |
| Peak memory | 285296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1790071999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ ctrl_disable.1790071999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.345069187 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4886995400 ps |
| CPU time | 133.31 seconds |
| Started | Sep 09 06:36:08 PM UTC 24 |
| Finished | Sep 09 06:38:24 PM UTC 24 |
| Peak memory | 270680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345069187 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.345069187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.1516335510 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1585473100 ps |
| CPU time | 191.53 seconds |
| Started | Sep 09 06:36:09 PM UTC 24 |
| Finished | Sep 09 06:39:24 PM UTC 24 |
| Peak memory | 293836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516335510 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.1516335510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2797814222 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 5803727600 ps |
| CPU time | 169.35 seconds |
| Started | Sep 09 06:36:12 PM UTC 24 |
| Finished | Sep 09 06:39:04 PM UTC 24 |
| Peak memory | 303716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2797814222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.flash_ctrl_intr_rd_slow_flash.2797814222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.1491237641 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 145265700 ps |
| CPU time | 225.41 seconds |
| Started | Sep 09 06:36:09 PM UTC 24 |
| Finished | Sep 09 06:39:58 PM UTC 24 |
| Peak memory | 270956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491237641 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.1491237641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.2699390747 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 212877500 ps |
| CPU time | 24.93 seconds |
| Started | Sep 09 06:36:15 PM UTC 24 |
| Finished | Sep 09 06:36:41 PM UTC 24 |
| Peak memory | 270936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699390747 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.2699390747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.2915399455 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 30016100 ps |
| CPU time | 55.4 seconds |
| Started | Sep 09 06:36:16 PM UTC 24 |
| Finished | Sep 09 06:37:13 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915399455 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.2915399455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.2204296001 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 3722654700 ps |
| CPU time | 72.01 seconds |
| Started | Sep 09 06:36:26 PM UTC 24 |
| Finished | Sep 09 06:37:40 PM UTC 24 |
| Peak memory | 275044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204296001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.2204296001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.3800202171 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 73494700 ps |
| CPU time | 268.01 seconds |
| Started | Sep 09 06:36:06 PM UTC 24 |
| Finished | Sep 09 06:40:38 PM UTC 24 |
| Peak memory | 289292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800202171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.3800202171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.4211590052 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 37463500 ps |
| CPU time | 24.28 seconds |
| Started | Sep 09 06:37:14 PM UTC 24 |
| Finished | Sep 09 06:37:39 PM UTC 24 |
| Peak memory | 268916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211590052 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.4211590052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.3257739665 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 17249900 ps |
| CPU time | 27.28 seconds |
| Started | Sep 09 06:37:12 PM UTC 24 |
| Finished | Sep 09 06:37:40 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257739665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.3257739665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.1607969094 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 20730900 ps |
| CPU time | 34.19 seconds |
| Started | Sep 09 06:37:06 PM UTC 24 |
| Finished | Sep 09 06:37:42 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1607969094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ ctrl_disable.1607969094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.3809949883 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 14733236400 ps |
| CPU time | 118.38 seconds |
| Started | Sep 09 06:36:42 PM UTC 24 |
| Finished | Sep 09 06:38:42 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809949883 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.3809949883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.2535346049 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2908973000 ps |
| CPU time | 195.49 seconds |
| Started | Sep 09 06:36:48 PM UTC 24 |
| Finished | Sep 09 06:40:07 PM UTC 24 |
| Peak memory | 305840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535346049 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.2535346049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.889672268 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 13607973200 ps |
| CPU time | 313.05 seconds |
| Started | Sep 09 06:36:49 PM UTC 24 |
| Finished | Sep 09 06:42:06 PM UTC 24 |
| Peak memory | 301676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=889672268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 21.flash_ctrl_intr_rd_slow_flash.889672268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.2833690423 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 155890800 ps |
| CPU time | 163.78 seconds |
| Started | Sep 09 06:36:46 PM UTC 24 |
| Finished | Sep 09 06:39:32 PM UTC 24 |
| Peak memory | 274892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833690423 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.2833690423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.2000411376 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 81441400 ps |
| CPU time | 17.48 seconds |
| Started | Sep 09 06:36:52 PM UTC 24 |
| Finished | Sep 09 06:37:11 PM UTC 24 |
| Peak memory | 268792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000411376 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.2000411376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.1119091590 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 382669200 ps |
| CPU time | 37.66 seconds |
| Started | Sep 09 06:36:54 PM UTC 24 |
| Finished | Sep 09 06:37:33 PM UTC 24 |
| Peak memory | 287452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119091590 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.1119091590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.3501317576 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 142342700 ps |
| CPU time | 50.87 seconds |
| Started | Sep 09 06:36:54 PM UTC 24 |
| Finished | Sep 09 06:37:47 PM UTC 24 |
| Peak memory | 285308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3501317576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_c trl_rw_evict_all_en.3501317576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.413342313 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 992104100 ps |
| CPU time | 85.57 seconds |
| Started | Sep 09 06:37:07 PM UTC 24 |
| Finished | Sep 09 06:38:34 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413342313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.413342313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.3891246746 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 105413600 ps |
| CPU time | 220.77 seconds |
| Started | Sep 09 06:36:40 PM UTC 24 |
| Finished | Sep 09 06:40:24 PM UTC 24 |
| Peak memory | 289548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891246746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.3891246746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3671820359 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 97952800 ps |
| CPU time | 16.79 seconds |
| Started | Sep 09 06:38:19 PM UTC 24 |
| Finished | Sep 09 06:38:37 PM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671820359 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.3671820359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.4223084901 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 40182500 ps |
| CPU time | 25.81 seconds |
| Started | Sep 09 06:38:18 PM UTC 24 |
| Finished | Sep 09 06:38:45 PM UTC 24 |
| Peak memory | 294612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223084901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.4223084901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.4002043462 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 10488186400 ps |
| CPU time | 120.07 seconds |
| Started | Sep 09 06:37:39 PM UTC 24 |
| Finished | Sep 09 06:39:42 PM UTC 24 |
| Peak memory | 270688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002043462 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.4002043462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.4197057316 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 4901195000 ps |
| CPU time | 186.06 seconds |
| Started | Sep 09 06:37:40 PM UTC 24 |
| Finished | Sep 09 06:40:49 PM UTC 24 |
| Peak memory | 303820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197057316 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.4197057316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.3938537779 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 5782340900 ps |
| CPU time | 163.49 seconds |
| Started | Sep 09 06:37:42 PM UTC 24 |
| Finished | Sep 09 06:40:28 PM UTC 24 |
| Peak memory | 304008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3938537779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 22.flash_ctrl_intr_rd_slow_flash.3938537779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.1904818378 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 125762200 ps |
| CPU time | 188.06 seconds |
| Started | Sep 09 06:37:40 PM UTC 24 |
| Finished | Sep 09 06:40:51 PM UTC 24 |
| Peak memory | 275320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904818378 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.1904818378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3113639395 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 75258700 ps |
| CPU time | 20.87 seconds |
| Started | Sep 09 06:37:43 PM UTC 24 |
| Finished | Sep 09 06:38:05 PM UTC 24 |
| Peak memory | 270928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113639395 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.3113639395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.2241261867 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 39758700 ps |
| CPU time | 52.73 seconds |
| Started | Sep 09 06:37:45 PM UTC 24 |
| Finished | Sep 09 06:38:39 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241261867 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.2241261867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.3222002842 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 273051200 ps |
| CPU time | 50.5 seconds |
| Started | Sep 09 06:37:48 PM UTC 24 |
| Finished | Sep 09 06:38:40 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3222002842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_c trl_rw_evict_all_en.3222002842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.1721932290 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 46214900 ps |
| CPU time | 167.52 seconds |
| Started | Sep 09 06:37:34 PM UTC 24 |
| Finished | Sep 09 06:40:24 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721932290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1721932290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.536793393 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 62566800 ps |
| CPU time | 25.75 seconds |
| Started | Sep 09 06:38:54 PM UTC 24 |
| Finished | Sep 09 06:39:21 PM UTC 24 |
| Peak memory | 269256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536793393 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.536793393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.1810389933 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 28292900 ps |
| CPU time | 19.84 seconds |
| Started | Sep 09 06:38:53 PM UTC 24 |
| Finished | Sep 09 06:39:14 PM UTC 24 |
| Peak memory | 294676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810389933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1810389933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.2343420592 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 10755800 ps |
| CPU time | 33.52 seconds |
| Started | Sep 09 06:38:43 PM UTC 24 |
| Finished | Sep 09 06:39:18 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2343420592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ ctrl_disable.2343420592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.2728364517 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 4446070200 ps |
| CPU time | 188.2 seconds |
| Started | Sep 09 06:38:31 PM UTC 24 |
| Finished | Sep 09 06:41:43 PM UTC 24 |
| Peak memory | 274784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728364517 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.2728364517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.3348663455 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 13225243000 ps |
| CPU time | 241.18 seconds |
| Started | Sep 09 06:38:34 PM UTC 24 |
| Finished | Sep 09 06:42:39 PM UTC 24 |
| Peak memory | 293812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348663455 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.3348663455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3264660998 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 26123633200 ps |
| CPU time | 161.91 seconds |
| Started | Sep 09 06:38:36 PM UTC 24 |
| Finished | Sep 09 06:41:20 PM UTC 24 |
| Peak memory | 303712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3264660998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.flash_ctrl_intr_rd_slow_flash.3264660998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.1742658244 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 150092500 ps |
| CPU time | 187.52 seconds |
| Started | Sep 09 06:38:32 PM UTC 24 |
| Finished | Sep 09 06:41:43 PM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742658244 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.1742658244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.1944249518 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 58009700 ps |
| CPU time | 25.64 seconds |
| Started | Sep 09 06:38:38 PM UTC 24 |
| Finished | Sep 09 06:39:05 PM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944249518 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.1944249518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.3928448543 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 27409600 ps |
| CPU time | 40.48 seconds |
| Started | Sep 09 06:38:40 PM UTC 24 |
| Finished | Sep 09 06:39:22 PM UTC 24 |
| Peak memory | 283328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928448543 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.3928448543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.1779756305 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 132423200 ps |
| CPU time | 54.24 seconds |
| Started | Sep 09 06:38:41 PM UTC 24 |
| Finished | Sep 09 06:39:37 PM UTC 24 |
| Peak memory | 285696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1779756305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c trl_rw_evict_all_en.1779756305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.1932287064 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2303651000 ps |
| CPU time | 71.31 seconds |
| Started | Sep 09 06:38:45 PM UTC 24 |
| Finished | Sep 09 06:39:59 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932287064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1932287064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.833092773 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 47948700 ps |
| CPU time | 63.86 seconds |
| Started | Sep 09 06:38:25 PM UTC 24 |
| Finished | Sep 09 06:39:31 PM UTC 24 |
| Peak memory | 285196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833092773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.833092773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.733154617 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 50174800 ps |
| CPU time | 23.21 seconds |
| Started | Sep 09 06:39:32 PM UTC 24 |
| Finished | Sep 09 06:39:57 PM UTC 24 |
| Peak memory | 275080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733154617 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.733154617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.3302559852 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 14878400 ps |
| CPU time | 23.01 seconds |
| Started | Sep 09 06:39:28 PM UTC 24 |
| Finished | Sep 09 06:39:52 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302559852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3302559852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.309404890 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 37046400 ps |
| CPU time | 25.71 seconds |
| Started | Sep 09 06:39:23 PM UTC 24 |
| Finished | Sep 09 06:39:50 PM UTC 24 |
| Peak memory | 285232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=309404890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_disable.309404890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.51183767 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 8389598500 ps |
| CPU time | 170.31 seconds |
| Started | Sep 09 06:39:05 PM UTC 24 |
| Finished | Sep 09 06:41:58 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51183767 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.51183767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.402833925 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 5272685000 ps |
| CPU time | 211.29 seconds |
| Started | Sep 09 06:39:06 PM UTC 24 |
| Finished | Sep 09 06:42:41 PM UTC 24 |
| Peak memory | 301740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402833925 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.402833925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2303164743 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 40631092000 ps |
| CPU time | 378.45 seconds |
| Started | Sep 09 06:39:12 PM UTC 24 |
| Finished | Sep 09 06:45:36 PM UTC 24 |
| Peak memory | 301668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2303164743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 24.flash_ctrl_intr_rd_slow_flash.2303164743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.1413573047 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 154172000 ps |
| CPU time | 164.47 seconds |
| Started | Sep 09 06:39:05 PM UTC 24 |
| Finished | Sep 09 06:41:52 PM UTC 24 |
| Peak memory | 270796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413573047 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.1413573047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.191877063 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 21155000 ps |
| CPU time | 17.12 seconds |
| Started | Sep 09 06:39:14 PM UTC 24 |
| Finished | Sep 09 06:39:33 PM UTC 24 |
| Peak memory | 270908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191877063 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.191877063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.2544324587 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 94942700 ps |
| CPU time | 42.39 seconds |
| Started | Sep 09 06:39:20 PM UTC 24 |
| Finished | Sep 09 06:40:03 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544324587 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.2544324587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.607733795 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 27554000 ps |
| CPU time | 43.69 seconds |
| Started | Sep 09 06:39:22 PM UTC 24 |
| Finished | Sep 09 06:40:07 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=607733795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ct rl_rw_evict_all_en.607733795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.15885717 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 4895181800 ps |
| CPU time | 65.7 seconds |
| Started | Sep 09 06:39:25 PM UTC 24 |
| Finished | Sep 09 06:40:32 PM UTC 24 |
| Peak memory | 274792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15885717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.15885717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.757937570 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 71921500 ps |
| CPU time | 255.36 seconds |
| Started | Sep 09 06:39:02 PM UTC 24 |
| Finished | Sep 09 06:43:21 PM UTC 24 |
| Peak memory | 287248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757937570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.757937570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.3427262357 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 86786600 ps |
| CPU time | 22.52 seconds |
| Started | Sep 09 06:40:08 PM UTC 24 |
| Finished | Sep 09 06:40:31 PM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427262357 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.3427262357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.3886165261 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 16776700 ps |
| CPU time | 31.11 seconds |
| Started | Sep 09 06:40:04 PM UTC 24 |
| Finished | Sep 09 06:40:37 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886165261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.3886165261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.481149815 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 94187500 ps |
| CPU time | 33.19 seconds |
| Started | Sep 09 06:39:59 PM UTC 24 |
| Finished | Sep 09 06:40:34 PM UTC 24 |
| Peak memory | 285556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=481149815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c trl_disable.481149815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.3837745363 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 9241333200 ps |
| CPU time | 105.22 seconds |
| Started | Sep 09 06:39:33 PM UTC 24 |
| Finished | Sep 09 06:41:21 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837745363 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.3837745363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.3862983643 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 9595660600 ps |
| CPU time | 165.18 seconds |
| Started | Sep 09 06:39:38 PM UTC 24 |
| Finished | Sep 09 06:42:26 PM UTC 24 |
| Peak memory | 305844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862983643 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.3862983643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3245871403 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 12327818600 ps |
| CPU time | 277.19 seconds |
| Started | Sep 09 06:39:43 PM UTC 24 |
| Finished | Sep 09 06:44:24 PM UTC 24 |
| Peak memory | 303976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3245871403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.flash_ctrl_intr_rd_slow_flash.3245871403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.1175051604 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 372038800 ps |
| CPU time | 192.41 seconds |
| Started | Sep 09 06:39:33 PM UTC 24 |
| Finished | Sep 09 06:42:49 PM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175051604 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.1175051604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.479844190 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 31187100 ps |
| CPU time | 23.54 seconds |
| Started | Sep 09 06:39:51 PM UTC 24 |
| Finished | Sep 09 06:40:16 PM UTC 24 |
| Peak memory | 275016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479844190 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.479844190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.2309714103 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 32655600 ps |
| CPU time | 51.28 seconds |
| Started | Sep 09 06:39:53 PM UTC 24 |
| Finished | Sep 09 06:40:46 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309714103 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.2309714103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.2588938211 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 42157400 ps |
| CPU time | 42.42 seconds |
| Started | Sep 09 06:39:57 PM UTC 24 |
| Finished | Sep 09 06:40:41 PM UTC 24 |
| Peak memory | 287744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2588938211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c trl_rw_evict_all_en.2588938211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.3704687120 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 28554200 ps |
| CPU time | 132.85 seconds |
| Started | Sep 09 06:39:32 PM UTC 24 |
| Finished | Sep 09 06:41:48 PM UTC 24 |
| Peak memory | 287228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704687120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3704687120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.3395055783 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 79963800 ps |
| CPU time | 25.91 seconds |
| Started | Sep 09 06:40:39 PM UTC 24 |
| Finished | Sep 09 06:41:06 PM UTC 24 |
| Peak memory | 268932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395055783 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.3395055783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.1268983047 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 15495400 ps |
| CPU time | 26.9 seconds |
| Started | Sep 09 06:40:38 PM UTC 24 |
| Finished | Sep 09 06:41:06 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268983047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1268983047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.785035916 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 40937100 ps |
| CPU time | 35.75 seconds |
| Started | Sep 09 06:40:35 PM UTC 24 |
| Finished | Sep 09 06:41:12 PM UTC 24 |
| Peak memory | 285300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=785035916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_c trl_disable.785035916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.2063728000 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2498473600 ps |
| CPU time | 179.12 seconds |
| Started | Sep 09 06:40:17 PM UTC 24 |
| Finished | Sep 09 06:43:19 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063728000 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.2063728000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.2025708128 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 12352492900 ps |
| CPU time | 185.35 seconds |
| Started | Sep 09 06:40:24 PM UTC 24 |
| Finished | Sep 09 06:43:32 PM UTC 24 |
| Peak memory | 301772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025708128 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.2025708128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.219734843 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 12149468100 ps |
| CPU time | 406.88 seconds |
| Started | Sep 09 06:40:25 PM UTC 24 |
| Finished | Sep 09 06:47:17 PM UTC 24 |
| Peak memory | 306056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=219734843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 26.flash_ctrl_intr_rd_slow_flash.219734843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.1314930742 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 59514000 ps |
| CPU time | 224.11 seconds |
| Started | Sep 09 06:40:22 PM UTC 24 |
| Finished | Sep 09 06:44:10 PM UTC 24 |
| Peak memory | 273096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314930742 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.1314930742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.343361794 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 61083300 ps |
| CPU time | 23.27 seconds |
| Started | Sep 09 06:40:28 PM UTC 24 |
| Finished | Sep 09 06:40:53 PM UTC 24 |
| Peak memory | 275012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343361794 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.343361794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.2889031946 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 27400500 ps |
| CPU time | 33.44 seconds |
| Started | Sep 09 06:40:32 PM UTC 24 |
| Finished | Sep 09 06:41:07 PM UTC 24 |
| Peak memory | 287456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889031946 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.2889031946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.3537885113 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 82397500 ps |
| CPU time | 35.02 seconds |
| Started | Sep 09 06:40:33 PM UTC 24 |
| Finished | Sep 09 06:41:10 PM UTC 24 |
| Peak memory | 281276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3537885113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_c trl_rw_evict_all_en.3537885113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.2672130371 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1646858100 ps |
| CPU time | 76.94 seconds |
| Started | Sep 09 06:40:35 PM UTC 24 |
| Finished | Sep 09 06:41:53 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672130371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2672130371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.976630070 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2667903000 ps |
| CPU time | 170.34 seconds |
| Started | Sep 09 06:40:08 PM UTC 24 |
| Finished | Sep 09 06:43:01 PM UTC 24 |
| Peak memory | 291340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976630070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.976630070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.3045434811 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 22620100 ps |
| CPU time | 24.78 seconds |
| Started | Sep 09 06:41:21 PM UTC 24 |
| Finished | Sep 09 06:41:47 PM UTC 24 |
| Peak memory | 268932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045434811 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.3045434811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.3294014484 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 21126500 ps |
| CPU time | 25.46 seconds |
| Started | Sep 09 06:41:13 PM UTC 24 |
| Finished | Sep 09 06:41:39 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294014484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3294014484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.673835041 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 28925000 ps |
| CPU time | 39.27 seconds |
| Started | Sep 09 06:41:08 PM UTC 24 |
| Finished | Sep 09 06:41:50 PM UTC 24 |
| Peak memory | 285556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=673835041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_c trl_disable.673835041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.2979758211 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2175682200 ps |
| CPU time | 96.92 seconds |
| Started | Sep 09 06:40:47 PM UTC 24 |
| Finished | Sep 09 06:42:26 PM UTC 24 |
| Peak memory | 274772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979758211 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.2979758211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.2430348645 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 3933943600 ps |
| CPU time | 134.45 seconds |
| Started | Sep 09 06:40:52 PM UTC 24 |
| Finished | Sep 09 06:43:09 PM UTC 24 |
| Peak memory | 302004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430348645 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.2430348645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.4048865187 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 25181407700 ps |
| CPU time | 183.39 seconds |
| Started | Sep 09 06:40:52 PM UTC 24 |
| Finished | Sep 09 06:43:58 PM UTC 24 |
| Peak memory | 301668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4048865187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.flash_ctrl_intr_rd_slow_flash.4048865187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.794306734 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 139973300 ps |
| CPU time | 173.1 seconds |
| Started | Sep 09 06:40:50 PM UTC 24 |
| Finished | Sep 09 06:43:46 PM UTC 24 |
| Peak memory | 274888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794306734 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.794306734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.3320627409 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 22455100 ps |
| CPU time | 28.67 seconds |
| Started | Sep 09 06:40:54 PM UTC 24 |
| Finished | Sep 09 06:41:24 PM UTC 24 |
| Peak memory | 275004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320627409 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.3320627409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.2429017987 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 29446600 ps |
| CPU time | 34.67 seconds |
| Started | Sep 09 06:41:07 PM UTC 24 |
| Finished | Sep 09 06:41:44 PM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429017987 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.2429017987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.1792937394 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 27460600 ps |
| CPU time | 40.18 seconds |
| Started | Sep 09 06:41:07 PM UTC 24 |
| Finished | Sep 09 06:41:50 PM UTC 24 |
| Peak memory | 285668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1792937394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_c trl_rw_evict_all_en.1792937394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.2928244573 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2000515600 ps |
| CPU time | 83.54 seconds |
| Started | Sep 09 06:41:11 PM UTC 24 |
| Finished | Sep 09 06:42:36 PM UTC 24 |
| Peak memory | 270752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928244573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2928244573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.1513313725 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 33014400 ps |
| CPU time | 64.95 seconds |
| Started | Sep 09 06:40:42 PM UTC 24 |
| Finished | Sep 09 06:41:49 PM UTC 24 |
| Peak memory | 283140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513313725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1513313725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.3036209439 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 109385200 ps |
| CPU time | 25.66 seconds |
| Started | Sep 09 06:41:51 PM UTC 24 |
| Finished | Sep 09 06:42:18 PM UTC 24 |
| Peak memory | 268916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036209439 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.3036209439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.4215577965 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 70420200 ps |
| CPU time | 20.32 seconds |
| Started | Sep 09 06:41:50 PM UTC 24 |
| Finished | Sep 09 06:42:11 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215577965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.4215577965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.2868181578 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 20397200 ps |
| CPU time | 37.3 seconds |
| Started | Sep 09 06:41:48 PM UTC 24 |
| Finished | Sep 09 06:42:26 PM UTC 24 |
| Peak memory | 285332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2868181578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ ctrl_disable.2868181578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.4074253865 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 10446681300 ps |
| CPU time | 211.84 seconds |
| Started | Sep 09 06:41:25 PM UTC 24 |
| Finished | Sep 09 06:45:00 PM UTC 24 |
| Peak memory | 274776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074253865 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.4074253865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.2092873080 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 1608811700 ps |
| CPU time | 127.7 seconds |
| Started | Sep 09 06:41:40 PM UTC 24 |
| Finished | Sep 09 06:43:50 PM UTC 24 |
| Peak memory | 305972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092873080 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.2092873080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3664284857 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 24995275800 ps |
| CPU time | 320.42 seconds |
| Started | Sep 09 06:41:41 PM UTC 24 |
| Finished | Sep 09 06:47:07 PM UTC 24 |
| Peak memory | 301796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3664284857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.flash_ctrl_intr_rd_slow_flash.3664284857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.1498888526 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 42133500 ps |
| CPU time | 174.03 seconds |
| Started | Sep 09 06:41:27 PM UTC 24 |
| Finished | Sep 09 06:44:23 PM UTC 24 |
| Peak memory | 270784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498888526 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.1498888526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.4141400205 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 20778900 ps |
| CPU time | 18.26 seconds |
| Started | Sep 09 06:41:43 PM UTC 24 |
| Finished | Sep 09 06:42:03 PM UTC 24 |
| Peak memory | 275324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141400205 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.4141400205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.2287074268 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 68830800 ps |
| CPU time | 49.01 seconds |
| Started | Sep 09 06:41:44 PM UTC 24 |
| Finished | Sep 09 06:42:35 PM UTC 24 |
| Peak memory | 281536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2287074268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_c trl_rw_evict_all_en.2287074268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.2565004045 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3332361000 ps |
| CPU time | 87.5 seconds |
| Started | Sep 09 06:41:49 PM UTC 24 |
| Finished | Sep 09 06:43:18 PM UTC 24 |
| Peak memory | 274784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565004045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2565004045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.2477161694 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 73302600 ps |
| CPU time | 107.49 seconds |
| Started | Sep 09 06:41:22 PM UTC 24 |
| Finished | Sep 09 06:43:12 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477161694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2477161694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.1011235731 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 244447400 ps |
| CPU time | 28.48 seconds |
| Started | Sep 09 06:42:24 PM UTC 24 |
| Finished | Sep 09 06:42:54 PM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011235731 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.1011235731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.2637549384 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 14241400 ps |
| CPU time | 19.64 seconds |
| Started | Sep 09 06:42:20 PM UTC 24 |
| Finished | Sep 09 06:42:41 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637549384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.2637549384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.2428719579 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 28185000 ps |
| CPU time | 29.89 seconds |
| Started | Sep 09 06:42:19 PM UTC 24 |
| Finished | Sep 09 06:42:50 PM UTC 24 |
| Peak memory | 285360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2428719579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ ctrl_disable.2428719579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.2369510611 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4109145200 ps |
| CPU time | 212.42 seconds |
| Started | Sep 09 06:41:53 PM UTC 24 |
| Finished | Sep 09 06:45:29 PM UTC 24 |
| Peak memory | 272728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369510611 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.2369510611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.46518410 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 1044534500 ps |
| CPU time | 146.44 seconds |
| Started | Sep 09 06:41:59 PM UTC 24 |
| Finished | Sep 09 06:44:28 PM UTC 24 |
| Peak memory | 305832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46518410 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.46518410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2627019914 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 40840237400 ps |
| CPU time | 146.61 seconds |
| Started | Sep 09 06:42:04 PM UTC 24 |
| Finished | Sep 09 06:44:32 PM UTC 24 |
| Peak memory | 303748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2627019914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.flash_ctrl_intr_rd_slow_flash.2627019914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.3759202686 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 71060800 ps |
| CPU time | 198.97 seconds |
| Started | Sep 09 06:41:54 PM UTC 24 |
| Finished | Sep 09 06:45:16 PM UTC 24 |
| Peak memory | 270640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759202686 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.3759202686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.309174728 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 216515900 ps |
| CPU time | 34.89 seconds |
| Started | Sep 09 06:42:04 PM UTC 24 |
| Finished | Sep 09 06:42:40 PM UTC 24 |
| Peak memory | 275268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309174728 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.309174728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.3623947007 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 29268400 ps |
| CPU time | 61.52 seconds |
| Started | Sep 09 06:42:12 PM UTC 24 |
| Finished | Sep 09 06:43:15 PM UTC 24 |
| Peak memory | 285632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3623947007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c trl_rw_evict_all_en.3623947007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.575938613 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 1801727400 ps |
| CPU time | 87.87 seconds |
| Started | Sep 09 06:42:19 PM UTC 24 |
| Finished | Sep 09 06:43:49 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575938613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.575938613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.1421771327 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 46749500 ps |
| CPU time | 123.72 seconds |
| Started | Sep 09 06:41:51 PM UTC 24 |
| Finished | Sep 09 06:43:57 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421771327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.1421771327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.1081145347 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 101946100 ps |
| CPU time | 26.63 seconds |
| Started | Sep 09 05:51:24 PM UTC 24 |
| Finished | Sep 09 05:51:52 PM UTC 24 |
| Peak memory | 275056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081145347 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.1081145347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2998106232 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 106130100 ps |
| CPU time | 24.51 seconds |
| Started | Sep 09 05:51:02 PM UTC 24 |
| Finished | Sep 09 05:51:28 PM UTC 24 |
| Peak memory | 272996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998106232 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.2998106232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.1293842737 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 40404300 ps |
| CPU time | 19.12 seconds |
| Started | Sep 09 05:50:49 PM UTC 24 |
| Finished | Sep 09 05:51:11 PM UTC 24 |
| Peak memory | 294876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293842737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.1293842737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.1473911461 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 645139600 ps |
| CPU time | 216.13 seconds |
| Started | Sep 09 05:49:03 PM UTC 24 |
| Finished | Sep 09 05:52:42 PM UTC 24 |
| Peak memory | 291508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1473911461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_derr_detect.1473911461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.2579821172 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 15326500 ps |
| CPU time | 31.71 seconds |
| Started | Sep 09 05:50:18 PM UTC 24 |
| Finished | Sep 09 05:50:51 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2579821172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_disable.2579821172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.2731133218 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3205277300 ps |
| CPU time | 394.34 seconds |
| Started | Sep 09 05:46:07 PM UTC 24 |
| Finished | Sep 09 05:52:46 PM UTC 24 |
| Peak memory | 274908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731133218 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2731133218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.2767246538 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 9525770400 ps |
| CPU time | 3433.79 seconds |
| Started | Sep 09 05:47:14 PM UTC 24 |
| Finished | Sep 09 06:45:04 PM UTC 24 |
| Peak memory | 277624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767246538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.2767246538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_type.1030985590 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 801438300 ps |
| CPU time | 2421.73 seconds |
| Started | Sep 09 05:46:48 PM UTC 24 |
| Finished | Sep 09 06:27:33 PM UTC 24 |
| Peak memory | 275696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10 30985590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _error_prog_type.1030985590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.1009563373 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 312870900 ps |
| CPU time | 1103.16 seconds |
| Started | Sep 09 05:46:51 PM UTC 24 |
| Finished | Sep 09 06:05:26 PM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009563373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1009563373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.4078620391 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1193010800 ps |
| CPU time | 39 seconds |
| Started | Sep 09 05:46:33 PM UTC 24 |
| Finished | Sep 09 05:47:14 PM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 78620391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetc h_code.4078620391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3121562705 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 710711800 ps |
| CPU time | 45.67 seconds |
| Started | Sep 09 05:50:51 PM UTC 24 |
| Finished | Sep 09 05:51:39 PM UTC 24 |
| Peak memory | 273320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121562 705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f s_sup.3121562705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.4125303451 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 324089820600 ps |
| CPU time | 2737.45 seconds |
| Started | Sep 09 05:46:41 PM UTC 24 |
| Finished | Sep 09 06:32:48 PM UTC 24 |
| Peak memory | 277972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125303451 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.4125303451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.384096946 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 247904085200 ps |
| CPU time | 3111.95 seconds |
| Started | Sep 09 05:46:26 PM UTC 24 |
| Finished | Sep 09 06:38:52 PM UTC 24 |
| Peak memory | 277852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384096946 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.384096946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.338966361 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 49188500 ps |
| CPU time | 188 seconds |
| Started | Sep 09 05:45:55 PM UTC 24 |
| Finished | Sep 09 05:49:06 PM UTC 24 |
| Peak memory | 274948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338966361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.338966361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1108597414 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 10039609700 ps |
| CPU time | 77.56 seconds |
| Started | Sep 09 05:51:23 PM UTC 24 |
| Finished | Sep 09 05:52:42 PM UTC 24 |
| Peak memory | 277260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1108597414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1108597414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.673942228 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 18510000 ps |
| CPU time | 26.2 seconds |
| Started | Sep 09 05:51:12 PM UTC 24 |
| Finished | Sep 09 05:51:39 PM UTC 24 |
| Peak memory | 275104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=673942228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_hw_read_seed_err.673942228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3416719421 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1454861000 ps |
| CPU time | 68.67 seconds |
| Started | Sep 09 05:46:02 PM UTC 24 |
| Finished | Sep 09 05:47:13 PM UTC 24 |
| Peak memory | 272728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416719421 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.3416719421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.2936939876 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 4453060200 ps |
| CPU time | 488.66 seconds |
| Started | Sep 09 05:49:22 PM UTC 24 |
| Finished | Sep 09 05:57:37 PM UTC 24 |
| Peak memory | 336612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2936939876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integr ity.2936939876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.3008472121 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1627924300 ps |
| CPU time | 132.99 seconds |
| Started | Sep 09 05:49:30 PM UTC 24 |
| Finished | Sep 09 05:51:46 PM UTC 24 |
| Peak memory | 305872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008472121 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.3008472121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1916443870 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 23780243900 ps |
| CPU time | 142.22 seconds |
| Started | Sep 09 05:49:36 PM UTC 24 |
| Finished | Sep 09 05:52:01 PM UTC 24 |
| Peak memory | 303716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1916443870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_intr_rd_slow_flash.1916443870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.628792622 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 8271210000 ps |
| CPU time | 75.73 seconds |
| Started | Sep 09 05:49:31 PM UTC 24 |
| Finished | Sep 09 05:50:49 PM UTC 24 |
| Peak memory | 270936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628792622 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.628792622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1495899356 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 28781705900 ps |
| CPU time | 154.65 seconds |
| Started | Sep 09 05:49:47 PM UTC 24 |
| Finished | Sep 09 05:52:24 PM UTC 24 |
| Peak memory | 270948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495899356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1495899356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.2626607101 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 5728187100 ps |
| CPU time | 91.89 seconds |
| Started | Sep 09 05:47:15 PM UTC 24 |
| Finished | Sep 09 05:48:49 PM UTC 24 |
| Peak memory | 274752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626607101 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2626607101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.623204253 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 13522858200 ps |
| CPU time | 870.99 seconds |
| Started | Sep 09 05:46:32 PM UTC 24 |
| Finished | Sep 09 06:01:14 PM UTC 24 |
| Peak memory | 283076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=623204253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_mp_regions.623204253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.1217058996 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 136717800 ps |
| CPU time | 135.09 seconds |
| Started | Sep 09 05:46:16 PM UTC 24 |
| Finished | Sep 09 05:48:34 PM UTC 24 |
| Peak memory | 270788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217058996 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.1217058996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.344542370 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2245534600 ps |
| CPU time | 160.66 seconds |
| Started | Sep 09 05:49:08 PM UTC 24 |
| Finished | Sep 09 05:51:51 PM UTC 24 |
| Peak memory | 291504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=344542370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_oversize_error.344542370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.3759564762 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 194684200 ps |
| CPU time | 24.83 seconds |
| Started | Sep 09 05:51:00 PM UTC 24 |
| Finished | Sep 09 05:51:26 PM UTC 24 |
| Peak memory | 273468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759564762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.3759564762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.1065801612 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 123312800 ps |
| CPU time | 127.84 seconds |
| Started | Sep 09 05:46:01 PM UTC 24 |
| Finished | Sep 09 05:48:12 PM UTC 24 |
| Peak memory | 274908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065801612 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1065801612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.53379701 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 886537500 ps |
| CPU time | 38.09 seconds |
| Started | Sep 09 05:50:52 PM UTC 24 |
| Finished | Sep 09 05:51:32 PM UTC 24 |
| Peak memory | 275228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=53379701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.53379701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3369721351 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 71919600 ps |
| CPU time | 24.07 seconds |
| Started | Sep 09 05:50:58 PM UTC 24 |
| Finished | Sep 09 05:51:23 PM UTC 24 |
| Peak memory | 273168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3369721351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3369721351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.2176212295 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 69355100 ps |
| CPU time | 27.54 seconds |
| Started | Sep 09 05:49:49 PM UTC 24 |
| Finished | Sep 09 05:50:17 PM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176212295 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.2176212295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.2194245487 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1516525000 ps |
| CPU time | 1311.26 seconds |
| Started | Sep 09 05:45:53 PM UTC 24 |
| Finished | Sep 09 06:07:59 PM UTC 24 |
| Peak memory | 295688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194245487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.2194245487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.4053942498 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4932446900 ps |
| CPU time | 250.38 seconds |
| Started | Sep 09 05:45:59 PM UTC 24 |
| Finished | Sep 09 05:50:13 PM UTC 24 |
| Peak memory | 272904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053942498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.4053942498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.1032222686 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 61875600 ps |
| CPU time | 45.42 seconds |
| Started | Sep 09 05:50:14 PM UTC 24 |
| Finished | Sep 09 05:51:01 PM UTC 24 |
| Peak memory | 287552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032222686 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.1032222686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.541499722 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 61319700 ps |
| CPU time | 43.82 seconds |
| Started | Sep 09 05:48:50 PM UTC 24 |
| Finished | Sep 09 05:49:36 PM UTC 24 |
| Peak memory | 275140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=541499722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash _ctrl_read_word_sweep_derr.541499722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.1763173507 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 89935500 ps |
| CPU time | 41.81 seconds |
| Started | Sep 09 05:48:13 PM UTC 24 |
| Finished | Sep 09 05:48:56 PM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763173507 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.1763173507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2839985534 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3400944400 ps |
| CPU time | 108.14 seconds |
| Started | Sep 09 05:48:00 PM UTC 24 |
| Finished | Sep 09 05:49:51 PM UTC 24 |
| Peak memory | 291388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2839985534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.2839985534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.771905865 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1673499700 ps |
| CPU time | 173.22 seconds |
| Started | Sep 09 05:48:51 PM UTC 24 |
| Finished | Sep 09 05:51:48 PM UTC 24 |
| Peak memory | 291528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771905865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.771905865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.3578211100 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2984150000 ps |
| CPU time | 122.7 seconds |
| Started | Sep 09 05:48:15 PM UTC 24 |
| Finished | Sep 09 05:50:20 PM UTC 24 |
| Peak memory | 307888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3578211100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash _ctrl_ro_serr.3578211100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.4115529894 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4142696500 ps |
| CPU time | 474.71 seconds |
| Started | Sep 09 05:48:02 PM UTC 24 |
| Finished | Sep 09 05:56:02 PM UTC 24 |
| Peak memory | 320100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115529894 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.4115529894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.1257503785 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 14919659400 ps |
| CPU time | 167.88 seconds |
| Started | Sep 09 05:48:57 PM UTC 24 |
| Finished | Sep 09 05:51:47 PM UTC 24 |
| Peak memory | 295812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1257503785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 3.flash_ctrl_rw_derr.1257503785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.4054567647 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 43780900 ps |
| CPU time | 58.58 seconds |
| Started | Sep 09 05:49:52 PM UTC 24 |
| Finished | Sep 09 05:50:52 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054567647 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.4054567647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2585055054 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 31835000 ps |
| CPU time | 53.16 seconds |
| Started | Sep 09 05:50:04 PM UTC 24 |
| Finished | Sep 09 05:50:58 PM UTC 24 |
| Peak memory | 285308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2585055054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct rl_rw_evict_all_en.2585055054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.1014758437 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2888270300 ps |
| CPU time | 139.6 seconds |
| Started | Sep 09 05:48:35 PM UTC 24 |
| Finished | Sep 09 05:50:57 PM UTC 24 |
| Peak memory | 305840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1014758437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.1014758437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.934097974 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3962915600 ps |
| CPU time | 6175.2 seconds |
| Started | Sep 09 05:50:20 PM UTC 24 |
| Finished | Sep 09 07:34:18 PM UTC 24 |
| Peak memory | 314172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934097974 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.934097974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.2005359666 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2911828400 ps |
| CPU time | 68.9 seconds |
| Started | Sep 09 05:50:35 PM UTC 24 |
| Finished | Sep 09 05:51:46 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005359666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2005359666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.4000630452 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1784906800 ps |
| CPU time | 109.88 seconds |
| Started | Sep 09 05:48:49 PM UTC 24 |
| Finished | Sep 09 05:50:41 PM UTC 24 |
| Peak memory | 275116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400 0630452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser r_address.4000630452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.1037467362 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3364709800 ps |
| CPU time | 114.43 seconds |
| Started | Sep 09 05:48:38 PM UTC 24 |
| Finished | Sep 09 05:50:35 PM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10 37467362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_se rr_counter.1037467362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1283717430 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 24545200 ps |
| CPU time | 132.56 seconds |
| Started | Sep 09 05:45:46 PM UTC 24 |
| Finished | Sep 09 05:48:01 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283717430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1283717430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1652896163 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 17671200 ps |
| CPU time | 41.65 seconds |
| Started | Sep 09 05:45:49 PM UTC 24 |
| Finished | Sep 09 05:46:32 PM UTC 24 |
| Peak memory | 270616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652896163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1652896163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1797883173 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 458429500 ps |
| CPU time | 1286.99 seconds |
| Started | Sep 09 05:50:42 PM UTC 24 |
| Finished | Sep 09 06:12:23 PM UTC 24 |
| Peak memory | 293344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797883173 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.1797883173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.321912864 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 50077500 ps |
| CPU time | 31.58 seconds |
| Started | Sep 09 05:45:53 PM UTC 24 |
| Finished | Sep 09 05:46:26 PM UTC 24 |
| Peak memory | 270616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321912864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.321912864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.1762558815 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 26735453100 ps |
| CPU time | 257.94 seconds |
| Started | Sep 09 05:47:55 PM UTC 24 |
| Finished | Sep 09 05:52:18 PM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1762558815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.1762558815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.31681734 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 128815500 ps |
| CPU time | 24.13 seconds |
| Started | Sep 09 06:42:52 PM UTC 24 |
| Finished | Sep 09 06:43:17 PM UTC 24 |
| Peak memory | 275060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31681734 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.31681734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.450510911 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 24136600 ps |
| CPU time | 27.67 seconds |
| Started | Sep 09 06:42:49 PM UTC 24 |
| Finished | Sep 09 06:43:18 PM UTC 24 |
| Peak memory | 294808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450510911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.450510911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.297251356 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 10669900 ps |
| CPU time | 42.94 seconds |
| Started | Sep 09 06:42:41 PM UTC 24 |
| Finished | Sep 09 06:43:26 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=297251356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c trl_disable.297251356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.508199389 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 7139936000 ps |
| CPU time | 92.27 seconds |
| Started | Sep 09 06:42:28 PM UTC 24 |
| Finished | Sep 09 06:44:02 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508199389 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.508199389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.3110115443 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 7292834900 ps |
| CPU time | 231.74 seconds |
| Started | Sep 09 06:42:36 PM UTC 24 |
| Finished | Sep 09 06:46:31 PM UTC 24 |
| Peak memory | 302004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110115443 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.3110115443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3653058631 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 33567044100 ps |
| CPU time | 192.34 seconds |
| Started | Sep 09 06:42:37 PM UTC 24 |
| Finished | Sep 09 06:45:52 PM UTC 24 |
| Peak memory | 301668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3653058631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.flash_ctrl_intr_rd_slow_flash.3653058631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.2646769394 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 172933400 ps |
| CPU time | 185.8 seconds |
| Started | Sep 09 06:42:28 PM UTC 24 |
| Finished | Sep 09 06:45:36 PM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646769394 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.2646769394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.1922887604 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 48857500 ps |
| CPU time | 32.85 seconds |
| Started | Sep 09 06:42:40 PM UTC 24 |
| Finished | Sep 09 06:43:14 PM UTC 24 |
| Peak memory | 281536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922887604 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.1922887604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.685672843 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 29126700 ps |
| CPU time | 44.62 seconds |
| Started | Sep 09 06:42:41 PM UTC 24 |
| Finished | Sep 09 06:43:27 PM UTC 24 |
| Peak memory | 287412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=685672843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ct rl_rw_evict_all_en.685672843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.1103560199 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 1344583600 ps |
| CPU time | 66.26 seconds |
| Started | Sep 09 06:42:42 PM UTC 24 |
| Finished | Sep 09 06:43:50 PM UTC 24 |
| Peak memory | 275044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103560199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1103560199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.1838312213 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 20707700 ps |
| CPU time | 162.13 seconds |
| Started | Sep 09 06:42:26 PM UTC 24 |
| Finished | Sep 09 06:45:11 PM UTC 24 |
| Peak memory | 287500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838312213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.1838312213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.207915156 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 18191800 ps |
| CPU time | 20.11 seconds |
| Started | Sep 09 06:43:20 PM UTC 24 |
| Finished | Sep 09 06:43:41 PM UTC 24 |
| Peak memory | 268916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207915156 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.207915156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.1875853292 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 16741900 ps |
| CPU time | 24.35 seconds |
| Started | Sep 09 06:43:20 PM UTC 24 |
| Finished | Sep 09 06:43:46 PM UTC 24 |
| Peak memory | 294612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875853292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.1875853292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.1833510100 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 15634500 ps |
| CPU time | 34.15 seconds |
| Started | Sep 09 06:43:17 PM UTC 24 |
| Finished | Sep 09 06:43:53 PM UTC 24 |
| Peak memory | 285460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1833510100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ ctrl_disable.1833510100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.2856703442 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 15906853800 ps |
| CPU time | 121.95 seconds |
| Started | Sep 09 06:42:58 PM UTC 24 |
| Finished | Sep 09 06:45:02 PM UTC 24 |
| Peak memory | 274776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856703442 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.2856703442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.1419821318 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 1753586300 ps |
| CPU time | 249.43 seconds |
| Started | Sep 09 06:43:10 PM UTC 24 |
| Finished | Sep 09 06:47:24 PM UTC 24 |
| Peak memory | 302004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419821318 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.1419821318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2850633188 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 105524956900 ps |
| CPU time | 409.33 seconds |
| Started | Sep 09 06:43:12 PM UTC 24 |
| Finished | Sep 09 06:50:07 PM UTC 24 |
| Peak memory | 301796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2850633188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.flash_ctrl_intr_rd_slow_flash.2850633188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.1034218800 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 137589000 ps |
| CPU time | 172.7 seconds |
| Started | Sep 09 06:43:02 PM UTC 24 |
| Finished | Sep 09 06:45:58 PM UTC 24 |
| Peak memory | 275140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034218800 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.1034218800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.3850261240 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 42695100 ps |
| CPU time | 37.01 seconds |
| Started | Sep 09 06:43:15 PM UTC 24 |
| Finished | Sep 09 06:43:54 PM UTC 24 |
| Peak memory | 281280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850261240 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.3850261240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.2073410123 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 29622100 ps |
| CPU time | 50.85 seconds |
| Started | Sep 09 06:43:16 PM UTC 24 |
| Finished | Sep 09 06:44:09 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2073410123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c trl_rw_evict_all_en.2073410123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.4035972720 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 7575354800 ps |
| CPU time | 91.25 seconds |
| Started | Sep 09 06:43:19 PM UTC 24 |
| Finished | Sep 09 06:44:52 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035972720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.4035972720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.1297647011 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 128656500 ps |
| CPU time | 198.11 seconds |
| Started | Sep 09 06:42:55 PM UTC 24 |
| Finished | Sep 09 06:46:16 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297647011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1297647011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.3863203080 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 61198600 ps |
| CPU time | 22.73 seconds |
| Started | Sep 09 06:43:51 PM UTC 24 |
| Finished | Sep 09 06:44:15 PM UTC 24 |
| Peak memory | 274832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863203080 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.3863203080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.1537313946 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 28192300 ps |
| CPU time | 17.88 seconds |
| Started | Sep 09 06:43:50 PM UTC 24 |
| Finished | Sep 09 06:44:09 PM UTC 24 |
| Peak memory | 294676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537313946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.1537313946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.3277067651 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 12990300 ps |
| CPU time | 25.3 seconds |
| Started | Sep 09 06:43:47 PM UTC 24 |
| Finished | Sep 09 06:44:13 PM UTC 24 |
| Peak memory | 285396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3277067651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ ctrl_disable.3277067651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.2289337347 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 1103916500 ps |
| CPU time | 70.26 seconds |
| Started | Sep 09 06:43:26 PM UTC 24 |
| Finished | Sep 09 06:44:38 PM UTC 24 |
| Peak memory | 275032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289337347 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.2289337347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.1868845398 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 468135100 ps |
| CPU time | 153.8 seconds |
| Started | Sep 09 06:43:30 PM UTC 24 |
| Finished | Sep 09 06:46:07 PM UTC 24 |
| Peak memory | 305844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868845398 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.1868845398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2232237435 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 29865132800 ps |
| CPU time | 158.41 seconds |
| Started | Sep 09 06:43:33 PM UTC 24 |
| Finished | Sep 09 06:46:14 PM UTC 24 |
| Peak memory | 303712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2232237435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.flash_ctrl_intr_rd_slow_flash.2232237435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.2651279154 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 44815600 ps |
| CPU time | 139.8 seconds |
| Started | Sep 09 06:43:28 PM UTC 24 |
| Finished | Sep 09 06:45:50 PM UTC 24 |
| Peak memory | 271040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651279154 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.2651279154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.2385615461 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 29945300 ps |
| CPU time | 61.21 seconds |
| Started | Sep 09 06:43:43 PM UTC 24 |
| Finished | Sep 09 06:44:45 PM UTC 24 |
| Peak memory | 287388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385615461 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.2385615461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.2536902562 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 62123800 ps |
| CPU time | 51.82 seconds |
| Started | Sep 09 06:43:47 PM UTC 24 |
| Finished | Sep 09 06:44:40 PM UTC 24 |
| Peak memory | 287620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2536902562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c trl_rw_evict_all_en.2536902562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.3385123734 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 6459410900 ps |
| CPU time | 67.93 seconds |
| Started | Sep 09 06:43:48 PM UTC 24 |
| Finished | Sep 09 06:44:58 PM UTC 24 |
| Peak memory | 274776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385123734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3385123734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.615639494 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 52755500 ps |
| CPU time | 78.33 seconds |
| Started | Sep 09 06:43:22 PM UTC 24 |
| Finished | Sep 09 06:44:43 PM UTC 24 |
| Peak memory | 283152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615639494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.615639494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.1009919211 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 32882800 ps |
| CPU time | 26.85 seconds |
| Started | Sep 09 06:44:09 PM UTC 24 |
| Finished | Sep 09 06:44:37 PM UTC 24 |
| Peak memory | 268920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009919211 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.1009919211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.1753714165 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 38211400 ps |
| CPU time | 19.61 seconds |
| Started | Sep 09 06:44:03 PM UTC 24 |
| Finished | Sep 09 06:44:24 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753714165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.1753714165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.1299804558 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 24744900 ps |
| CPU time | 28.62 seconds |
| Started | Sep 09 06:44:02 PM UTC 24 |
| Finished | Sep 09 06:44:32 PM UTC 24 |
| Peak memory | 285388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1299804558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ ctrl_disable.1299804558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.202532856 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 8926470100 ps |
| CPU time | 140.13 seconds |
| Started | Sep 09 06:43:51 PM UTC 24 |
| Finished | Sep 09 06:46:13 PM UTC 24 |
| Peak memory | 273048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202532856 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.202532856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.3511729207 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 6622187600 ps |
| CPU time | 248.86 seconds |
| Started | Sep 09 06:43:55 PM UTC 24 |
| Finished | Sep 09 06:48:07 PM UTC 24 |
| Peak memory | 293572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511729207 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.3511729207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1385347332 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 23852748500 ps |
| CPU time | 169.85 seconds |
| Started | Sep 09 06:43:56 PM UTC 24 |
| Finished | Sep 09 06:46:49 PM UTC 24 |
| Peak memory | 303972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1385347332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.flash_ctrl_intr_rd_slow_flash.1385347332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.3774508020 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 136615600 ps |
| CPU time | 141.77 seconds |
| Started | Sep 09 06:43:54 PM UTC 24 |
| Finished | Sep 09 06:46:18 PM UTC 24 |
| Peak memory | 271224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774508020 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.3774508020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.2055979814 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 73846900 ps |
| CPU time | 36.55 seconds |
| Started | Sep 09 06:43:57 PM UTC 24 |
| Finished | Sep 09 06:44:35 PM UTC 24 |
| Peak memory | 281536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055979814 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.2055979814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.4046732062 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 185540700 ps |
| CPU time | 44.53 seconds |
| Started | Sep 09 06:43:59 PM UTC 24 |
| Finished | Sep 09 06:44:45 PM UTC 24 |
| Peak memory | 281280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4046732062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c trl_rw_evict_all_en.4046732062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.1497938030 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 8157200200 ps |
| CPU time | 76.59 seconds |
| Started | Sep 09 06:44:03 PM UTC 24 |
| Finished | Sep 09 06:45:21 PM UTC 24 |
| Peak memory | 272728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497938030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1497938030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.969508874 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 69991600 ps |
| CPU time | 106.34 seconds |
| Started | Sep 09 06:43:51 PM UTC 24 |
| Finished | Sep 09 06:45:39 PM UTC 24 |
| Peak memory | 287112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969508874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.969508874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.2275516388 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 62294900 ps |
| CPU time | 28.04 seconds |
| Started | Sep 09 06:44:40 PM UTC 24 |
| Finished | Sep 09 06:45:10 PM UTC 24 |
| Peak memory | 275060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275516388 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.2275516388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.484812974 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 52833800 ps |
| CPU time | 21.8 seconds |
| Started | Sep 09 06:44:33 PM UTC 24 |
| Finished | Sep 09 06:44:56 PM UTC 24 |
| Peak memory | 294676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484812974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.484812974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.4179639437 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 46070600 ps |
| CPU time | 36.17 seconds |
| Started | Sep 09 06:44:29 PM UTC 24 |
| Finished | Sep 09 06:45:07 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4179639437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ ctrl_disable.4179639437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.688956779 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2663640300 ps |
| CPU time | 82.52 seconds |
| Started | Sep 09 06:44:10 PM UTC 24 |
| Finished | Sep 09 06:45:35 PM UTC 24 |
| Peak memory | 275100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688956779 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.688956779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.1617908249 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 5213029600 ps |
| CPU time | 181.29 seconds |
| Started | Sep 09 06:44:16 PM UTC 24 |
| Finished | Sep 09 06:47:20 PM UTC 24 |
| Peak memory | 301748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617908249 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.1617908249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3547087860 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 15535987900 ps |
| CPU time | 153.15 seconds |
| Started | Sep 09 06:44:25 PM UTC 24 |
| Finished | Sep 09 06:47:01 PM UTC 24 |
| Peak memory | 303716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3547087860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.flash_ctrl_intr_rd_slow_flash.3547087860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.2293702903 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 38192300 ps |
| CPU time | 161.24 seconds |
| Started | Sep 09 06:44:14 PM UTC 24 |
| Finished | Sep 09 06:46:58 PM UTC 24 |
| Peak memory | 270956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293702903 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.2293702903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.2326196590 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 112733600 ps |
| CPU time | 41.23 seconds |
| Started | Sep 09 06:44:25 PM UTC 24 |
| Finished | Sep 09 06:45:07 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326196590 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.2326196590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.2252902600 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 110443400 ps |
| CPU time | 37.08 seconds |
| Started | Sep 09 06:44:25 PM UTC 24 |
| Finished | Sep 09 06:45:03 PM UTC 24 |
| Peak memory | 281600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2252902600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c trl_rw_evict_all_en.2252902600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.652141189 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 4443424300 ps |
| CPU time | 85.75 seconds |
| Started | Sep 09 06:44:32 PM UTC 24 |
| Finished | Sep 09 06:46:00 PM UTC 24 |
| Peak memory | 275104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652141189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.652141189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.1474278277 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 43483900 ps |
| CPU time | 64.37 seconds |
| Started | Sep 09 06:44:10 PM UTC 24 |
| Finished | Sep 09 06:45:16 PM UTC 24 |
| Peak memory | 283144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474278277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1474278277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.1949298709 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 52886000 ps |
| CPU time | 25.24 seconds |
| Started | Sep 09 06:45:02 PM UTC 24 |
| Finished | Sep 09 06:45:28 PM UTC 24 |
| Peak memory | 268916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949298709 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.1949298709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.1118591840 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 47575400 ps |
| CPU time | 16.89 seconds |
| Started | Sep 09 06:44:58 PM UTC 24 |
| Finished | Sep 09 06:45:16 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118591840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.1118591840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.4291686752 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 73181000 ps |
| CPU time | 36.17 seconds |
| Started | Sep 09 06:44:53 PM UTC 24 |
| Finished | Sep 09 06:45:31 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4291686752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ ctrl_disable.4291686752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.3907462325 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 4179492600 ps |
| CPU time | 77.6 seconds |
| Started | Sep 09 06:44:42 PM UTC 24 |
| Finished | Sep 09 06:46:01 PM UTC 24 |
| Peak memory | 271008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907462325 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.3907462325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.3399737108 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 7155333900 ps |
| CPU time | 251.83 seconds |
| Started | Sep 09 06:44:42 PM UTC 24 |
| Finished | Sep 09 06:48:57 PM UTC 24 |
| Peak memory | 293548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399737108 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.3399737108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.54951579 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 13279905500 ps |
| CPU time | 304.8 seconds |
| Started | Sep 09 06:44:44 PM UTC 24 |
| Finished | Sep 09 06:49:53 PM UTC 24 |
| Peak memory | 304008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=54951579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 35.flash_ctrl_intr_rd_slow_flash.54951579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.4252100435 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 76210700 ps |
| CPU time | 183 seconds |
| Started | Sep 09 06:44:42 PM UTC 24 |
| Finished | Sep 09 06:47:47 PM UTC 24 |
| Peak memory | 274744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252100435 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.4252100435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.3770726384 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 71203800 ps |
| CPU time | 44.8 seconds |
| Started | Sep 09 06:44:46 PM UTC 24 |
| Finished | Sep 09 06:45:32 PM UTC 24 |
| Peak memory | 287488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770726384 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.3770726384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.3531976933 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 26890700 ps |
| CPU time | 60.12 seconds |
| Started | Sep 09 06:44:46 PM UTC 24 |
| Finished | Sep 09 06:45:48 PM UTC 24 |
| Peak memory | 287388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3531976933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c trl_rw_evict_all_en.3531976933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.2053298040 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 7109804100 ps |
| CPU time | 79.14 seconds |
| Started | Sep 09 06:44:57 PM UTC 24 |
| Finished | Sep 09 06:46:18 PM UTC 24 |
| Peak memory | 275040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053298040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2053298040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.591582872 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 25840300 ps |
| CPU time | 226.1 seconds |
| Started | Sep 09 06:44:42 PM UTC 24 |
| Finished | Sep 09 06:48:31 PM UTC 24 |
| Peak memory | 289356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591582872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.591582872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.608476467 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 46492100 ps |
| CPU time | 18.04 seconds |
| Started | Sep 09 06:45:22 PM UTC 24 |
| Finished | Sep 09 06:45:41 PM UTC 24 |
| Peak memory | 268916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608476467 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.608476467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.2655621720 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 21856600 ps |
| CPU time | 23.64 seconds |
| Started | Sep 09 06:45:18 PM UTC 24 |
| Finished | Sep 09 06:45:43 PM UTC 24 |
| Peak memory | 284436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655621720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.2655621720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.672868743 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 13997000 ps |
| CPU time | 31.81 seconds |
| Started | Sep 09 06:45:17 PM UTC 24 |
| Finished | Sep 09 06:45:50 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=672868743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c trl_disable.672868743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.705389028 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 4942618600 ps |
| CPU time | 100.58 seconds |
| Started | Sep 09 06:45:04 PM UTC 24 |
| Finished | Sep 09 06:46:46 PM UTC 24 |
| Peak memory | 270684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705389028 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.705389028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.1747172245 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 7090698000 ps |
| CPU time | 147.12 seconds |
| Started | Sep 09 06:45:07 PM UTC 24 |
| Finished | Sep 09 06:47:37 PM UTC 24 |
| Peak memory | 301748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747172245 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.1747172245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.163035866 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 12131742500 ps |
| CPU time | 339.92 seconds |
| Started | Sep 09 06:45:08 PM UTC 24 |
| Finished | Sep 09 06:50:53 PM UTC 24 |
| Peak memory | 303744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=163035866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 36.flash_ctrl_intr_rd_slow_flash.163035866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.1003298997 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 70793300 ps |
| CPU time | 200.17 seconds |
| Started | Sep 09 06:45:05 PM UTC 24 |
| Finished | Sep 09 06:48:28 PM UTC 24 |
| Peak memory | 275060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003298997 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.1003298997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.2157640177 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 52523700 ps |
| CPU time | 43.51 seconds |
| Started | Sep 09 06:45:10 PM UTC 24 |
| Finished | Sep 09 06:45:55 PM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157640177 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.2157640177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.3362981028 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 41905400 ps |
| CPU time | 41.66 seconds |
| Started | Sep 09 06:45:12 PM UTC 24 |
| Finished | Sep 09 06:45:56 PM UTC 24 |
| Peak memory | 285472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3362981028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c trl_rw_evict_all_en.3362981028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.2615986418 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 8703238600 ps |
| CPU time | 88.01 seconds |
| Started | Sep 09 06:45:18 PM UTC 24 |
| Finished | Sep 09 06:46:48 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615986418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2615986418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.1178516354 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 294786500 ps |
| CPU time | 184.66 seconds |
| Started | Sep 09 06:45:03 PM UTC 24 |
| Finished | Sep 09 06:48:10 PM UTC 24 |
| Peak memory | 287240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178516354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.1178516354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.4016387937 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 82022500 ps |
| CPU time | 28.73 seconds |
| Started | Sep 09 06:45:48 PM UTC 24 |
| Finished | Sep 09 06:46:18 PM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016387937 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.4016387937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.3881514814 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 146482600 ps |
| CPU time | 30.54 seconds |
| Started | Sep 09 06:45:43 PM UTC 24 |
| Finished | Sep 09 06:46:15 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881514814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3881514814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.2949449802 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 23434600 ps |
| CPU time | 31.75 seconds |
| Started | Sep 09 06:45:40 PM UTC 24 |
| Finished | Sep 09 06:46:13 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2949449802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ ctrl_disable.2949449802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.2235955961 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 1274431700 ps |
| CPU time | 65.51 seconds |
| Started | Sep 09 06:45:30 PM UTC 24 |
| Finished | Sep 09 06:46:38 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235955961 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.2235955961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.2549296558 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 3773701100 ps |
| CPU time | 188.79 seconds |
| Started | Sep 09 06:45:33 PM UTC 24 |
| Finished | Sep 09 06:48:46 PM UTC 24 |
| Peak memory | 301748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549296558 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.2549296558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.676468618 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 14061839100 ps |
| CPU time | 190.9 seconds |
| Started | Sep 09 06:45:36 PM UTC 24 |
| Finished | Sep 09 06:48:50 PM UTC 24 |
| Peak memory | 303716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=676468618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 37.flash_ctrl_intr_rd_slow_flash.676468618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.186193188 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 38524800 ps |
| CPU time | 167.1 seconds |
| Started | Sep 09 06:45:31 PM UTC 24 |
| Finished | Sep 09 06:48:22 PM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186193188 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.186193188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.667722221 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 47802500 ps |
| CPU time | 37.13 seconds |
| Started | Sep 09 06:45:37 PM UTC 24 |
| Finished | Sep 09 06:46:15 PM UTC 24 |
| Peak memory | 285412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667722221 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.667722221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.816403075 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 31074000 ps |
| CPU time | 48.18 seconds |
| Started | Sep 09 06:45:37 PM UTC 24 |
| Finished | Sep 09 06:46:27 PM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=816403075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ct rl_rw_evict_all_en.816403075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.1797084739 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 1630433500 ps |
| CPU time | 72.02 seconds |
| Started | Sep 09 06:45:42 PM UTC 24 |
| Finished | Sep 09 06:46:56 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797084739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1797084739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.1318999718 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 198076800 ps |
| CPU time | 209.86 seconds |
| Started | Sep 09 06:45:29 PM UTC 24 |
| Finished | Sep 09 06:49:02 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318999718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.1318999718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.3929910409 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 275291700 ps |
| CPU time | 25.16 seconds |
| Started | Sep 09 06:46:14 PM UTC 24 |
| Finished | Sep 09 06:46:41 PM UTC 24 |
| Peak memory | 268936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929910409 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.3929910409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.3505538467 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 13573900 ps |
| CPU time | 22.68 seconds |
| Started | Sep 09 06:46:13 PM UTC 24 |
| Finished | Sep 09 06:46:37 PM UTC 24 |
| Peak memory | 294676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505538467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3505538467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.549413128 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 14760600 ps |
| CPU time | 28.91 seconds |
| Started | Sep 09 06:46:02 PM UTC 24 |
| Finished | Sep 09 06:46:32 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=549413128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c trl_disable.549413128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.3890668828 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2856749300 ps |
| CPU time | 89.76 seconds |
| Started | Sep 09 06:45:51 PM UTC 24 |
| Finished | Sep 09 06:47:23 PM UTC 24 |
| Peak memory | 272732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890668828 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.3890668828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.3517487718 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 14540756600 ps |
| CPU time | 193.3 seconds |
| Started | Sep 09 06:45:57 PM UTC 24 |
| Finished | Sep 09 06:49:13 PM UTC 24 |
| Peak memory | 293548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517487718 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.3517487718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1125525548 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 12500399100 ps |
| CPU time | 309.97 seconds |
| Started | Sep 09 06:45:57 PM UTC 24 |
| Finished | Sep 09 06:51:11 PM UTC 24 |
| Peak memory | 301700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1125525548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 38.flash_ctrl_intr_rd_slow_flash.1125525548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.3168864570 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 37520200 ps |
| CPU time | 187.1 seconds |
| Started | Sep 09 06:45:52 PM UTC 24 |
| Finished | Sep 09 06:49:03 PM UTC 24 |
| Peak memory | 270964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168864570 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.3168864570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.600526705 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 58872600 ps |
| CPU time | 46.33 seconds |
| Started | Sep 09 06:45:59 PM UTC 24 |
| Finished | Sep 09 06:46:47 PM UTC 24 |
| Peak memory | 287356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600526705 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.600526705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.35346701 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 32548200 ps |
| CPU time | 36.25 seconds |
| Started | Sep 09 06:46:01 PM UTC 24 |
| Finished | Sep 09 06:46:39 PM UTC 24 |
| Peak memory | 281312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=35346701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctr l_rw_evict_all_en.35346701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.2060412490 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 3329264500 ps |
| CPU time | 69.26 seconds |
| Started | Sep 09 06:46:08 PM UTC 24 |
| Finished | Sep 09 06:47:19 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060412490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2060412490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.2476960825 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 51884200 ps |
| CPU time | 288.12 seconds |
| Started | Sep 09 06:45:51 PM UTC 24 |
| Finished | Sep 09 06:50:43 PM UTC 24 |
| Peak memory | 291336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476960825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.2476960825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.1151176958 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 68271200 ps |
| CPU time | 22.97 seconds |
| Started | Sep 09 06:46:34 PM UTC 24 |
| Finished | Sep 09 06:46:58 PM UTC 24 |
| Peak memory | 268932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151176958 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.1151176958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.495683733 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 15753500 ps |
| CPU time | 19.82 seconds |
| Started | Sep 09 06:46:31 PM UTC 24 |
| Finished | Sep 09 06:46:52 PM UTC 24 |
| Peak memory | 294612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495683733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.495683733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.2398516977 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 25559200 ps |
| CPU time | 37.77 seconds |
| Started | Sep 09 06:46:19 PM UTC 24 |
| Finished | Sep 09 06:46:58 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2398516977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ ctrl_disable.2398516977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.860559159 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 1089716000 ps |
| CPU time | 43.57 seconds |
| Started | Sep 09 06:46:16 PM UTC 24 |
| Finished | Sep 09 06:47:01 PM UTC 24 |
| Peak memory | 275100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860559159 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.860559159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.3337982961 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 1309216400 ps |
| CPU time | 163.3 seconds |
| Started | Sep 09 06:46:17 PM UTC 24 |
| Finished | Sep 09 06:49:03 PM UTC 24 |
| Peak memory | 301772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337982961 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.3337982961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3543934146 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 5989633600 ps |
| CPU time | 141.47 seconds |
| Started | Sep 09 06:46:17 PM UTC 24 |
| Finished | Sep 09 06:48:41 PM UTC 24 |
| Peak memory | 303716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3543934146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.flash_ctrl_intr_rd_slow_flash.3543934146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.634802658 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 41226700 ps |
| CPU time | 200.9 seconds |
| Started | Sep 09 06:46:16 PM UTC 24 |
| Finished | Sep 09 06:49:40 PM UTC 24 |
| Peak memory | 270964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634802658 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.634802658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.397010356 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 63769700 ps |
| CPU time | 58.93 seconds |
| Started | Sep 09 06:46:19 PM UTC 24 |
| Finished | Sep 09 06:47:20 PM UTC 24 |
| Peak memory | 287552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397010356 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.397010356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.925393427 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 30492900 ps |
| CPU time | 34.89 seconds |
| Started | Sep 09 06:46:19 PM UTC 24 |
| Finished | Sep 09 06:46:55 PM UTC 24 |
| Peak memory | 281272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=925393427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ct rl_rw_evict_all_en.925393427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.1133599756 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4080989200 ps |
| CPU time | 93.37 seconds |
| Started | Sep 09 06:46:27 PM UTC 24 |
| Finished | Sep 09 06:48:03 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133599756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1133599756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.2961169354 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 98778100 ps |
| CPU time | 146.73 seconds |
| Started | Sep 09 06:46:16 PM UTC 24 |
| Finished | Sep 09 06:48:45 PM UTC 24 |
| Peak memory | 287500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961169354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.2961169354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.2713898568 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 154779700 ps |
| CPU time | 19.92 seconds |
| Started | Sep 09 05:55:52 PM UTC 24 |
| Finished | Sep 09 05:56:13 PM UTC 24 |
| Peak memory | 268912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713898568 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.2713898568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1214474081 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 71973300 ps |
| CPU time | 16.93 seconds |
| Started | Sep 09 05:55:43 PM UTC 24 |
| Finished | Sep 09 05:56:01 PM UTC 24 |
| Peak memory | 272952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214474081 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.1214474081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.1772479535 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 13725500 ps |
| CPU time | 24.24 seconds |
| Started | Sep 09 05:55:17 PM UTC 24 |
| Finished | Sep 09 05:55:43 PM UTC 24 |
| Peak memory | 294676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772479535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1772479535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3328679513 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 789353400 ps |
| CPU time | 243.28 seconds |
| Started | Sep 09 05:53:54 PM UTC 24 |
| Finished | Sep 09 05:58:00 PM UTC 24 |
| Peak memory | 289716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3328679513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_derr_detect.3328679513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.3999616267 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 10705200 ps |
| CPU time | 39.35 seconds |
| Started | Sep 09 05:55:07 PM UTC 24 |
| Finished | Sep 09 05:55:48 PM UTC 24 |
| Peak memory | 285392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3999616267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_disable.3999616267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.1092185872 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 5572289400 ps |
| CPU time | 416.48 seconds |
| Started | Sep 09 05:51:48 PM UTC 24 |
| Finished | Sep 09 05:58:49 PM UTC 24 |
| Peak memory | 274908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092185872 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1092185872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.1226461880 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 21499315200 ps |
| CPU time | 2740.19 seconds |
| Started | Sep 09 05:52:26 PM UTC 24 |
| Finished | Sep 09 06:38:33 PM UTC 24 |
| Peak memory | 277608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226461880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.1226461880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.3760339783 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3280689800 ps |
| CPU time | 1065.22 seconds |
| Started | Sep 09 05:52:19 PM UTC 24 |
| Finished | Sep 09 06:10:15 PM UTC 24 |
| Peak memory | 285156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760339783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3760339783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.3589540089 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 231238100 ps |
| CPU time | 28.02 seconds |
| Started | Sep 09 05:52:01 PM UTC 24 |
| Finished | Sep 09 05:52:31 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35 89540089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc h_code.3589540089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.677185139 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 125212840700 ps |
| CPU time | 3653.53 seconds |
| Started | Sep 09 05:52:08 PM UTC 24 |
| Finished | Sep 09 06:53:40 PM UTC 24 |
| Peak memory | 277520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677185139 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.677185139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1592321932 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 74125300 ps |
| CPU time | 194.33 seconds |
| Started | Sep 09 05:51:40 PM UTC 24 |
| Finished | Sep 09 05:54:57 PM UTC 24 |
| Peak memory | 274952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592321932 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1592321932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.159110764 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 10035434900 ps |
| CPU time | 89.76 seconds |
| Started | Sep 09 05:55:49 PM UTC 24 |
| Finished | Sep 09 05:57:20 PM UTC 24 |
| Peak memory | 277264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=159110764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.159110764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.1222620753 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 46330300 ps |
| CPU time | 24.49 seconds |
| Started | Sep 09 05:55:48 PM UTC 24 |
| Finished | Sep 09 05:56:14 PM UTC 24 |
| Peak memory | 270948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1222620753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.1222620753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.2696559880 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 50128252400 ps |
| CPU time | 958.14 seconds |
| Started | Sep 09 05:51:49 PM UTC 24 |
| Finished | Sep 09 06:07:58 PM UTC 24 |
| Peak memory | 275004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696559880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.2696559880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.1357294376 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1431501100 ps |
| CPU time | 147.06 seconds |
| Started | Sep 09 05:51:47 PM UTC 24 |
| Finished | Sep 09 05:54:16 PM UTC 24 |
| Peak memory | 275100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357294376 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.1357294376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.602315595 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 3670358900 ps |
| CPU time | 458.06 seconds |
| Started | Sep 09 05:54:17 PM UTC 24 |
| Finished | Sep 09 06:02:01 PM UTC 24 |
| Peak memory | 328376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=602315595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integrity.602315595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1353395887 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5942326000 ps |
| CPU time | 177.31 seconds |
| Started | Sep 09 05:54:31 PM UTC 24 |
| Finished | Sep 09 05:57:31 PM UTC 24 |
| Peak memory | 305760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1353395887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_intr_rd_slow_flash.1353395887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.1378388805 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2669184500 ps |
| CPU time | 69.86 seconds |
| Started | Sep 09 05:54:19 PM UTC 24 |
| Finished | Sep 09 05:55:31 PM UTC 24 |
| Peak memory | 275008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378388805 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.1378388805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1117612610 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 35499698200 ps |
| CPU time | 193.75 seconds |
| Started | Sep 09 05:54:35 PM UTC 24 |
| Finished | Sep 09 05:57:52 PM UTC 24 |
| Peak memory | 270960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117612610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1117612610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.3602010185 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 6097648900 ps |
| CPU time | 76.96 seconds |
| Started | Sep 09 05:52:32 PM UTC 24 |
| Finished | Sep 09 05:53:51 PM UTC 24 |
| Peak memory | 274752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602010185 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3602010185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.2586007530 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 15315500 ps |
| CPU time | 23.58 seconds |
| Started | Sep 09 05:55:45 PM UTC 24 |
| Finished | Sep 09 05:56:10 PM UTC 24 |
| Peak memory | 275396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2586007530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_lcmgr_intg.2586007530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.3077782859 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 922857900 ps |
| CPU time | 115.09 seconds |
| Started | Sep 09 05:52:43 PM UTC 24 |
| Finished | Sep 09 05:54:40 PM UTC 24 |
| Peak memory | 270892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077782859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3077782859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.1295260571 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3845873000 ps |
| CPU time | 212.52 seconds |
| Started | Sep 09 05:51:57 PM UTC 24 |
| Finished | Sep 09 05:55:33 PM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1295260571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.1295260571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1820466398 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 88671000 ps |
| CPU time | 199.4 seconds |
| Started | Sep 09 05:51:52 PM UTC 24 |
| Finished | Sep 09 05:55:15 PM UTC 24 |
| Peak memory | 270960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820466398 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.1820466398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.2349152661 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 136738300 ps |
| CPU time | 201.1 seconds |
| Started | Sep 09 05:51:47 PM UTC 24 |
| Finished | Sep 09 05:55:11 PM UTC 24 |
| Peak memory | 274908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349152661 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.2349152661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.2145828929 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 4654789800 ps |
| CPU time | 194.99 seconds |
| Started | Sep 09 05:54:41 PM UTC 24 |
| Finished | Sep 09 05:57:59 PM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145828929 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.2145828929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.1861993747 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 479214900 ps |
| CPU time | 1079.64 seconds |
| Started | Sep 09 05:51:28 PM UTC 24 |
| Finished | Sep 09 06:09:39 PM UTC 24 |
| Peak memory | 293384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861993747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.1861993747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.3464724584 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 763830800 ps |
| CPU time | 155.3 seconds |
| Started | Sep 09 05:51:41 PM UTC 24 |
| Finished | Sep 09 05:54:18 PM UTC 24 |
| Peak memory | 272908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464724584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3464724584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.1303969858 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 63881400 ps |
| CPU time | 61.6 seconds |
| Started | Sep 09 05:55:07 PM UTC 24 |
| Finished | Sep 09 05:56:10 PM UTC 24 |
| Peak memory | 283260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303969858 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.1303969858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.2348473879 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 31629800 ps |
| CPU time | 33.67 seconds |
| Started | Sep 09 05:53:41 PM UTC 24 |
| Finished | Sep 09 05:54:16 PM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2348473879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_read_word_sweep_derr.2348473879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.3286964051 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 161147600 ps |
| CPU time | 37.82 seconds |
| Started | Sep 09 05:53:00 PM UTC 24 |
| Finished | Sep 09 05:53:40 PM UTC 24 |
| Peak memory | 275124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286964051 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.3286964051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.469065461 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1131055100 ps |
| CPU time | 151.28 seconds |
| Started | Sep 09 05:52:47 PM UTC 24 |
| Finished | Sep 09 05:55:21 PM UTC 24 |
| Peak memory | 291780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=469065461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.469065461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.3161976382 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2615828900 ps |
| CPU time | 160.43 seconds |
| Started | Sep 09 05:53:02 PM UTC 24 |
| Finished | Sep 09 05:55:45 PM UTC 24 |
| Peak memory | 305868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3161976382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_ro_serr.3161976382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2668328284 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 5188494400 ps |
| CPU time | 212.51 seconds |
| Started | Sep 09 05:53:51 PM UTC 24 |
| Finished | Sep 09 05:57:27 PM UTC 24 |
| Peak memory | 295616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2668328284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 4.flash_ctrl_rw_derr.2668328284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.302281389 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 69012800 ps |
| CPU time | 52.7 seconds |
| Started | Sep 09 05:54:44 PM UTC 24 |
| Finished | Sep 09 05:55:38 PM UTC 24 |
| Peak memory | 287352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302281389 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.302281389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.558607476 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 42704600 ps |
| CPU time | 48.06 seconds |
| Started | Sep 09 05:54:58 PM UTC 24 |
| Finished | Sep 09 05:55:47 PM UTC 24 |
| Peak memory | 281532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=558607476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctr l_rw_evict_all_en.558607476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.2259512716 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1786141300 ps |
| CPU time | 236.76 seconds |
| Started | Sep 09 05:53:09 PM UTC 24 |
| Finished | Sep 09 05:57:09 PM UTC 24 |
| Peak memory | 291524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2259512716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.2259512716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.2556556510 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3750303300 ps |
| CPU time | 6473.48 seconds |
| Started | Sep 09 05:55:08 PM UTC 24 |
| Finished | Sep 09 07:44:08 PM UTC 24 |
| Peak memory | 316200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556556510 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.2556556510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.469469252 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 886478700 ps |
| CPU time | 76.73 seconds |
| Started | Sep 09 05:55:12 PM UTC 24 |
| Finished | Sep 09 05:56:31 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469469252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.469469252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.2798136090 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 434068000 ps |
| CPU time | 61.24 seconds |
| Started | Sep 09 05:53:40 PM UTC 24 |
| Finished | Sep 09 05:54:43 PM UTC 24 |
| Peak memory | 275444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279 8136090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser r_address.2798136090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.1956957297 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1024455400 ps |
| CPU time | 98.54 seconds |
| Started | Sep 09 05:53:36 PM UTC 24 |
| Finished | Sep 09 05:55:17 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19 56957297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_se rr_counter.1956957297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.1053056019 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 34009300 ps |
| CPU time | 136.35 seconds |
| Started | Sep 09 05:51:24 PM UTC 24 |
| Finished | Sep 09 05:53:43 PM UTC 24 |
| Peak memory | 287244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053056019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1053056019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.2464421339 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 17858000 ps |
| CPU time | 43.91 seconds |
| Started | Sep 09 05:51:26 PM UTC 24 |
| Finished | Sep 09 05:52:12 PM UTC 24 |
| Peak memory | 270616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464421339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.2464421339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.2498890933 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 2225297200 ps |
| CPU time | 997.42 seconds |
| Started | Sep 09 05:55:15 PM UTC 24 |
| Finished | Sep 09 06:12:03 PM UTC 24 |
| Peak memory | 293344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498890933 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.2498890933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.3737825439 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 39300000 ps |
| CPU time | 32.17 seconds |
| Started | Sep 09 05:51:33 PM UTC 24 |
| Finished | Sep 09 05:52:07 PM UTC 24 |
| Peak memory | 272988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737825439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.3737825439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.2612911905 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2600581700 ps |
| CPU time | 141.64 seconds |
| Started | Sep 09 05:52:43 PM UTC 24 |
| Finished | Sep 09 05:55:07 PM UTC 24 |
| Peak memory | 275040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2612911905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.2612911905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.1970090351 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 30404900 ps |
| CPU time | 24.18 seconds |
| Started | Sep 09 06:46:47 PM UTC 24 |
| Finished | Sep 09 06:47:13 PM UTC 24 |
| Peak memory | 268916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970090351 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.1970090351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.3079822934 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 85991500 ps |
| CPU time | 19.76 seconds |
| Started | Sep 09 06:46:47 PM UTC 24 |
| Finished | Sep 09 06:47:08 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079822934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3079822934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.434586153 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 15071000 ps |
| CPU time | 32.79 seconds |
| Started | Sep 09 06:46:42 PM UTC 24 |
| Finished | Sep 09 06:47:16 PM UTC 24 |
| Peak memory | 285296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=434586153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_c trl_disable.434586153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.1016212535 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 25474619800 ps |
| CPU time | 155.32 seconds |
| Started | Sep 09 06:46:39 PM UTC 24 |
| Finished | Sep 09 06:49:17 PM UTC 24 |
| Peak memory | 270680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016212535 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.1016212535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.582011365 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 39671300 ps |
| CPU time | 172.67 seconds |
| Started | Sep 09 06:46:40 PM UTC 24 |
| Finished | Sep 09 06:49:35 PM UTC 24 |
| Peak memory | 274736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582011365 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.582011365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.2878147205 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 694158200 ps |
| CPU time | 58.73 seconds |
| Started | Sep 09 06:46:45 PM UTC 24 |
| Finished | Sep 09 06:47:45 PM UTC 24 |
| Peak memory | 274916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878147205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2878147205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.3698058112 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 18217200 ps |
| CPU time | 62.56 seconds |
| Started | Sep 09 06:46:38 PM UTC 24 |
| Finished | Sep 09 06:47:42 PM UTC 24 |
| Peak memory | 283148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698058112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.3698058112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.3731451397 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 114534600 ps |
| CPU time | 23.95 seconds |
| Started | Sep 09 06:46:59 PM UTC 24 |
| Finished | Sep 09 06:47:24 PM UTC 24 |
| Peak memory | 268920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731451397 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.3731451397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.3202200089 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 14641000 ps |
| CPU time | 25.03 seconds |
| Started | Sep 09 06:46:57 PM UTC 24 |
| Finished | Sep 09 06:47:23 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202200089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.3202200089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.376341087 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 38924600 ps |
| CPU time | 30.24 seconds |
| Started | Sep 09 06:46:54 PM UTC 24 |
| Finished | Sep 09 06:47:25 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=376341087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_c trl_disable.376341087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.615867505 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 3283229600 ps |
| CPU time | 68.44 seconds |
| Started | Sep 09 06:46:50 PM UTC 24 |
| Finished | Sep 09 06:48:00 PM UTC 24 |
| Peak memory | 275096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615867505 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.615867505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.150037549 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 82844600 ps |
| CPU time | 153.95 seconds |
| Started | Sep 09 06:46:54 PM UTC 24 |
| Finished | Sep 09 06:49:30 PM UTC 24 |
| Peak memory | 270960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150037549 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.150037549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.837169791 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 350141600 ps |
| CPU time | 59.44 seconds |
| Started | Sep 09 06:46:56 PM UTC 24 |
| Finished | Sep 09 06:47:57 PM UTC 24 |
| Peak memory | 274784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837169791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.837169791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.2071861385 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 118926500 ps |
| CPU time | 198.36 seconds |
| Started | Sep 09 06:46:48 PM UTC 24 |
| Finished | Sep 09 06:50:10 PM UTC 24 |
| Peak memory | 287560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071861385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2071861385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.1135880777 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 316365300 ps |
| CPU time | 28.55 seconds |
| Started | Sep 09 06:47:14 PM UTC 24 |
| Finished | Sep 09 06:47:44 PM UTC 24 |
| Peak memory | 268908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135880777 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.1135880777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.4045535892 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 22172900 ps |
| CPU time | 20.72 seconds |
| Started | Sep 09 06:47:09 PM UTC 24 |
| Finished | Sep 09 06:47:31 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045535892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.4045535892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.3730586730 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 74912800 ps |
| CPU time | 42.54 seconds |
| Started | Sep 09 06:47:01 PM UTC 24 |
| Finished | Sep 09 06:47:45 PM UTC 24 |
| Peak memory | 285324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3730586730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ ctrl_disable.3730586730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.1844939049 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 1979012500 ps |
| CPU time | 72.64 seconds |
| Started | Sep 09 06:46:59 PM UTC 24 |
| Finished | Sep 09 06:48:14 PM UTC 24 |
| Peak memory | 274784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844939049 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.1844939049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.3399303551 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 140605800 ps |
| CPU time | 164.06 seconds |
| Started | Sep 09 06:47:01 PM UTC 24 |
| Finished | Sep 09 06:49:48 PM UTC 24 |
| Peak memory | 274988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399303551 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.3399303551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.2444577780 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 650833400 ps |
| CPU time | 67.28 seconds |
| Started | Sep 09 06:47:08 PM UTC 24 |
| Finished | Sep 09 06:48:17 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444577780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2444577780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.3466917514 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 47740300 ps |
| CPU time | 97.67 seconds |
| Started | Sep 09 06:46:59 PM UTC 24 |
| Finished | Sep 09 06:48:39 PM UTC 24 |
| Peak memory | 285452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466917514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3466917514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.2357314767 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 33326500 ps |
| CPU time | 28.67 seconds |
| Started | Sep 09 06:47:24 PM UTC 24 |
| Finished | Sep 09 06:47:54 PM UTC 24 |
| Peak memory | 268920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357314767 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.2357314767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.3452022534 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 15835700 ps |
| CPU time | 18.83 seconds |
| Started | Sep 09 06:47:24 PM UTC 24 |
| Finished | Sep 09 06:47:44 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452022534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3452022534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.92238772 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 16400400 ps |
| CPU time | 33.11 seconds |
| Started | Sep 09 06:47:20 PM UTC 24 |
| Finished | Sep 09 06:47:56 PM UTC 24 |
| Peak memory | 285556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=92238772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ct rl_disable.92238772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.3155139345 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 1255152000 ps |
| CPU time | 62.45 seconds |
| Started | Sep 09 06:47:18 PM UTC 24 |
| Finished | Sep 09 06:48:22 PM UTC 24 |
| Peak memory | 272732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155139345 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.3155139345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.187511045 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 72215200 ps |
| CPU time | 171.71 seconds |
| Started | Sep 09 06:47:20 PM UTC 24 |
| Finished | Sep 09 06:50:16 PM UTC 24 |
| Peak memory | 270784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187511045 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.187511045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.3389798249 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 99402800 ps |
| CPU time | 218.27 seconds |
| Started | Sep 09 06:47:17 PM UTC 24 |
| Finished | Sep 09 06:50:59 PM UTC 24 |
| Peak memory | 291340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389798249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.3389798249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.1210837916 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 40066000 ps |
| CPU time | 23.7 seconds |
| Started | Sep 09 06:47:44 PM UTC 24 |
| Finished | Sep 09 06:48:09 PM UTC 24 |
| Peak memory | 275076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210837916 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.1210837916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.4290967035 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 16979100 ps |
| CPU time | 30.74 seconds |
| Started | Sep 09 06:47:42 PM UTC 24 |
| Finished | Sep 09 06:48:14 PM UTC 24 |
| Peak memory | 294676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290967035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.4290967035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.2244222255 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 11240500 ps |
| CPU time | 43.21 seconds |
| Started | Sep 09 06:47:31 PM UTC 24 |
| Finished | Sep 09 06:48:16 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2244222255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ ctrl_disable.2244222255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.3295692568 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 3681008800 ps |
| CPU time | 135.92 seconds |
| Started | Sep 09 06:47:25 PM UTC 24 |
| Finished | Sep 09 06:49:44 PM UTC 24 |
| Peak memory | 274784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295692568 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.3295692568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.2018442260 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 85632000 ps |
| CPU time | 171.97 seconds |
| Started | Sep 09 06:47:26 PM UTC 24 |
| Finished | Sep 09 06:50:21 PM UTC 24 |
| Peak memory | 270788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018442260 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.2018442260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.4151555470 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 1639165500 ps |
| CPU time | 76.55 seconds |
| Started | Sep 09 06:47:37 PM UTC 24 |
| Finished | Sep 09 06:48:56 PM UTC 24 |
| Peak memory | 274784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151555470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.4151555470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.367869360 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 81777800 ps |
| CPU time | 126.85 seconds |
| Started | Sep 09 06:47:25 PM UTC 24 |
| Finished | Sep 09 06:49:34 PM UTC 24 |
| Peak memory | 286780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367869360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.367869360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.2020557261 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 51698700 ps |
| CPU time | 28.55 seconds |
| Started | Sep 09 06:47:56 PM UTC 24 |
| Finished | Sep 09 06:48:26 PM UTC 24 |
| Peak memory | 275056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020557261 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.2020557261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.4017760099 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 16963100 ps |
| CPU time | 24.14 seconds |
| Started | Sep 09 06:47:55 PM UTC 24 |
| Finished | Sep 09 06:48:21 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017760099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.4017760099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.2653581689 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 36689200 ps |
| CPU time | 34.49 seconds |
| Started | Sep 09 06:47:48 PM UTC 24 |
| Finished | Sep 09 06:48:24 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2653581689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ ctrl_disable.2653581689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.3113855799 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 8287668500 ps |
| CPU time | 84.49 seconds |
| Started | Sep 09 06:47:46 PM UTC 24 |
| Finished | Sep 09 06:49:12 PM UTC 24 |
| Peak memory | 270944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113855799 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.3113855799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.797148225 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 42520400 ps |
| CPU time | 167.91 seconds |
| Started | Sep 09 06:47:47 PM UTC 24 |
| Finished | Sep 09 06:50:37 PM UTC 24 |
| Peak memory | 270644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797148225 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.797148225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.2386971934 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1576551900 ps |
| CPU time | 68.38 seconds |
| Started | Sep 09 06:47:50 PM UTC 24 |
| Finished | Sep 09 06:49:00 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386971934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2386971934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.1217816746 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 91407700 ps |
| CPU time | 102.28 seconds |
| Started | Sep 09 06:47:45 PM UTC 24 |
| Finished | Sep 09 06:49:29 PM UTC 24 |
| Peak memory | 277260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217816746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1217816746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.2466317360 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 32094700 ps |
| CPU time | 21.92 seconds |
| Started | Sep 09 06:48:14 PM UTC 24 |
| Finished | Sep 09 06:48:37 PM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466317360 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.2466317360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.3913562956 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 39074200 ps |
| CPU time | 24.08 seconds |
| Started | Sep 09 06:48:11 PM UTC 24 |
| Finished | Sep 09 06:48:36 PM UTC 24 |
| Peak memory | 294612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913562956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.3913562956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.1934124359 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 20998400 ps |
| CPU time | 34.8 seconds |
| Started | Sep 09 06:48:09 PM UTC 24 |
| Finished | Sep 09 06:48:45 PM UTC 24 |
| Peak memory | 285360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1934124359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ ctrl_disable.1934124359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.3505576832 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 7091901300 ps |
| CPU time | 90.67 seconds |
| Started | Sep 09 06:48:01 PM UTC 24 |
| Finished | Sep 09 06:49:33 PM UTC 24 |
| Peak memory | 270676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505576832 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.3505576832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.2204076369 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 96547400 ps |
| CPU time | 180.66 seconds |
| Started | Sep 09 06:48:04 PM UTC 24 |
| Finished | Sep 09 06:51:07 PM UTC 24 |
| Peak memory | 270960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204076369 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.2204076369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.1732177868 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 460542900 ps |
| CPU time | 62.01 seconds |
| Started | Sep 09 06:48:10 PM UTC 24 |
| Finished | Sep 09 06:49:14 PM UTC 24 |
| Peak memory | 275044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732177868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1732177868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.2001527172 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 82518600 ps |
| CPU time | 184.81 seconds |
| Started | Sep 09 06:47:57 PM UTC 24 |
| Finished | Sep 09 06:51:05 PM UTC 24 |
| Peak memory | 289292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001527172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2001527172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.740104744 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 30219200 ps |
| CPU time | 29.63 seconds |
| Started | Sep 09 06:48:25 PM UTC 24 |
| Finished | Sep 09 06:48:56 PM UTC 24 |
| Peak memory | 268916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740104744 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.740104744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.4107717997 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 31745400 ps |
| CPU time | 28.01 seconds |
| Started | Sep 09 06:48:23 PM UTC 24 |
| Finished | Sep 09 06:48:52 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107717997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.4107717997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.3639534840 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 10708000 ps |
| CPU time | 36.25 seconds |
| Started | Sep 09 06:48:22 PM UTC 24 |
| Finished | Sep 09 06:48:59 PM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3639534840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ ctrl_disable.3639534840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.3614135924 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 10461512500 ps |
| CPU time | 91.95 seconds |
| Started | Sep 09 06:48:17 PM UTC 24 |
| Finished | Sep 09 06:49:51 PM UTC 24 |
| Peak memory | 274756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614135924 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.3614135924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.2993863035 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 69727200 ps |
| CPU time | 182.14 seconds |
| Started | Sep 09 06:48:17 PM UTC 24 |
| Finished | Sep 09 06:51:22 PM UTC 24 |
| Peak memory | 271048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993863035 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.2993863035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.4194268212 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 677456300 ps |
| CPU time | 83.42 seconds |
| Started | Sep 09 06:48:23 PM UTC 24 |
| Finished | Sep 09 06:49:48 PM UTC 24 |
| Peak memory | 274784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194268212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.4194268212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1449918078 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 33493800 ps |
| CPU time | 74.88 seconds |
| Started | Sep 09 06:48:15 PM UTC 24 |
| Finished | Sep 09 06:49:32 PM UTC 24 |
| Peak memory | 283100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449918078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.1449918078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.1160527334 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 127520500 ps |
| CPU time | 15.3 seconds |
| Started | Sep 09 06:48:40 PM UTC 24 |
| Finished | Sep 09 06:48:56 PM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160527334 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.1160527334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.3535575334 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 14136700 ps |
| CPU time | 16.94 seconds |
| Started | Sep 09 06:48:39 PM UTC 24 |
| Finished | Sep 09 06:48:57 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535575334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3535575334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.1392931934 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 12749500 ps |
| CPU time | 38.45 seconds |
| Started | Sep 09 06:48:32 PM UTC 24 |
| Finished | Sep 09 06:49:12 PM UTC 24 |
| Peak memory | 285524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1392931934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ ctrl_disable.1392931934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.1481911925 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 26765448600 ps |
| CPU time | 279.35 seconds |
| Started | Sep 09 06:48:29 PM UTC 24 |
| Finished | Sep 09 06:53:13 PM UTC 24 |
| Peak memory | 272732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481911925 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.1481911925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.196290997 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 40959100 ps |
| CPU time | 154.24 seconds |
| Started | Sep 09 06:48:32 PM UTC 24 |
| Finished | Sep 09 06:51:09 PM UTC 24 |
| Peak memory | 270788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196290997 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.196290997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.946632487 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 952366400 ps |
| CPU time | 59.26 seconds |
| Started | Sep 09 06:48:37 PM UTC 24 |
| Finished | Sep 09 06:49:38 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946632487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.946632487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.4286306256 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 28290200 ps |
| CPU time | 68.49 seconds |
| Started | Sep 09 06:48:27 PM UTC 24 |
| Finished | Sep 09 06:49:37 PM UTC 24 |
| Peak memory | 283148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286306256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.4286306256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.764124950 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 22150900 ps |
| CPU time | 16 seconds |
| Started | Sep 09 06:48:56 PM UTC 24 |
| Finished | Sep 09 06:49:14 PM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764124950 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.764124950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.1084321316 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 32789800 ps |
| CPU time | 27.74 seconds |
| Started | Sep 09 06:48:53 PM UTC 24 |
| Finished | Sep 09 06:49:22 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084321316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1084321316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.3483687302 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 15709300 ps |
| CPU time | 24.64 seconds |
| Started | Sep 09 06:48:47 PM UTC 24 |
| Finished | Sep 09 06:49:13 PM UTC 24 |
| Peak memory | 285232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3483687302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ ctrl_disable.3483687302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.3672820558 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 2667082700 ps |
| CPU time | 95.94 seconds |
| Started | Sep 09 06:48:46 PM UTC 24 |
| Finished | Sep 09 06:50:24 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672820558 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.3672820558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.3767061985 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 464839100 ps |
| CPU time | 181.03 seconds |
| Started | Sep 09 06:48:46 PM UTC 24 |
| Finished | Sep 09 06:51:50 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767061985 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.3767061985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.3574762052 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 2649854700 ps |
| CPU time | 70.87 seconds |
| Started | Sep 09 06:48:50 PM UTC 24 |
| Finished | Sep 09 06:50:03 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574762052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3574762052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.3732366530 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 446760300 ps |
| CPU time | 227.44 seconds |
| Started | Sep 09 06:48:42 PM UTC 24 |
| Finished | Sep 09 06:52:33 PM UTC 24 |
| Peak memory | 289280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732366530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3732366530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.1103027641 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 121483700 ps |
| CPU time | 21.77 seconds |
| Started | Sep 09 05:59:22 PM UTC 24 |
| Finished | Sep 09 05:59:45 PM UTC 24 |
| Peak memory | 269188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103027641 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1103027641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.3087608581 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 15213800 ps |
| CPU time | 31.8 seconds |
| Started | Sep 09 05:59:00 PM UTC 24 |
| Finished | Sep 09 05:59:33 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087608581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3087608581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.202289730 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 22103100 ps |
| CPU time | 38.09 seconds |
| Started | Sep 09 05:58:41 PM UTC 24 |
| Finished | Sep 09 05:59:21 PM UTC 24 |
| Peak memory | 285292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=202289730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct rl_disable.202289730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.3939191168 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 6064844300 ps |
| CPU time | 3233.79 seconds |
| Started | Sep 09 05:56:31 PM UTC 24 |
| Finished | Sep 09 06:51:00 PM UTC 24 |
| Peak memory | 277676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939191168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.3939191168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2301736036 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 628087600 ps |
| CPU time | 1109.4 seconds |
| Started | Sep 09 05:56:15 PM UTC 24 |
| Finished | Sep 09 06:14:57 PM UTC 24 |
| Peak memory | 283096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301736036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2301736036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.1519313067 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 309906100 ps |
| CPU time | 24.32 seconds |
| Started | Sep 09 05:56:13 PM UTC 24 |
| Finished | Sep 09 05:56:39 PM UTC 24 |
| Peak memory | 272972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15 19313067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetc h_code.1519313067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2024237415 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 10012529800 ps |
| CPU time | 141.16 seconds |
| Started | Sep 09 05:59:21 PM UTC 24 |
| Finished | Sep 09 06:01:45 PM UTC 24 |
| Peak memory | 336692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2024237415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2024237415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3658981865 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 26183200 ps |
| CPU time | 18.6 seconds |
| Started | Sep 09 05:59:19 PM UTC 24 |
| Finished | Sep 09 05:59:39 PM UTC 24 |
| Peak memory | 271016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3658981865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.3658981865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.3247254418 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 160183253300 ps |
| CPU time | 979.62 seconds |
| Started | Sep 09 05:56:10 PM UTC 24 |
| Finished | Sep 09 06:12:41 PM UTC 24 |
| Peak memory | 274752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247254418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.3247254418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.987385650 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2831312800 ps |
| CPU time | 198.62 seconds |
| Started | Sep 09 05:57:32 PM UTC 24 |
| Finished | Sep 09 06:00:55 PM UTC 24 |
| Peak memory | 305832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987385650 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.987385650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.99970491 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 5970022300 ps |
| CPU time | 145.9 seconds |
| Started | Sep 09 05:57:53 PM UTC 24 |
| Finished | Sep 09 06:00:21 PM UTC 24 |
| Peak memory | 304040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=99970491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.flash_ctrl_intr_rd_slow_flash.99970491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1591169371 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 15805786500 ps |
| CPU time | 112.84 seconds |
| Started | Sep 09 05:57:38 PM UTC 24 |
| Finished | Sep 09 05:59:33 PM UTC 24 |
| Peak memory | 275008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591169371 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.1591169371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3388062934 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 33905370200 ps |
| CPU time | 168.97 seconds |
| Started | Sep 09 05:58:01 PM UTC 24 |
| Finished | Sep 09 06:00:53 PM UTC 24 |
| Peak memory | 275048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388062934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3388062934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.733941178 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1264660300 ps |
| CPU time | 84.74 seconds |
| Started | Sep 09 05:56:38 PM UTC 24 |
| Finished | Sep 09 05:58:04 PM UTC 24 |
| Peak memory | 274884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733941178 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.733941178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1042200335 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 15666600 ps |
| CPU time | 24.61 seconds |
| Started | Sep 09 05:59:07 PM UTC 24 |
| Finished | Sep 09 05:59:33 PM UTC 24 |
| Peak memory | 271300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1042200335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_lcmgr_intg.1042200335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.479098823 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 221737930500 ps |
| CPU time | 817.6 seconds |
| Started | Sep 09 05:56:11 PM UTC 24 |
| Finished | Sep 09 06:09:58 PM UTC 24 |
| Peak memory | 283208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=479098823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_mp_regions.479098823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2049090749 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 42884400 ps |
| CPU time | 291.37 seconds |
| Started | Sep 09 05:56:03 PM UTC 24 |
| Finished | Sep 09 06:00:58 PM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049090749 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2049090749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.302321037 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 59546900 ps |
| CPU time | 28.37 seconds |
| Started | Sep 09 05:58:01 PM UTC 24 |
| Finished | Sep 09 05:58:31 PM UTC 24 |
| Peak memory | 274940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302321037 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.302321037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.325095994 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 198583300 ps |
| CPU time | 1078.88 seconds |
| Started | Sep 09 05:56:03 PM UTC 24 |
| Finished | Sep 09 06:14:13 PM UTC 24 |
| Peak memory | 293384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325095994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.325095994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.4180569235 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 82409400 ps |
| CPU time | 47.59 seconds |
| Started | Sep 09 05:58:31 PM UTC 24 |
| Finished | Sep 09 05:59:21 PM UTC 24 |
| Peak memory | 287780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180569235 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.4180569235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.1419962939 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 635038200 ps |
| CPU time | 117.72 seconds |
| Started | Sep 09 05:56:40 PM UTC 24 |
| Finished | Sep 09 05:58:41 PM UTC 24 |
| Peak memory | 303960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1419962939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.1419962939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.2301098729 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 791494000 ps |
| CPU time | 193.15 seconds |
| Started | Sep 09 05:57:21 PM UTC 24 |
| Finished | Sep 09 06:00:38 PM UTC 24 |
| Peak memory | 291764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301098729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.2301098729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.1443581412 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2823591600 ps |
| CPU time | 131.12 seconds |
| Started | Sep 09 05:57:08 PM UTC 24 |
| Finished | Sep 09 05:59:22 PM UTC 24 |
| Peak memory | 291528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1443581412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash _ctrl_ro_serr.1443581412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.2654454888 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 3497033300 ps |
| CPU time | 500.74 seconds |
| Started | Sep 09 05:56:51 PM UTC 24 |
| Finished | Sep 09 06:05:18 PM UTC 24 |
| Peak memory | 324248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654454888 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.2654454888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.2123802205 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 25366643900 ps |
| CPU time | 184.26 seconds |
| Started | Sep 09 05:57:28 PM UTC 24 |
| Finished | Sep 09 06:00:35 PM UTC 24 |
| Peak memory | 291504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2123802205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 5.flash_ctrl_rw_derr.2123802205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.1059387671 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 47033600 ps |
| CPU time | 58.58 seconds |
| Started | Sep 09 05:58:05 PM UTC 24 |
| Finished | Sep 09 05:59:06 PM UTC 24 |
| Peak memory | 281212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059387671 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.1059387671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.2847986919 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 26479700 ps |
| CPU time | 38.38 seconds |
| Started | Sep 09 05:58:19 PM UTC 24 |
| Finished | Sep 09 05:58:59 PM UTC 24 |
| Peak memory | 287424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2847986919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct rl_rw_evict_all_en.2847986919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.4271096752 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 4434069300 ps |
| CPU time | 138.95 seconds |
| Started | Sep 09 05:57:10 PM UTC 24 |
| Finished | Sep 09 05:59:31 PM UTC 24 |
| Peak memory | 305840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4271096752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.4271096752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3855240080 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2641756800 ps |
| CPU time | 96.78 seconds |
| Started | Sep 09 05:58:51 PM UTC 24 |
| Finished | Sep 09 06:00:30 PM UTC 24 |
| Peak memory | 274788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855240080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3855240080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.2126581827 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 39101900 ps |
| CPU time | 203.65 seconds |
| Started | Sep 09 05:56:03 PM UTC 24 |
| Finished | Sep 09 05:59:30 PM UTC 24 |
| Peak memory | 287236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126581827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2126581827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.2406727434 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 18318806500 ps |
| CPU time | 192.67 seconds |
| Started | Sep 09 05:56:40 PM UTC 24 |
| Finished | Sep 09 05:59:56 PM UTC 24 |
| Peak memory | 271176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2406727434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.2406727434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.3249419963 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 15832700 ps |
| CPU time | 18.84 seconds |
| Started | Sep 09 06:48:57 PM UTC 24 |
| Finished | Sep 09 06:49:17 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249419963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3249419963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1364052124 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 69133100 ps |
| CPU time | 137.68 seconds |
| Started | Sep 09 06:48:57 PM UTC 24 |
| Finished | Sep 09 06:51:16 PM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364052124 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.1364052124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.3149476774 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 181523400 ps |
| CPU time | 19.59 seconds |
| Started | Sep 09 06:48:58 PM UTC 24 |
| Finished | Sep 09 06:49:19 PM UTC 24 |
| Peak memory | 294812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149476774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3149476774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.67350381 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 84221400 ps |
| CPU time | 161.88 seconds |
| Started | Sep 09 06:48:58 PM UTC 24 |
| Finished | Sep 09 06:51:42 PM UTC 24 |
| Peak memory | 270956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67350381 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.67350381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.464582806 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 41875500 ps |
| CPU time | 29.05 seconds |
| Started | Sep 09 06:49:01 PM UTC 24 |
| Finished | Sep 09 06:49:31 PM UTC 24 |
| Peak memory | 294808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464582806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.464582806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.1217375636 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 60685700 ps |
| CPU time | 146.97 seconds |
| Started | Sep 09 06:49:00 PM UTC 24 |
| Finished | Sep 09 06:51:29 PM UTC 24 |
| Peak memory | 270776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217375636 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.1217375636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.3534233470 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 24964600 ps |
| CPU time | 23.32 seconds |
| Started | Sep 09 06:49:03 PM UTC 24 |
| Finished | Sep 09 06:49:28 PM UTC 24 |
| Peak memory | 294808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534233470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.3534233470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.175128372 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 127915000 ps |
| CPU time | 165.29 seconds |
| Started | Sep 09 06:49:03 PM UTC 24 |
| Finished | Sep 09 06:51:51 PM UTC 24 |
| Peak memory | 270644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175128372 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.175128372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.3520663239 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 15142800 ps |
| CPU time | 23.15 seconds |
| Started | Sep 09 06:49:13 PM UTC 24 |
| Finished | Sep 09 06:49:38 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520663239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3520663239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3287243814 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 84316100 ps |
| CPU time | 143.39 seconds |
| Started | Sep 09 06:49:04 PM UTC 24 |
| Finished | Sep 09 06:51:30 PM UTC 24 |
| Peak memory | 271052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287243814 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.3287243814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.954537712 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 17499000 ps |
| CPU time | 18.76 seconds |
| Started | Sep 09 06:49:14 PM UTC 24 |
| Finished | Sep 09 06:49:33 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954537712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.954537712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.1347186153 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 201525000 ps |
| CPU time | 176.54 seconds |
| Started | Sep 09 06:49:14 PM UTC 24 |
| Finished | Sep 09 06:52:13 PM UTC 24 |
| Peak memory | 271372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347186153 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.1347186153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.1926450942 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 41747000 ps |
| CPU time | 24.99 seconds |
| Started | Sep 09 06:49:15 PM UTC 24 |
| Finished | Sep 09 06:49:41 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926450942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1926450942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.1500778671 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 78018500 ps |
| CPU time | 146.19 seconds |
| Started | Sep 09 06:49:15 PM UTC 24 |
| Finished | Sep 09 06:51:43 PM UTC 24 |
| Peak memory | 270796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500778671 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.1500778671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.433748960 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 16670800 ps |
| CPU time | 23.82 seconds |
| Started | Sep 09 06:49:18 PM UTC 24 |
| Finished | Sep 09 06:49:43 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433748960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.433748960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1504271591 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 39122000 ps |
| CPU time | 160.98 seconds |
| Started | Sep 09 06:49:15 PM UTC 24 |
| Finished | Sep 09 06:51:58 PM UTC 24 |
| Peak memory | 271220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504271591 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.1504271591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.1127521448 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 47293200 ps |
| CPU time | 23.62 seconds |
| Started | Sep 09 06:49:19 PM UTC 24 |
| Finished | Sep 09 06:49:44 PM UTC 24 |
| Peak memory | 294872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127521448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1127521448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2874929465 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 138675400 ps |
| CPU time | 183.06 seconds |
| Started | Sep 09 06:49:18 PM UTC 24 |
| Finished | Sep 09 06:52:24 PM UTC 24 |
| Peak memory | 270648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874929465 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.2874929465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.1637501308 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 71425300 ps |
| CPU time | 22.96 seconds |
| Started | Sep 09 06:49:28 PM UTC 24 |
| Finished | Sep 09 06:49:54 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637501308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.1637501308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.2271509386 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 137696800 ps |
| CPU time | 167.28 seconds |
| Started | Sep 09 06:49:23 PM UTC 24 |
| Finished | Sep 09 06:52:14 PM UTC 24 |
| Peak memory | 271304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271509386 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.2271509386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.4235511218 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 46237200 ps |
| CPU time | 23.48 seconds |
| Started | Sep 09 06:02:42 PM UTC 24 |
| Finished | Sep 09 06:03:07 PM UTC 24 |
| Peak memory | 268908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235511218 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.4235511218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.1745284686 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 22458700 ps |
| CPU time | 24.76 seconds |
| Started | Sep 09 06:02:12 PM UTC 24 |
| Finished | Sep 09 06:02:38 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745284686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1745284686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.3868218909 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 27937500 ps |
| CPU time | 37.77 seconds |
| Started | Sep 09 06:02:02 PM UTC 24 |
| Finished | Sep 09 06:02:41 PM UTC 24 |
| Peak memory | 285364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3868218909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c trl_disable.3868218909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.2700938017 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 21094006300 ps |
| CPU time | 2787.6 seconds |
| Started | Sep 09 05:59:58 PM UTC 24 |
| Finished | Sep 09 06:46:53 PM UTC 24 |
| Peak memory | 275628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700938017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.2700938017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.3457855123 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 663987300 ps |
| CPU time | 981.95 seconds |
| Started | Sep 09 05:59:57 PM UTC 24 |
| Finished | Sep 09 06:16:29 PM UTC 24 |
| Peak memory | 285152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457855123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.3457855123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2601039412 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3817950300 ps |
| CPU time | 41.86 seconds |
| Started | Sep 09 05:59:46 PM UTC 24 |
| Finished | Sep 09 06:00:29 PM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26 01039412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetc h_code.2601039412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1738511988 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 10101298200 ps |
| CPU time | 71.03 seconds |
| Started | Sep 09 06:02:39 PM UTC 24 |
| Finished | Sep 09 06:03:52 PM UTC 24 |
| Peak memory | 275160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1738511988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1738511988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.3796687453 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 25221100 ps |
| CPU time | 26.79 seconds |
| Started | Sep 09 06:02:30 PM UTC 24 |
| Finished | Sep 09 06:02:58 PM UTC 24 |
| Peak memory | 271020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3796687453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3796687453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.2794139624 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 80138926700 ps |
| CPU time | 1009.22 seconds |
| Started | Sep 09 05:59:33 PM UTC 24 |
| Finished | Sep 09 06:16:34 PM UTC 24 |
| Peak memory | 270648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794139624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.2794139624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.207690171 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 3427471500 ps |
| CPU time | 141.84 seconds |
| Started | Sep 09 05:59:33 PM UTC 24 |
| Finished | Sep 09 06:01:58 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207690171 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.207690171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.118191990 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2752473500 ps |
| CPU time | 148.74 seconds |
| Started | Sep 09 06:00:59 PM UTC 24 |
| Finished | Sep 09 06:03:30 PM UTC 24 |
| Peak memory | 301736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118191990 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.118191990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.185956287 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 8080006900 ps |
| CPU time | 169.83 seconds |
| Started | Sep 09 06:01:06 PM UTC 24 |
| Finished | Sep 09 06:03:59 PM UTC 24 |
| Peak memory | 303724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=185956287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 6.flash_ctrl_intr_rd_slow_flash.185956287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.1740652985 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 9063576000 ps |
| CPU time | 64.15 seconds |
| Started | Sep 09 06:01:02 PM UTC 24 |
| Finished | Sep 09 06:02:08 PM UTC 24 |
| Peak memory | 275004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740652985 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.1740652985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.322062666 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 10510328000 ps |
| CPU time | 88.92 seconds |
| Started | Sep 09 06:00:22 PM UTC 24 |
| Finished | Sep 09 06:01:53 PM UTC 24 |
| Peak memory | 274748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322062666 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.322062666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.2845277275 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 47491500 ps |
| CPU time | 27.91 seconds |
| Started | Sep 09 06:02:19 PM UTC 24 |
| Finished | Sep 09 06:02:48 PM UTC 24 |
| Peak memory | 271300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2845277275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_lcmgr_intg.2845277275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.3224011903 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 16408364000 ps |
| CPU time | 194.32 seconds |
| Started | Sep 09 05:59:40 PM UTC 24 |
| Finished | Sep 09 06:02:57 PM UTC 24 |
| Peak memory | 274876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3224011903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.3224011903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2982127734 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 38907500 ps |
| CPU time | 208.24 seconds |
| Started | Sep 09 05:59:34 PM UTC 24 |
| Finished | Sep 09 06:03:05 PM UTC 24 |
| Peak memory | 275140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982127734 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.2982127734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.2860867305 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3195320400 ps |
| CPU time | 342.75 seconds |
| Started | Sep 09 05:59:32 PM UTC 24 |
| Finished | Sep 09 06:05:19 PM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860867305 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2860867305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.2141033553 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 70662500 ps |
| CPU time | 23.64 seconds |
| Started | Sep 09 06:01:46 PM UTC 24 |
| Finished | Sep 09 06:02:11 PM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141033553 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.2141033553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.4274124431 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1511023900 ps |
| CPU time | 1242.94 seconds |
| Started | Sep 09 05:59:30 PM UTC 24 |
| Finished | Sep 09 06:20:27 PM UTC 24 |
| Peak memory | 295436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274124431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.4274124431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2999115688 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 300058100 ps |
| CPU time | 55.81 seconds |
| Started | Sep 09 06:01:59 PM UTC 24 |
| Finished | Sep 09 06:02:56 PM UTC 24 |
| Peak memory | 285632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999115688 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.2999115688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.879789297 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2226692200 ps |
| CPU time | 105.51 seconds |
| Started | Sep 09 06:00:30 PM UTC 24 |
| Finished | Sep 09 06:02:18 PM UTC 24 |
| Peak memory | 291460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=879789297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.879789297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.2401372506 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1246807400 ps |
| CPU time | 144.73 seconds |
| Started | Sep 09 06:00:54 PM UTC 24 |
| Finished | Sep 09 06:03:21 PM UTC 24 |
| Peak memory | 291508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401372506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2401372506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1995369351 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1407146000 ps |
| CPU time | 160.85 seconds |
| Started | Sep 09 06:00:36 PM UTC 24 |
| Finished | Sep 09 06:03:21 PM UTC 24 |
| Peak memory | 305840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1995369351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash _ctrl_ro_serr.1995369351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.123655665 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 14720577400 ps |
| CPU time | 549.66 seconds |
| Started | Sep 09 06:00:30 PM UTC 24 |
| Finished | Sep 09 06:09:47 PM UTC 24 |
| Peak memory | 320124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123655665 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.123655665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2150091112 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1343905900 ps |
| CPU time | 185.74 seconds |
| Started | Sep 09 06:00:56 PM UTC 24 |
| Finished | Sep 09 06:04:05 PM UTC 24 |
| Peak memory | 291500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2150091112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 6.flash_ctrl_rw_derr.2150091112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.1556346571 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 43520000 ps |
| CPU time | 60.56 seconds |
| Started | Sep 09 06:01:50 PM UTC 24 |
| Finished | Sep 09 06:02:52 PM UTC 24 |
| Peak memory | 281276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556346571 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.1556346571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.4177337047 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 120281000 ps |
| CPU time | 33.84 seconds |
| Started | Sep 09 06:01:54 PM UTC 24 |
| Finished | Sep 09 06:02:29 PM UTC 24 |
| Peak memory | 287748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4177337047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct rl_rw_evict_all_en.4177337047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1560941276 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 954372500 ps |
| CPU time | 122.42 seconds |
| Started | Sep 09 06:00:39 PM UTC 24 |
| Finished | Sep 09 06:02:43 PM UTC 24 |
| Peak memory | 301760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1560941276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.1560941276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.1795561225 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2052574600 ps |
| CPU time | 69 seconds |
| Started | Sep 09 06:02:09 PM UTC 24 |
| Finished | Sep 09 06:03:20 PM UTC 24 |
| Peak memory | 274776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795561225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.1795561225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.2956824058 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 38403200 ps |
| CPU time | 96.86 seconds |
| Started | Sep 09 05:59:22 PM UTC 24 |
| Finished | Sep 09 06:01:01 PM UTC 24 |
| Peak memory | 285196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956824058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2956824058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.766914565 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 10427468300 ps |
| CPU time | 273.15 seconds |
| Started | Sep 09 06:00:27 PM UTC 24 |
| Finished | Sep 09 06:05:04 PM UTC 24 |
| Peak memory | 275016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =766914565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.766914565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.3402209999 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 201017400 ps |
| CPU time | 24.76 seconds |
| Started | Sep 09 06:49:32 PM UTC 24 |
| Finished | Sep 09 06:49:58 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402209999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3402209999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.1611042825 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 157113400 ps |
| CPU time | 158.41 seconds |
| Started | Sep 09 06:49:30 PM UTC 24 |
| Finished | Sep 09 06:52:11 PM UTC 24 |
| Peak memory | 274740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611042825 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.1611042825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.1385132191 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 28130400 ps |
| CPU time | 17.24 seconds |
| Started | Sep 09 06:49:33 PM UTC 24 |
| Finished | Sep 09 06:49:52 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385132191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1385132191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1987631663 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 72979900 ps |
| CPU time | 166.97 seconds |
| Started | Sep 09 06:49:32 PM UTC 24 |
| Finished | Sep 09 06:52:22 PM UTC 24 |
| Peak memory | 270792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987631663 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.1987631663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.2761045064 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 51270300 ps |
| CPU time | 23.48 seconds |
| Started | Sep 09 06:49:34 PM UTC 24 |
| Finished | Sep 09 06:49:59 PM UTC 24 |
| Peak memory | 294872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761045064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2761045064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.1914197277 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 133376400 ps |
| CPU time | 168 seconds |
| Started | Sep 09 06:49:34 PM UTC 24 |
| Finished | Sep 09 06:52:25 PM UTC 24 |
| Peak memory | 270964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914197277 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.1914197277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.1575260349 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 45286300 ps |
| CPU time | 26.08 seconds |
| Started | Sep 09 06:49:35 PM UTC 24 |
| Finished | Sep 09 06:50:03 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575260349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1575260349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2044561546 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 151210300 ps |
| CPU time | 135.93 seconds |
| Started | Sep 09 06:49:34 PM UTC 24 |
| Finished | Sep 09 06:51:53 PM UTC 24 |
| Peak memory | 271052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044561546 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.2044561546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.153144035 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 83521000 ps |
| CPU time | 26.88 seconds |
| Started | Sep 09 06:49:38 PM UTC 24 |
| Finished | Sep 09 06:50:06 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153144035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.153144035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.871128974 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 61855200 ps |
| CPU time | 141 seconds |
| Started | Sep 09 06:49:37 PM UTC 24 |
| Finished | Sep 09 06:52:00 PM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871128974 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.871128974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.2177481510 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 71151900 ps |
| CPU time | 24.47 seconds |
| Started | Sep 09 06:49:39 PM UTC 24 |
| Finished | Sep 09 06:50:05 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177481510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2177481510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.160816838 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 35462100 ps |
| CPU time | 157.08 seconds |
| Started | Sep 09 06:49:39 PM UTC 24 |
| Finished | Sep 09 06:52:19 PM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160816838 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.160816838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.253017055 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 23184300 ps |
| CPU time | 21.57 seconds |
| Started | Sep 09 06:49:42 PM UTC 24 |
| Finished | Sep 09 06:50:05 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253017055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.253017055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.72572881 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 39350400 ps |
| CPU time | 141.29 seconds |
| Started | Sep 09 06:49:41 PM UTC 24 |
| Finished | Sep 09 06:52:05 PM UTC 24 |
| Peak memory | 270956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72572881 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.72572881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.788475084 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 26441900 ps |
| CPU time | 20.88 seconds |
| Started | Sep 09 06:49:44 PM UTC 24 |
| Finished | Sep 09 06:50:07 PM UTC 24 |
| Peak memory | 284440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788475084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.788475084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.2754768641 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 160784000 ps |
| CPU time | 166.88 seconds |
| Started | Sep 09 06:49:44 PM UTC 24 |
| Finished | Sep 09 06:52:34 PM UTC 24 |
| Peak memory | 271224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754768641 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.2754768641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.3740902169 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 26868000 ps |
| CPU time | 22.97 seconds |
| Started | Sep 09 06:49:49 PM UTC 24 |
| Finished | Sep 09 06:50:13 PM UTC 24 |
| Peak memory | 294676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740902169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3740902169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.4162464463 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 42569800 ps |
| CPU time | 158.45 seconds |
| Started | Sep 09 06:49:45 PM UTC 24 |
| Finished | Sep 09 06:52:27 PM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162464463 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.4162464463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.41085367 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 14804900 ps |
| CPU time | 25.69 seconds |
| Started | Sep 09 06:49:52 PM UTC 24 |
| Finished | Sep 09 06:50:19 PM UTC 24 |
| Peak memory | 294812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41085367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.41085367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.292149964 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 76934400 ps |
| CPU time | 172.88 seconds |
| Started | Sep 09 06:49:49 PM UTC 24 |
| Finished | Sep 09 06:52:45 PM UTC 24 |
| Peak memory | 270900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292149964 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.292149964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.292664062 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 97230800 ps |
| CPU time | 28.35 seconds |
| Started | Sep 09 06:06:55 PM UTC 24 |
| Finished | Sep 09 06:07:24 PM UTC 24 |
| Peak memory | 268912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292664062 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.292664062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.3521271581 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 4925273300 ps |
| CPU time | 2937.4 seconds |
| Started | Sep 09 06:03:22 PM UTC 24 |
| Finished | Sep 09 06:52:50 PM UTC 24 |
| Peak memory | 274952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521271581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.3521271581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3303991323 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 373881200 ps |
| CPU time | 993.09 seconds |
| Started | Sep 09 06:03:21 PM UTC 24 |
| Finished | Sep 09 06:20:05 PM UTC 24 |
| Peak memory | 285152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303991323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3303991323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.3929991644 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 3561146000 ps |
| CPU time | 38.68 seconds |
| Started | Sep 09 06:03:07 PM UTC 24 |
| Finished | Sep 09 06:03:48 PM UTC 24 |
| Peak memory | 272904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39 29991644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetc h_code.3929991644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3933846283 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 10034518800 ps |
| CPU time | 95.12 seconds |
| Started | Sep 09 06:06:47 PM UTC 24 |
| Finished | Sep 09 06:08:24 PM UTC 24 |
| Peak memory | 301784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3933846283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3933846283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1220699198 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 15149400 ps |
| CPU time | 22.29 seconds |
| Started | Sep 09 06:06:46 PM UTC 24 |
| Finished | Sep 09 06:07:09 PM UTC 24 |
| Peak memory | 271008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1220699198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1220699198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.657185488 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 40125451600 ps |
| CPU time | 791.15 seconds |
| Started | Sep 09 06:02:58 PM UTC 24 |
| Finished | Sep 09 06:16:18 PM UTC 24 |
| Peak memory | 272692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657185488 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.657185488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.1854205569 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2330728400 ps |
| CPU time | 205.79 seconds |
| Started | Sep 09 06:02:57 PM UTC 24 |
| Finished | Sep 09 06:06:26 PM UTC 24 |
| Peak memory | 272732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854205569 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.1854205569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2268417573 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 736906500 ps |
| CPU time | 180.08 seconds |
| Started | Sep 09 06:05:19 PM UTC 24 |
| Finished | Sep 09 06:08:23 PM UTC 24 |
| Peak memory | 303820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268417573 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.2268417573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3503644120 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 49982391400 ps |
| CPU time | 273.26 seconds |
| Started | Sep 09 06:05:27 PM UTC 24 |
| Finished | Sep 09 06:10:04 PM UTC 24 |
| Peak memory | 293468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3503644120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_intr_rd_slow_flash.3503644120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.1211584940 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 4732278300 ps |
| CPU time | 106.43 seconds |
| Started | Sep 09 06:05:20 PM UTC 24 |
| Finished | Sep 09 06:07:09 PM UTC 24 |
| Peak memory | 275004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211584940 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.1211584940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1883134691 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 50490678100 ps |
| CPU time | 400.37 seconds |
| Started | Sep 09 06:05:35 PM UTC 24 |
| Finished | Sep 09 06:12:21 PM UTC 24 |
| Peak memory | 271216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883134691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1883134691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.1083139986 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 6129552000 ps |
| CPU time | 88.63 seconds |
| Started | Sep 09 06:03:22 PM UTC 24 |
| Finished | Sep 09 06:04:52 PM UTC 24 |
| Peak memory | 272708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083139986 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.1083139986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2160558538 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 29978400 ps |
| CPU time | 26.57 seconds |
| Started | Sep 09 06:06:43 PM UTC 24 |
| Finished | Sep 09 06:07:11 PM UTC 24 |
| Peak memory | 271076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2160558538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_lcmgr_intg.2160558538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.4039033284 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 100478904600 ps |
| CPU time | 322.3 seconds |
| Started | Sep 09 06:03:05 PM UTC 24 |
| Finished | Sep 09 06:08:32 PM UTC 24 |
| Peak memory | 283332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4039033284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.4039033284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.1189501182 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 132164400 ps |
| CPU time | 177.81 seconds |
| Started | Sep 09 06:02:59 PM UTC 24 |
| Finished | Sep 09 06:06:00 PM UTC 24 |
| Peak memory | 271280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189501182 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.1189501182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.4000150590 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 150825200 ps |
| CPU time | 184.2 seconds |
| Started | Sep 09 06:02:54 PM UTC 24 |
| Finished | Sep 09 06:06:00 PM UTC 24 |
| Peak memory | 275164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000150590 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.4000150590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.4176190039 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 76127000 ps |
| CPU time | 15.37 seconds |
| Started | Sep 09 06:06:01 PM UTC 24 |
| Finished | Sep 09 06:06:17 PM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176190039 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.4176190039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.2061388438 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3316936800 ps |
| CPU time | 2119.42 seconds |
| Started | Sep 09 06:02:49 PM UTC 24 |
| Finished | Sep 09 06:38:32 PM UTC 24 |
| Peak memory | 297544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061388438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.2061388438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.3010117949 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 98999300 ps |
| CPU time | 51.88 seconds |
| Started | Sep 09 06:06:11 PM UTC 24 |
| Finished | Sep 09 06:07:04 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010117949 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.3010117949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.3903741980 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 2759611200 ps |
| CPU time | 133.83 seconds |
| Started | Sep 09 06:03:49 PM UTC 24 |
| Finished | Sep 09 06:06:05 PM UTC 24 |
| Peak memory | 291500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3903741980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.3903741980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.951436429 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 648336600 ps |
| CPU time | 178.97 seconds |
| Started | Sep 09 06:04:54 PM UTC 24 |
| Finished | Sep 09 06:07:56 PM UTC 24 |
| Peak memory | 291508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951436429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.951436429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.2913128674 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 662567900 ps |
| CPU time | 146.61 seconds |
| Started | Sep 09 06:03:59 PM UTC 24 |
| Finished | Sep 09 06:06:28 PM UTC 24 |
| Peak memory | 303796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2913128674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash _ctrl_ro_serr.2913128674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.200231776 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3296955200 ps |
| CPU time | 399.66 seconds |
| Started | Sep 09 06:03:53 PM UTC 24 |
| Finished | Sep 09 06:10:38 PM UTC 24 |
| Peak memory | 320340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200231776 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.200231776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.2826360630 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1587105100 ps |
| CPU time | 176.47 seconds |
| Started | Sep 09 06:05:05 PM UTC 24 |
| Finished | Sep 09 06:08:04 PM UTC 24 |
| Peak memory | 295620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2826360630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 7.flash_ctrl_rw_derr.2826360630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.4217034777 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 69883900 ps |
| CPU time | 53.67 seconds |
| Started | Sep 09 06:06:02 PM UTC 24 |
| Finished | Sep 09 06:06:57 PM UTC 24 |
| Peak memory | 287552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217034777 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.4217034777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.2325010259 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 37235700 ps |
| CPU time | 34.98 seconds |
| Started | Sep 09 06:06:06 PM UTC 24 |
| Finished | Sep 09 06:06:42 PM UTC 24 |
| Peak memory | 287428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2325010259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct rl_rw_evict_all_en.2325010259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.1139668369 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1246622700 ps |
| CPU time | 157.31 seconds |
| Started | Sep 09 06:04:05 PM UTC 24 |
| Finished | Sep 09 06:06:45 PM UTC 24 |
| Peak memory | 305832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1139668369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.1139668369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.3455334608 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1493662700 ps |
| CPU time | 94.99 seconds |
| Started | Sep 09 06:06:26 PM UTC 24 |
| Finished | Sep 09 06:08:03 PM UTC 24 |
| Peak memory | 275036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455334608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3455334608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.4094784735 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 3586778500 ps |
| CPU time | 202.95 seconds |
| Started | Sep 09 06:02:44 PM UTC 24 |
| Finished | Sep 09 06:06:10 PM UTC 24 |
| Peak memory | 291596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094784735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.4094784735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.1659341065 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 12925007800 ps |
| CPU time | 239.11 seconds |
| Started | Sep 09 06:03:31 PM UTC 24 |
| Finished | Sep 09 06:07:34 PM UTC 24 |
| Peak memory | 275296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1659341065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.1659341065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.1038121698 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 15795500 ps |
| CPU time | 19.79 seconds |
| Started | Sep 09 06:49:54 PM UTC 24 |
| Finished | Sep 09 06:50:15 PM UTC 24 |
| Peak memory | 284436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038121698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1038121698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.1828844334 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 73693000 ps |
| CPU time | 176.38 seconds |
| Started | Sep 09 06:49:53 PM UTC 24 |
| Finished | Sep 09 06:52:52 PM UTC 24 |
| Peak memory | 270648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828844334 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.1828844334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.131060549 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 45252600 ps |
| CPU time | 26.99 seconds |
| Started | Sep 09 06:49:58 PM UTC 24 |
| Finished | Sep 09 06:50:26 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131060549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.131060549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.3842701438 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 202099200 ps |
| CPU time | 18.78 seconds |
| Started | Sep 09 06:50:03 PM UTC 24 |
| Finished | Sep 09 06:50:23 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842701438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3842701438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.3737725582 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 47042900 ps |
| CPU time | 152.81 seconds |
| Started | Sep 09 06:50:00 PM UTC 24 |
| Finished | Sep 09 06:52:36 PM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737725582 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.3737725582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.3590332270 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 22640300 ps |
| CPU time | 32.74 seconds |
| Started | Sep 09 06:50:06 PM UTC 24 |
| Finished | Sep 09 06:50:40 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590332270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3590332270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.1600049057 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 79985500 ps |
| CPU time | 146.12 seconds |
| Started | Sep 09 06:50:03 PM UTC 24 |
| Finished | Sep 09 06:52:32 PM UTC 24 |
| Peak memory | 270792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600049057 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.1600049057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.845626745 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 30705100 ps |
| CPU time | 24.06 seconds |
| Started | Sep 09 06:50:07 PM UTC 24 |
| Finished | Sep 09 06:50:32 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845626745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.845626745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.437242497 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 41256500 ps |
| CPU time | 136.88 seconds |
| Started | Sep 09 06:50:06 PM UTC 24 |
| Finished | Sep 09 06:52:25 PM UTC 24 |
| Peak memory | 271048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437242497 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.437242497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.1657699986 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 28795300 ps |
| CPU time | 24.36 seconds |
| Started | Sep 09 06:50:08 PM UTC 24 |
| Finished | Sep 09 06:50:34 PM UTC 24 |
| Peak memory | 294676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657699986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1657699986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.4058081661 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 371459000 ps |
| CPU time | 153.35 seconds |
| Started | Sep 09 06:50:08 PM UTC 24 |
| Finished | Sep 09 06:52:44 PM UTC 24 |
| Peak memory | 270960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058081661 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.4058081661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.1023585905 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 30367800 ps |
| CPU time | 26.69 seconds |
| Started | Sep 09 06:50:14 PM UTC 24 |
| Finished | Sep 09 06:50:42 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023585905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1023585905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.2743816138 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 184251300 ps |
| CPU time | 168.9 seconds |
| Started | Sep 09 06:50:11 PM UTC 24 |
| Finished | Sep 09 06:53:03 PM UTC 24 |
| Peak memory | 270788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743816138 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.2743816138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.4123698942 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 69199700 ps |
| CPU time | 20.48 seconds |
| Started | Sep 09 06:50:16 PM UTC 24 |
| Finished | Sep 09 06:50:38 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123698942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.4123698942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.1283231354 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 47792600 ps |
| CPU time | 18.75 seconds |
| Started | Sep 09 06:50:22 PM UTC 24 |
| Finished | Sep 09 06:50:42 PM UTC 24 |
| Peak memory | 294616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283231354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1283231354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2294326730 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 77908100 ps |
| CPU time | 165.95 seconds |
| Started | Sep 09 06:50:19 PM UTC 24 |
| Finished | Sep 09 06:53:08 PM UTC 24 |
| Peak memory | 271224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294326730 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.2294326730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.910327668 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 117923900 ps |
| CPU time | 19.4 seconds |
| Started | Sep 09 06:50:25 PM UTC 24 |
| Finished | Sep 09 06:50:45 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910327668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.910327668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.3942749713 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 92220300 ps |
| CPU time | 165.94 seconds |
| Started | Sep 09 06:50:24 PM UTC 24 |
| Finished | Sep 09 06:53:12 PM UTC 24 |
| Peak memory | 271052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942749713 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.3942749713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.4127446397 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 28645200 ps |
| CPU time | 29.7 seconds |
| Started | Sep 09 06:10:52 PM UTC 24 |
| Finished | Sep 09 06:11:23 PM UTC 24 |
| Peak memory | 268912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127446397 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.4127446397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.291690988 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 14680700 ps |
| CPU time | 24.55 seconds |
| Started | Sep 09 06:10:29 PM UTC 24 |
| Finished | Sep 09 06:10:55 PM UTC 24 |
| Peak memory | 294680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291690988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.291690988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.1133501655 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 27694200 ps |
| CPU time | 44.43 seconds |
| Started | Sep 09 06:10:14 PM UTC 24 |
| Finished | Sep 09 06:11:00 PM UTC 24 |
| Peak memory | 285360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1133501655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_c trl_disable.1133501655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.2181430858 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 31489369200 ps |
| CPU time | 3211.48 seconds |
| Started | Sep 09 06:08:00 PM UTC 24 |
| Finished | Sep 09 07:02:05 PM UTC 24 |
| Peak memory | 275968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181430858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.2181430858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3568071128 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1942660200 ps |
| CPU time | 1617.91 seconds |
| Started | Sep 09 06:08:00 PM UTC 24 |
| Finished | Sep 09 06:35:16 PM UTC 24 |
| Peak memory | 285152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568071128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3568071128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.621951636 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 423533900 ps |
| CPU time | 41.12 seconds |
| Started | Sep 09 06:07:56 PM UTC 24 |
| Finished | Sep 09 06:08:39 PM UTC 24 |
| Peak memory | 272852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62 1951636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch _code.621951636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3858631373 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 10019366500 ps |
| CPU time | 154.56 seconds |
| Started | Sep 09 06:10:38 PM UTC 24 |
| Finished | Sep 09 06:13:16 PM UTC 24 |
| Peak memory | 338644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3858631373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3858631373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1317510005 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 15832800 ps |
| CPU time | 27.16 seconds |
| Started | Sep 09 06:10:37 PM UTC 24 |
| Finished | Sep 09 06:11:06 PM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1317510005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1317510005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2726508069 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 80149172300 ps |
| CPU time | 806.57 seconds |
| Started | Sep 09 06:07:12 PM UTC 24 |
| Finished | Sep 09 06:20:48 PM UTC 24 |
| Peak memory | 275004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726508069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.2726508069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.446249269 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3187044900 ps |
| CPU time | 121.56 seconds |
| Started | Sep 09 06:07:10 PM UTC 24 |
| Finished | Sep 09 06:09:14 PM UTC 24 |
| Peak memory | 272732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446249269 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.446249269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1765693586 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1754370500 ps |
| CPU time | 228.87 seconds |
| Started | Sep 09 06:09:14 PM UTC 24 |
| Finished | Sep 09 06:13:06 PM UTC 24 |
| Peak memory | 293544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765693586 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.1765693586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1212754083 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 5853185400 ps |
| CPU time | 158.84 seconds |
| Started | Sep 09 06:09:48 PM UTC 24 |
| Finished | Sep 09 06:12:29 PM UTC 24 |
| Peak memory | 303976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1212754083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_intr_rd_slow_flash.1212754083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3156461765 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2992623300 ps |
| CPU time | 68.01 seconds |
| Started | Sep 09 06:09:40 PM UTC 24 |
| Finished | Sep 09 06:10:50 PM UTC 24 |
| Peak memory | 271164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156461765 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.3156461765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.26941223 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 29031089400 ps |
| CPU time | 288.52 seconds |
| Started | Sep 09 06:09:51 PM UTC 24 |
| Finished | Sep 09 06:14:43 PM UTC 24 |
| Peak memory | 270960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26941223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.26941223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3996221053 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3392081900 ps |
| CPU time | 52.54 seconds |
| Started | Sep 09 06:08:05 PM UTC 24 |
| Finished | Sep 09 06:08:59 PM UTC 24 |
| Peak memory | 274756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996221053 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3996221053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.857808351 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2239607900 ps |
| CPU time | 144.35 seconds |
| Started | Sep 09 06:07:35 PM UTC 24 |
| Finished | Sep 09 06:10:02 PM UTC 24 |
| Peak memory | 274884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=857808351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_mp_regions.857808351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1753283701 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1425775800 ps |
| CPU time | 694.22 seconds |
| Started | Sep 09 06:07:10 PM UTC 24 |
| Finished | Sep 09 06:18:53 PM UTC 24 |
| Peak memory | 274952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753283701 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1753283701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.1955362744 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 27628400 ps |
| CPU time | 23.25 seconds |
| Started | Sep 09 06:10:04 PM UTC 24 |
| Finished | Sep 09 06:10:28 PM UTC 24 |
| Peak memory | 275036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955362744 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.1955362744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3798012220 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 649277700 ps |
| CPU time | 1196.73 seconds |
| Started | Sep 09 06:07:05 PM UTC 24 |
| Finished | Sep 09 06:27:14 PM UTC 24 |
| Peak memory | 293376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798012220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3798012220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.4079775813 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 936568800 ps |
| CPU time | 107.73 seconds |
| Started | Sep 09 06:08:23 PM UTC 24 |
| Finished | Sep 09 06:10:13 PM UTC 24 |
| Peak memory | 301784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4079775813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.4079775813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2596720299 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1634966600 ps |
| CPU time | 138.04 seconds |
| Started | Sep 09 06:09:00 PM UTC 24 |
| Finished | Sep 09 06:11:21 PM UTC 24 |
| Peak memory | 291500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596720299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2596720299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3918272464 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 494763400 ps |
| CPU time | 121.03 seconds |
| Started | Sep 09 06:08:34 PM UTC 24 |
| Finished | Sep 09 06:10:37 PM UTC 24 |
| Peak memory | 291532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3918272464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_ro_serr.3918272464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.2033771701 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3533402600 ps |
| CPU time | 502.85 seconds |
| Started | Sep 09 06:08:25 PM UTC 24 |
| Finished | Sep 09 06:16:55 PM UTC 24 |
| Peak memory | 320136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033771701 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.2033771701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3616928819 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 5642143400 ps |
| CPU time | 223.48 seconds |
| Started | Sep 09 06:09:05 PM UTC 24 |
| Finished | Sep 09 06:12:52 PM UTC 24 |
| Peak memory | 297924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3616928819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 8.flash_ctrl_rw_derr.3616928819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3096011133 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 99340500 ps |
| CPU time | 55.07 seconds |
| Started | Sep 09 06:10:06 PM UTC 24 |
| Finished | Sep 09 06:11:02 PM UTC 24 |
| Peak memory | 287616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096011133 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.3096011133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.3670033179 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 66253900 ps |
| CPU time | 50.84 seconds |
| Started | Sep 09 06:10:06 PM UTC 24 |
| Finished | Sep 09 06:10:58 PM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3670033179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct rl_rw_evict_all_en.3670033179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.4252980585 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 8919936700 ps |
| CPU time | 186.21 seconds |
| Started | Sep 09 06:08:40 PM UTC 24 |
| Finished | Sep 09 06:11:49 PM UTC 24 |
| Peak memory | 291504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4252980585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.4252980585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.2062232809 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 6496875000 ps |
| CPU time | 72.86 seconds |
| Started | Sep 09 06:10:16 PM UTC 24 |
| Finished | Sep 09 06:11:31 PM UTC 24 |
| Peak memory | 275104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062232809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.2062232809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.2117379103 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2327565300 ps |
| CPU time | 284.71 seconds |
| Started | Sep 09 06:06:58 PM UTC 24 |
| Finished | Sep 09 06:11:46 PM UTC 24 |
| Peak memory | 291404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117379103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2117379103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1718948779 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3959756300 ps |
| CPU time | 184.05 seconds |
| Started | Sep 09 06:08:06 PM UTC 24 |
| Finished | Sep 09 06:11:13 PM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1718948779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.1718948779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.3213703048 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 34435600 ps |
| CPU time | 25.41 seconds |
| Started | Sep 09 06:14:45 PM UTC 24 |
| Finished | Sep 09 06:15:12 PM UTC 24 |
| Peak memory | 268912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213703048 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.3213703048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.1268896753 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 50035600 ps |
| CPU time | 27.27 seconds |
| Started | Sep 09 06:14:16 PM UTC 24 |
| Finished | Sep 09 06:14:44 PM UTC 24 |
| Peak memory | 294684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268896753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1268896753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.3650703129 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 55400500 ps |
| CPU time | 38.1 seconds |
| Started | Sep 09 06:14:09 PM UTC 24 |
| Finished | Sep 09 06:14:48 PM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3650703129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c trl_disable.3650703129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.2190958778 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 17146415300 ps |
| CPU time | 2913.32 seconds |
| Started | Sep 09 06:11:23 PM UTC 24 |
| Finished | Sep 09 07:00:26 PM UTC 24 |
| Peak memory | 274908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190958778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.2190958778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.1486887543 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 364323500 ps |
| CPU time | 1154.87 seconds |
| Started | Sep 09 06:11:21 PM UTC 24 |
| Finished | Sep 09 06:30:49 PM UTC 24 |
| Peak memory | 285152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486887543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1486887543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2012818635 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 114345400 ps |
| CPU time | 34.07 seconds |
| Started | Sep 09 06:11:14 PM UTC 24 |
| Finished | Sep 09 06:11:50 PM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20 12818635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc h_code.2012818635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.281861225 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 10018720800 ps |
| CPU time | 125.33 seconds |
| Started | Sep 09 06:14:44 PM UTC 24 |
| Finished | Sep 09 06:16:52 PM UTC 24 |
| Peak memory | 322548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=281861225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.281861225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.1547816728 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 26941100 ps |
| CPU time | 20.22 seconds |
| Started | Sep 09 06:14:33 PM UTC 24 |
| Finished | Sep 09 06:14:54 PM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1547816728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.1547816728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.3370494145 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 80137677400 ps |
| CPU time | 773.32 seconds |
| Started | Sep 09 06:11:03 PM UTC 24 |
| Finished | Sep 09 06:24:05 PM UTC 24 |
| Peak memory | 274736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370494145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.3370494145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.2684100278 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2573574300 ps |
| CPU time | 220.59 seconds |
| Started | Sep 09 06:11:01 PM UTC 24 |
| Finished | Sep 09 06:14:45 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684100278 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.2684100278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.585507439 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1627531200 ps |
| CPU time | 233.69 seconds |
| Started | Sep 09 06:12:30 PM UTC 24 |
| Finished | Sep 09 06:16:27 PM UTC 24 |
| Peak memory | 301740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585507439 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.585507439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.157822417 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 49983567100 ps |
| CPU time | 284.13 seconds |
| Started | Sep 09 06:12:53 PM UTC 24 |
| Finished | Sep 09 06:17:41 PM UTC 24 |
| Peak memory | 301708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=157822417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_intr_rd_slow_flash.157822417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.507485975 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 4894021100 ps |
| CPU time | 107.97 seconds |
| Started | Sep 09 06:12:42 PM UTC 24 |
| Finished | Sep 09 06:14:32 PM UTC 24 |
| Peak memory | 270912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507485975 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.507485975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3171210379 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 344411942100 ps |
| CPU time | 424.92 seconds |
| Started | Sep 09 06:12:53 PM UTC 24 |
| Finished | Sep 09 06:20:03 PM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171210379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3171210379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2524940223 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 3643673700 ps |
| CPU time | 78.7 seconds |
| Started | Sep 09 06:11:32 PM UTC 24 |
| Finished | Sep 09 06:12:52 PM UTC 24 |
| Peak memory | 274748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524940223 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2524940223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.2470771630 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 148442000 ps |
| CPU time | 22.11 seconds |
| Started | Sep 09 06:14:27 PM UTC 24 |
| Finished | Sep 09 06:14:50 PM UTC 24 |
| Peak memory | 271044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2470771630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_lcmgr_intg.2470771630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1303716769 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 6163772400 ps |
| CPU time | 400.23 seconds |
| Started | Sep 09 06:11:06 PM UTC 24 |
| Finished | Sep 09 06:17:52 PM UTC 24 |
| Peak memory | 283076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1303716769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.1303716769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.671015341 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 37635000 ps |
| CPU time | 188.65 seconds |
| Started | Sep 09 06:11:03 PM UTC 24 |
| Finished | Sep 09 06:14:15 PM UTC 24 |
| Peak memory | 270904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671015341 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.671015341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2255032564 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 13569495600 ps |
| CPU time | 506.41 seconds |
| Started | Sep 09 06:10:59 PM UTC 24 |
| Finished | Sep 09 06:19:32 PM UTC 24 |
| Peak memory | 274952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255032564 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2255032564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.2284547097 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 18735500 ps |
| CPU time | 23.66 seconds |
| Started | Sep 09 06:13:07 PM UTC 24 |
| Finished | Sep 09 06:13:32 PM UTC 24 |
| Peak memory | 268896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284547097 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.2284547097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.2479957901 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 70968500 ps |
| CPU time | 751.43 seconds |
| Started | Sep 09 06:10:56 PM UTC 24 |
| Finished | Sep 09 06:23:36 PM UTC 24 |
| Peak memory | 291340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479957901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2479957901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.4070506194 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 258345900 ps |
| CPU time | 57.9 seconds |
| Started | Sep 09 06:14:06 PM UTC 24 |
| Finished | Sep 09 06:15:05 PM UTC 24 |
| Peak memory | 287460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070506194 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.4070506194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1769653419 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1884252200 ps |
| CPU time | 132.3 seconds |
| Started | Sep 09 06:11:50 PM UTC 24 |
| Finished | Sep 09 06:14:05 PM UTC 24 |
| Peak memory | 301716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1769653419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.1769653419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2562873424 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 615899500 ps |
| CPU time | 151.19 seconds |
| Started | Sep 09 06:12:22 PM UTC 24 |
| Finished | Sep 09 06:14:56 PM UTC 24 |
| Peak memory | 291788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562873424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2562873424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.2314996571 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2889478000 ps |
| CPU time | 181.89 seconds |
| Started | Sep 09 06:11:55 PM UTC 24 |
| Finished | Sep 09 06:15:00 PM UTC 24 |
| Peak memory | 291532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2314996571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash _ctrl_ro_serr.2314996571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1999056195 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3386660300 ps |
| CPU time | 452.31 seconds |
| Started | Sep 09 06:11:51 PM UTC 24 |
| Finished | Sep 09 06:19:29 PM UTC 24 |
| Peak memory | 324416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999056195 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.1999056195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.4165316991 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 5301870500 ps |
| CPU time | 231.43 seconds |
| Started | Sep 09 06:12:24 PM UTC 24 |
| Finished | Sep 09 06:16:20 PM UTC 24 |
| Peak memory | 297696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=4165316991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 9.flash_ctrl_rw_derr.4165316991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2594455211 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 28364800 ps |
| CPU time | 48.93 seconds |
| Started | Sep 09 06:13:17 PM UTC 24 |
| Finished | Sep 09 06:14:08 PM UTC 24 |
| Peak memory | 281312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594455211 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.2594455211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.112442571 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 28036800 ps |
| CPU time | 51.67 seconds |
| Started | Sep 09 06:13:33 PM UTC 24 |
| Finished | Sep 09 06:14:27 PM UTC 24 |
| Peak memory | 287420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=112442571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctr l_rw_evict_all_en.112442571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.4062271874 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1289519500 ps |
| CPU time | 208.95 seconds |
| Started | Sep 09 06:12:04 PM UTC 24 |
| Finished | Sep 09 06:15:37 PM UTC 24 |
| Peak memory | 305860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4062271874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.4062271874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.4262913087 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 1324199400 ps |
| CPU time | 64.8 seconds |
| Started | Sep 09 06:14:15 PM UTC 24 |
| Finished | Sep 09 06:15:21 PM UTC 24 |
| Peak memory | 274780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262913087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.4262913087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.103788168 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 22527600 ps |
| CPU time | 61.27 seconds |
| Started | Sep 09 06:10:52 PM UTC 24 |
| Finished | Sep 09 06:11:55 PM UTC 24 |
| Peak memory | 283400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103788168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.103788168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.2665384011 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 4064449100 ps |
| CPU time | 193.19 seconds |
| Started | Sep 09 06:11:47 PM UTC 24 |
| Finished | Sep 09 06:15:03 PM UTC 24 |
| Peak memory | 271232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2665384011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.2665384011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest |
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