| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.210671153 |
|
|
Oct 03 08:46:19 AM UTC 24 |
Oct 03 08:51:04 AM UTC 24 |
171755800 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3210584297 |
|
|
Oct 03 08:48:52 AM UTC 24 |
Oct 03 08:51:05 AM UTC 24 |
145709200 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.3036557155 |
|
|
Oct 03 08:49:06 AM UTC 24 |
Oct 03 08:51:18 AM UTC 24 |
43823000 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.795490606 |
|
|
Oct 03 08:48:40 AM UTC 24 |
Oct 03 08:51:18 AM UTC 24 |
91710900 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.1451208060 |
|
|
Oct 03 08:46:50 AM UTC 24 |
Oct 03 08:51:19 AM UTC 24 |
105219500 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.1328635848 |
|
|
Oct 03 08:48:29 AM UTC 24 |
Oct 03 08:51:20 AM UTC 24 |
305815200 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.4170608895 |
|
|
Oct 03 08:43:32 AM UTC 24 |
Oct 03 08:51:24 AM UTC 24 |
86579355300 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.3257426481 |
|
|
Oct 03 08:48:39 AM UTC 24 |
Oct 03 08:51:27 AM UTC 24 |
78386700 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.4166232084 |
|
|
Oct 03 08:49:17 AM UTC 24 |
Oct 03 08:51:30 AM UTC 24 |
36483500 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.2489439123 |
|
|
Oct 03 08:48:56 AM UTC 24 |
Oct 03 08:51:30 AM UTC 24 |
137259300 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.4223098658 |
|
|
Oct 03 08:48:27 AM UTC 24 |
Oct 03 08:51:30 AM UTC 24 |
147767300 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1655314632 |
|
|
Oct 03 08:48:51 AM UTC 24 |
Oct 03 08:51:32 AM UTC 24 |
52038900 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.3393916736 |
|
|
Oct 03 08:48:45 AM UTC 24 |
Oct 03 08:51:34 AM UTC 24 |
37733100 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.2606689539 |
|
|
Oct 03 08:44:47 AM UTC 24 |
Oct 03 08:51:35 AM UTC 24 |
3574161400 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.1207191451 |
|
|
Oct 03 08:48:51 AM UTC 24 |
Oct 03 08:51:36 AM UTC 24 |
38785500 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.672579052 |
|
|
Oct 03 08:48:48 AM UTC 24 |
Oct 03 08:51:42 AM UTC 24 |
609539400 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.1402149316 |
|
|
Oct 03 08:33:22 AM UTC 24 |
Oct 03 08:51:50 AM UTC 24 |
172510700 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.3343865757 |
|
|
Oct 03 08:49:02 AM UTC 24 |
Oct 03 08:51:54 AM UTC 24 |
125931100 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.2734835439 |
|
|
Oct 03 08:49:11 AM UTC 24 |
Oct 03 08:51:58 AM UTC 24 |
468112200 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.2882694312 |
|
|
Oct 03 08:49:00 AM UTC 24 |
Oct 03 08:52:00 AM UTC 24 |
143805300 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.854937827 |
|
|
Oct 03 08:49:19 AM UTC 24 |
Oct 03 08:52:02 AM UTC 24 |
244698300 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.2138580716 |
|
|
Oct 03 08:49:27 AM UTC 24 |
Oct 03 08:52:02 AM UTC 24 |
165984100 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.893744859 |
|
|
Oct 03 08:49:29 AM UTC 24 |
Oct 03 08:52:03 AM UTC 24 |
40548800 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.2092852570 |
|
|
Oct 03 08:49:15 AM UTC 24 |
Oct 03 08:52:06 AM UTC 24 |
126441000 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1778685385 |
|
|
Oct 03 08:49:07 AM UTC 24 |
Oct 03 08:52:10 AM UTC 24 |
64785000 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.3916497464 |
|
|
Oct 03 08:49:30 AM UTC 24 |
Oct 03 08:52:18 AM UTC 24 |
75923600 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.506254256 |
|
|
Oct 03 08:49:12 AM UTC 24 |
Oct 03 08:52:25 AM UTC 24 |
65399500 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.384604678 |
|
|
Oct 03 08:49:49 AM UTC 24 |
Oct 03 08:52:26 AM UTC 24 |
111017800 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.35022341 |
|
|
Oct 03 08:49:43 AM UTC 24 |
Oct 03 08:52:33 AM UTC 24 |
126327700 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3894669715 |
|
|
Oct 03 08:49:36 AM UTC 24 |
Oct 03 08:52:36 AM UTC 24 |
132052100 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.1272101811 |
|
|
Oct 03 08:49:23 AM UTC 24 |
Oct 03 08:52:40 AM UTC 24 |
76466700 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.3528494403 |
|
|
Oct 03 08:49:38 AM UTC 24 |
Oct 03 08:52:41 AM UTC 24 |
43273700 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.3249619592 |
|
|
Oct 03 08:49:52 AM UTC 24 |
Oct 03 08:52:49 AM UTC 24 |
143724000 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1190625637 |
|
|
Oct 03 08:49:54 AM UTC 24 |
Oct 03 08:53:02 AM UTC 24 |
671705200 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.1360691694 |
|
|
Oct 03 08:47:51 AM UTC 24 |
Oct 03 08:53:18 AM UTC 24 |
714945300 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.2696999767 |
|
|
Oct 03 08:07:26 AM UTC 24 |
Oct 03 08:57:14 AM UTC 24 |
2035213100 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.2564184756 |
|
|
Oct 03 08:04:10 AM UTC 24 |
Oct 03 08:57:17 AM UTC 24 |
14196286000 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3406905673 |
|
|
Oct 03 08:10:49 AM UTC 24 |
Oct 03 09:07:43 AM UTC 24 |
45523802000 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2541033743 |
|
|
Oct 03 07:20:00 AM UTC 24 |
Oct 03 09:21:30 AM UTC 24 |
977157200 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.859243433 |
|
|
Oct 03 07:39:33 AM UTC 24 |
Oct 03 09:34:00 AM UTC 24 |
2760239400 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.4248896077 |
|
|
Oct 03 07:47:31 AM UTC 24 |
Oct 03 09:45:59 AM UTC 24 |
2735171700 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.4148653335 |
|
|
Oct 03 07:42:21 AM UTC 24 |
Oct 03 09:47:20 AM UTC 24 |
3941309500 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.1272706781 |
|
|
Oct 03 07:53:16 AM UTC 24 |
Oct 03 09:47:25 AM UTC 24 |
1197946800 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2435159909 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:27 AM UTC 24 |
20791500 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.214722897 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:28 AM UTC 24 |
28248200 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.1397306468 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:28 AM UTC 24 |
15873100 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2271515953 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:28 AM UTC 24 |
22622100 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2420659361 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:29 AM UTC 24 |
107603600 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.560539192 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:30 AM UTC 24 |
157846300 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3794187592 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:31 AM UTC 24 |
198784700 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.513661652 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:31 AM UTC 24 |
29204400 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1517381830 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:32 AM UTC 24 |
71984500 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.746065697 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:32 AM UTC 24 |
24961500 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.3639770227 |
|
|
Oct 03 06:44:14 AM UTC 24 |
Oct 03 06:44:32 AM UTC 24 |
28044600 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1589179429 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:33 AM UTC 24 |
196264800 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3150807015 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:33 AM UTC 24 |
181738700 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.4169734088 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:34 AM UTC 24 |
72990200 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4055884636 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:34 AM UTC 24 |
43175400 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3421707932 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:34 AM UTC 24 |
13288400 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1130381883 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:44:34 AM UTC 24 |
27441200 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3301045432 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:44:35 AM UTC 24 |
13675000 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2058568545 |
|
|
Oct 03 06:44:16 AM UTC 24 |
Oct 03 06:44:35 AM UTC 24 |
30119500 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3548048011 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:44:36 AM UTC 24 |
51800500 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2835589852 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:44:36 AM UTC 24 |
32429400 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1867338227 |
|
|
Oct 03 06:44:13 AM UTC 24 |
Oct 03 06:44:36 AM UTC 24 |
181355500 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.1939940751 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:44:36 AM UTC 24 |
24914500 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1923607173 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:44:37 AM UTC 24 |
19789500 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4084802214 |
|
|
Oct 03 06:44:14 AM UTC 24 |
Oct 03 06:44:38 AM UTC 24 |
35991700 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.630308509 |
|
|
Oct 03 06:44:14 AM UTC 24 |
Oct 03 06:44:38 AM UTC 24 |
13923400 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.293129988 |
|
|
Oct 03 06:44:14 AM UTC 24 |
Oct 03 06:44:38 AM UTC 24 |
41928600 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.613831416 |
|
|
Oct 03 06:44:13 AM UTC 24 |
Oct 03 06:44:39 AM UTC 24 |
86674800 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4131478567 |
|
|
Oct 03 06:44:16 AM UTC 24 |
Oct 03 06:44:40 AM UTC 24 |
17381900 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1625167898 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:44:40 AM UTC 24 |
38721200 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1533880109 |
|
|
Oct 03 06:44:18 AM UTC 24 |
Oct 03 06:44:42 AM UTC 24 |
152189600 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1090960426 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:42 AM UTC 24 |
221751800 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1175215899 |
|
|
Oct 03 06:44:24 AM UTC 24 |
Oct 03 06:44:45 AM UTC 24 |
118001900 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3262125934 |
|
|
Oct 03 06:44:29 AM UTC 24 |
Oct 03 06:44:48 AM UTC 24 |
50587800 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.4082739732 |
|
|
Oct 03 06:44:30 AM UTC 24 |
Oct 03 06:44:49 AM UTC 24 |
231399600 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3803032990 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:49 AM UTC 24 |
51802700 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3905783199 |
|
|
Oct 03 06:44:29 AM UTC 24 |
Oct 03 06:44:50 AM UTC 24 |
29637500 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4134077396 |
|
|
Oct 03 06:44:29 AM UTC 24 |
Oct 03 06:44:50 AM UTC 24 |
13855000 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2708960698 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:44:50 AM UTC 24 |
325629000 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2531051348 |
|
|
Oct 03 06:44:28 AM UTC 24 |
Oct 03 06:44:50 AM UTC 24 |
406395300 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3447524763 |
|
|
Oct 03 06:44:31 AM UTC 24 |
Oct 03 06:44:51 AM UTC 24 |
53809800 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2773485973 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:44:51 AM UTC 24 |
248590800 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.528429276 |
|
|
Oct 03 06:44:35 AM UTC 24 |
Oct 03 06:44:51 AM UTC 24 |
16050200 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.809615529 |
|
|
Oct 03 06:44:35 AM UTC 24 |
Oct 03 06:44:52 AM UTC 24 |
16094100 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2864937041 |
|
|
Oct 03 06:44:13 AM UTC 24 |
Oct 03 06:44:53 AM UTC 24 |
931743700 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2196813987 |
|
|
Oct 03 06:44:34 AM UTC 24 |
Oct 03 06:44:55 AM UTC 24 |
75111000 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1638325886 |
|
|
Oct 03 06:44:32 AM UTC 24 |
Oct 03 06:44:55 AM UTC 24 |
125211300 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1159908090 |
|
|
Oct 03 06:44:13 AM UTC 24 |
Oct 03 06:44:55 AM UTC 24 |
750990500 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3483020554 |
|
|
Oct 03 06:44:31 AM UTC 24 |
Oct 03 06:44:56 AM UTC 24 |
15069300 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3321269073 |
|
|
Oct 03 06:44:39 AM UTC 24 |
Oct 03 06:44:58 AM UTC 24 |
13765300 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3090688180 |
|
|
Oct 03 06:44:35 AM UTC 24 |
Oct 03 06:44:58 AM UTC 24 |
41687000 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3764980231 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:44:59 AM UTC 24 |
324747500 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1268312822 |
|
|
Oct 03 06:44:37 AM UTC 24 |
Oct 03 06:45:00 AM UTC 24 |
125322400 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1138927910 |
|
|
Oct 03 06:44:36 AM UTC 24 |
Oct 03 06:45:01 AM UTC 24 |
129637200 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.322303276 |
|
|
Oct 03 06:44:34 AM UTC 24 |
Oct 03 06:45:01 AM UTC 24 |
36402700 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1237267994 |
|
|
Oct 03 06:44:39 AM UTC 24 |
Oct 03 06:45:01 AM UTC 24 |
20492900 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.921900494 |
|
|
Oct 03 06:44:39 AM UTC 24 |
Oct 03 06:45:01 AM UTC 24 |
24251400 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2010659512 |
|
|
Oct 03 06:44:39 AM UTC 24 |
Oct 03 06:45:03 AM UTC 24 |
104174000 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3694693013 |
|
|
Oct 03 06:44:34 AM UTC 24 |
Oct 03 06:45:04 AM UTC 24 |
237322300 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4251002813 |
|
|
Oct 03 06:44:36 AM UTC 24 |
Oct 03 06:45:04 AM UTC 24 |
295370600 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.523147389 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:45:04 AM UTC 24 |
25507200 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.601027350 |
|
|
Oct 03 06:44:43 AM UTC 24 |
Oct 03 06:45:05 AM UTC 24 |
15130300 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3531896504 |
|
|
Oct 03 06:44:37 AM UTC 24 |
Oct 03 06:45:05 AM UTC 24 |
54224300 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.616994054 |
|
|
Oct 03 06:44:46 AM UTC 24 |
Oct 03 06:45:05 AM UTC 24 |
118065800 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1158366959 |
|
|
Oct 03 06:44:21 AM UTC 24 |
Oct 03 06:45:05 AM UTC 24 |
3096081400 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2501988754 |
|
|
Oct 03 06:44:37 AM UTC 24 |
Oct 03 06:45:06 AM UTC 24 |
36397000 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4116658865 |
|
|
Oct 03 06:44:40 AM UTC 24 |
Oct 03 06:45:06 AM UTC 24 |
68522000 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2869722559 |
|
|
Oct 03 06:44:49 AM UTC 24 |
Oct 03 06:45:09 AM UTC 24 |
75743200 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.3109022305 |
|
|
Oct 03 06:44:52 AM UTC 24 |
Oct 03 06:45:09 AM UTC 24 |
64535700 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.568852472 |
|
|
Oct 03 06:44:41 AM UTC 24 |
Oct 03 06:45:10 AM UTC 24 |
68190100 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2711495585 |
|
|
Oct 03 06:44:53 AM UTC 24 |
Oct 03 06:45:11 AM UTC 24 |
29232900 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.787059147 |
|
|
Oct 03 06:44:43 AM UTC 24 |
Oct 03 06:45:12 AM UTC 24 |
42238500 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2603832283 |
|
|
Oct 03 06:44:49 AM UTC 24 |
Oct 03 06:45:14 AM UTC 24 |
32962900 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.994599671 |
|
|
Oct 03 06:44:53 AM UTC 24 |
Oct 03 06:45:15 AM UTC 24 |
27675800 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3529448800 |
|
|
Oct 03 06:44:52 AM UTC 24 |
Oct 03 06:45:14 AM UTC 24 |
123352600 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4024090131 |
|
|
Oct 03 06:44:50 AM UTC 24 |
Oct 03 06:45:18 AM UTC 24 |
98291100 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2592878063 |
|
|
Oct 03 06:44:57 AM UTC 24 |
Oct 03 06:45:18 AM UTC 24 |
56664100 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2768409889 |
|
|
Oct 03 06:44:56 AM UTC 24 |
Oct 03 06:45:19 AM UTC 24 |
15709200 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3064437982 |
|
|
Oct 03 06:44:16 AM UTC 24 |
Oct 03 06:45:19 AM UTC 24 |
196186400 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3939036414 |
|
|
Oct 03 06:44:31 AM UTC 24 |
Oct 03 06:45:20 AM UTC 24 |
189574700 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1495729992 |
|
|
Oct 03 06:44:50 AM UTC 24 |
Oct 03 06:45:20 AM UTC 24 |
289311800 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1391635218 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:45:20 AM UTC 24 |
4548725400 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3832113510 |
|
|
Oct 03 06:44:59 AM UTC 24 |
Oct 03 06:45:21 AM UTC 24 |
39163800 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3570183562 |
|
|
Oct 03 06:44:56 AM UTC 24 |
Oct 03 06:45:21 AM UTC 24 |
21871800 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4137966731 |
|
|
Oct 03 06:44:58 AM UTC 24 |
Oct 03 06:45:21 AM UTC 24 |
74716100 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1928728843 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:45:21 AM UTC 24 |
78587500 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.647170192 |
|
|
Oct 03 06:45:00 AM UTC 24 |
Oct 03 06:45:22 AM UTC 24 |
105119900 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3784734444 |
|
|
Oct 03 06:44:18 AM UTC 24 |
Oct 03 06:45:22 AM UTC 24 |
649246000 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1553356300 |
|
|
Oct 03 06:45:02 AM UTC 24 |
Oct 03 06:45:23 AM UTC 24 |
70625400 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2459649579 |
|
|
Oct 03 06:44:34 AM UTC 24 |
Oct 03 06:45:23 AM UTC 24 |
4319927600 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.276488420 |
|
|
Oct 03 06:44:54 AM UTC 24 |
Oct 03 06:45:23 AM UTC 24 |
44300900 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1361611084 |
|
|
Oct 03 06:44:52 AM UTC 24 |
Oct 03 06:45:24 AM UTC 24 |
24070300 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2413972939 |
|
|
Oct 03 06:44:53 AM UTC 24 |
Oct 03 06:45:24 AM UTC 24 |
66797900 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2577547062 |
|
|
Oct 03 06:45:02 AM UTC 24 |
Oct 03 06:45:24 AM UTC 24 |
18961500 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1683859580 |
|
|
Oct 03 06:45:02 AM UTC 24 |
Oct 03 06:45:25 AM UTC 24 |
11572000 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2344757517 |
|
|
Oct 03 06:44:13 AM UTC 24 |
Oct 03 06:45:26 AM UTC 24 |
635922400 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3827173029 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:45:26 AM UTC 24 |
1351391400 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1642102740 |
|
|
Oct 03 06:45:04 AM UTC 24 |
Oct 03 06:45:26 AM UTC 24 |
239103200 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2569195700 |
|
|
Oct 03 06:45:03 AM UTC 24 |
Oct 03 06:45:26 AM UTC 24 |
20171900 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.688565505 |
|
|
Oct 03 06:45:04 AM UTC 24 |
Oct 03 06:45:27 AM UTC 24 |
555175300 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3931373919 |
|
|
Oct 03 06:45:06 AM UTC 24 |
Oct 03 06:45:27 AM UTC 24 |
24901100 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2336557389 |
|
|
Oct 03 06:45:06 AM UTC 24 |
Oct 03 06:45:27 AM UTC 24 |
24311200 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3929688799 |
|
|
Oct 03 06:45:05 AM UTC 24 |
Oct 03 06:45:29 AM UTC 24 |
20004600 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1550721450 |
|
|
Oct 03 06:45:08 AM UTC 24 |
Oct 03 06:45:29 AM UTC 24 |
142092900 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1006019162 |
|
|
Oct 03 06:45:05 AM UTC 24 |
Oct 03 06:45:31 AM UTC 24 |
207321500 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3330162473 |
|
|
Oct 03 06:45:15 AM UTC 24 |
Oct 03 06:45:34 AM UTC 24 |
16074200 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.763534728 |
|
|
Oct 03 06:45:04 AM UTC 24 |
Oct 03 06:45:35 AM UTC 24 |
209973000 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1724038004 |
|
|
Oct 03 06:45:10 AM UTC 24 |
Oct 03 06:45:35 AM UTC 24 |
83476100 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3229948108 |
|
|
Oct 03 06:45:12 AM UTC 24 |
Oct 03 06:45:35 AM UTC 24 |
91664800 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.4198078671 |
|
|
Oct 03 06:45:08 AM UTC 24 |
Oct 03 06:45:37 AM UTC 24 |
227940200 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2301433028 |
|
|
Oct 03 06:45:13 AM UTC 24 |
Oct 03 06:45:37 AM UTC 24 |
14953600 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2331632848 |
|
|
Oct 03 06:45:19 AM UTC 24 |
Oct 03 06:45:38 AM UTC 24 |
37524400 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.518417560 |
|
|
Oct 03 06:45:11 AM UTC 24 |
Oct 03 06:45:38 AM UTC 24 |
35267600 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1426288686 |
|
|
Oct 03 06:45:15 AM UTC 24 |
Oct 03 06:45:39 AM UTC 24 |
21303300 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4014616435 |
|
|
Oct 03 06:45:18 AM UTC 24 |
Oct 03 06:45:41 AM UTC 24 |
92571900 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1146411096 |
|
|
Oct 03 06:45:16 AM UTC 24 |
Oct 03 06:45:41 AM UTC 24 |
329126600 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.1347286220 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:42 AM UTC 24 |
19837500 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3784771971 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:43 AM UTC 24 |
32648500 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.616921876 |
|
|
Oct 03 06:45:24 AM UTC 24 |
Oct 03 06:45:43 AM UTC 24 |
29989900 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.545328526 |
|
|
Oct 03 06:45:26 AM UTC 24 |
Oct 03 06:45:44 AM UTC 24 |
251081300 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4118350020 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:44 AM UTC 24 |
79489200 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1633743430 |
|
|
Oct 03 06:45:19 AM UTC 24 |
Oct 03 06:45:44 AM UTC 24 |
113805700 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3440639436 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:44 AM UTC 24 |
43515300 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1126992482 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:45 AM UTC 24 |
22969300 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.344820960 |
|
|
Oct 03 06:45:28 AM UTC 24 |
Oct 03 06:45:46 AM UTC 24 |
11329400 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3930784015 |
|
|
Oct 03 06:45:24 AM UTC 24 |
Oct 03 06:45:48 AM UTC 24 |
31136200 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2655165902 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:48 AM UTC 24 |
418772700 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2138410110 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:48 AM UTC 24 |
209640900 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2396701289 |
|
|
Oct 03 06:44:34 AM UTC 24 |
Oct 03 06:45:49 AM UTC 24 |
5687565600 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.458326130 |
|
|
Oct 03 06:45:30 AM UTC 24 |
Oct 03 06:45:49 AM UTC 24 |
47237700 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2362792968 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:49 AM UTC 24 |
411849400 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.4150474225 |
|
|
Oct 03 06:45:29 AM UTC 24 |
Oct 03 06:45:50 AM UTC 24 |
11405200 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2084028337 |
|
|
Oct 03 06:45:24 AM UTC 24 |
Oct 03 06:45:50 AM UTC 24 |
70119200 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4263313316 |
|
|
Oct 03 06:45:26 AM UTC 24 |
Oct 03 06:45:51 AM UTC 24 |
77187500 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1588615427 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:51 AM UTC 24 |
69381200 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.983398815 |
|
|
Oct 03 06:45:28 AM UTC 24 |
Oct 03 06:45:51 AM UTC 24 |
55995000 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1406497994 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:52 AM UTC 24 |
64567600 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2909225648 |
|
|
Oct 03 06:45:30 AM UTC 24 |
Oct 03 06:45:54 AM UTC 24 |
70887400 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2463269681 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:45:54 AM UTC 24 |
419158200 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.725681240 |
|
|
Oct 03 06:45:28 AM UTC 24 |
Oct 03 06:45:56 AM UTC 24 |
461332000 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4153311702 |
|
|
Oct 03 06:45:28 AM UTC 24 |
Oct 03 06:45:57 AM UTC 24 |
593581100 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.2783453313 |
|
|
Oct 03 06:45:38 AM UTC 24 |
Oct 03 06:45:57 AM UTC 24 |
32935100 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2399121928 |
|
|
Oct 03 06:45:32 AM UTC 24 |
Oct 03 06:45:57 AM UTC 24 |
37145800 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2881715722 |
|
|
Oct 03 06:45:35 AM UTC 24 |
Oct 03 06:45:59 AM UTC 24 |
176357100 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.592758634 |
|
|
Oct 03 06:45:36 AM UTC 24 |
Oct 03 06:45:59 AM UTC 24 |
41250100 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3121788022 |
|
|
Oct 03 06:45:37 AM UTC 24 |
Oct 03 06:46:01 AM UTC 24 |
38527900 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2118412463 |
|
|
Oct 03 06:45:39 AM UTC 24 |
Oct 03 06:46:02 AM UTC 24 |
123041100 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2287425852 |
|
|
Oct 03 06:45:44 AM UTC 24 |
Oct 03 06:46:03 AM UTC 24 |
29906200 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3386429217 |
|
|
Oct 03 06:45:40 AM UTC 24 |
Oct 03 06:46:03 AM UTC 24 |
346113000 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.109315400 |
|
|
Oct 03 06:45:39 AM UTC 24 |
Oct 03 06:46:03 AM UTC 24 |
167874200 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4221187106 |
|
|
Oct 03 06:45:35 AM UTC 24 |
Oct 03 06:46:05 AM UTC 24 |
64208400 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2213524880 |
|
|
Oct 03 06:45:45 AM UTC 24 |
Oct 03 06:46:06 AM UTC 24 |
40882800 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4231640000 |
|
|
Oct 03 06:45:44 AM UTC 24 |
Oct 03 06:46:08 AM UTC 24 |
36333200 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.543431629 |
|
|
Oct 03 06:45:44 AM UTC 24 |
Oct 03 06:46:08 AM UTC 24 |
33983000 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.1359538068 |
|
|
Oct 03 06:45:51 AM UTC 24 |
Oct 03 06:46:08 AM UTC 24 |
42110100 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.402998615 |
|
|
Oct 03 06:45:43 AM UTC 24 |
Oct 03 06:46:09 AM UTC 24 |
19416400 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2896862450 |
|
|
Oct 03 06:45:47 AM UTC 24 |
Oct 03 06:46:09 AM UTC 24 |
24657900 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.506627200 |
|
|
Oct 03 06:45:51 AM UTC 24 |
Oct 03 06:46:09 AM UTC 24 |
17752400 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1178865712 |
|
|
Oct 03 06:45:49 AM UTC 24 |
Oct 03 06:46:09 AM UTC 24 |
12917000 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.800387468 |
|
|
Oct 03 06:45:50 AM UTC 24 |
Oct 03 06:46:09 AM UTC 24 |
17869900 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3737689081 |
|
|
Oct 03 06:45:49 AM UTC 24 |
Oct 03 06:46:10 AM UTC 24 |
73432600 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1563009858 |
|
|
Oct 03 06:45:25 AM UTC 24 |
Oct 03 06:46:10 AM UTC 24 |
864337500 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.3783374177 |
|
|
Oct 03 06:45:51 AM UTC 24 |
Oct 03 06:46:10 AM UTC 24 |
67750300 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2040878249 |
|
|
Oct 03 06:45:50 AM UTC 24 |
Oct 03 06:46:11 AM UTC 24 |
363404700 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.4272673770 |
|
|
Oct 03 06:45:50 AM UTC 24 |
Oct 03 06:46:11 AM UTC 24 |
28177600 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2328077105 |
|
|
Oct 03 06:45:45 AM UTC 24 |
Oct 03 06:46:14 AM UTC 24 |
323717300 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3772704976 |
|
|
Oct 03 06:45:42 AM UTC 24 |
Oct 03 06:46:14 AM UTC 24 |
69282900 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3471649742 |
|
|
Oct 03 06:45:55 AM UTC 24 |
Oct 03 06:46:15 AM UTC 24 |
25698000 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.708263817 |
|
|
Oct 03 06:45:51 AM UTC 24 |
Oct 03 06:46:15 AM UTC 24 |
58828400 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.4057290815 |
|
|
Oct 03 06:45:57 AM UTC 24 |
Oct 03 06:46:16 AM UTC 24 |
58518600 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2668552783 |
|
|
Oct 03 06:45:53 AM UTC 24 |
Oct 03 06:46:16 AM UTC 24 |
81740800 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1443718274 |
|
|
Oct 03 06:45:58 AM UTC 24 |
Oct 03 06:46:17 AM UTC 24 |
15347700 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.428337163 |
|
|
Oct 03 06:45:56 AM UTC 24 |
Oct 03 06:46:18 AM UTC 24 |
18464900 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.1683258394 |
|
|
Oct 03 06:45:59 AM UTC 24 |
Oct 03 06:46:19 AM UTC 24 |
14722700 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1829107417 |
|
|
Oct 03 06:45:49 AM UTC 24 |
Oct 03 06:46:19 AM UTC 24 |
35500100 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.3165590861 |
|
|
Oct 03 06:45:58 AM UTC 24 |
Oct 03 06:46:20 AM UTC 24 |
17377600 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.707022035 |
|
|
Oct 03 06:46:03 AM UTC 24 |
Oct 03 06:46:21 AM UTC 24 |
31836100 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.3121956606 |
|
|
Oct 03 06:46:00 AM UTC 24 |
Oct 03 06:46:21 AM UTC 24 |
30890200 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.1418113935 |
|
|
Oct 03 06:46:00 AM UTC 24 |
Oct 03 06:46:22 AM UTC 24 |
16037300 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.2256929182 |
|
|
Oct 03 06:46:03 AM UTC 24 |
Oct 03 06:46:22 AM UTC 24 |
16358600 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.124004346 |
|
|
Oct 03 06:46:01 AM UTC 24 |
Oct 03 06:46:22 AM UTC 24 |
81066000 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.1971011739 |
|
|
Oct 03 06:46:05 AM UTC 24 |
Oct 03 06:46:23 AM UTC 24 |
14382000 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.2110095252 |
|
|
Oct 03 06:46:04 AM UTC 24 |
Oct 03 06:46:23 AM UTC 24 |
16531600 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.652779588 |
|
|
Oct 03 06:46:04 AM UTC 24 |
Oct 03 06:46:24 AM UTC 24 |
22031300 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.1812437800 |
|
|
Oct 03 06:46:10 AM UTC 24 |
Oct 03 06:46:28 AM UTC 24 |
56133600 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.2506418157 |
|
|
Oct 03 06:46:10 AM UTC 24 |
Oct 03 06:46:28 AM UTC 24 |
48044000 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.1660824751 |
|
|
Oct 03 06:46:10 AM UTC 24 |
Oct 03 06:46:28 AM UTC 24 |
46595400 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.3632626317 |
|
|
Oct 03 06:46:10 AM UTC 24 |
Oct 03 06:46:29 AM UTC 24 |
41641500 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2943512260 |
|
|
Oct 03 06:46:09 AM UTC 24 |
Oct 03 06:46:29 AM UTC 24 |
51190300 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.2942074040 |
|
|
Oct 03 06:46:10 AM UTC 24 |
Oct 03 06:46:29 AM UTC 24 |
18636100 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2890714330 |
|
|
Oct 03 06:46:06 AM UTC 24 |
Oct 03 06:46:29 AM UTC 24 |
14414900 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.3654388526 |
|
|
Oct 03 06:46:09 AM UTC 24 |
Oct 03 06:46:30 AM UTC 24 |
17119100 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.414339761 |
|
|
Oct 03 06:46:13 AM UTC 24 |
Oct 03 06:46:32 AM UTC 24 |
135857800 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.17625016 |
|
|
Oct 03 06:45:45 AM UTC 24 |
Oct 03 06:46:32 AM UTC 24 |
228389400 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.416838888 |
|
|
Oct 03 06:45:50 AM UTC 24 |
Oct 03 06:46:38 AM UTC 24 |
311364700 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3667890924 |
|
|
Oct 03 06:45:02 AM UTC 24 |
Oct 03 06:52:55 AM UTC 24 |
1760176400 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.835477258 |
|
|
Oct 03 06:44:12 AM UTC 24 |
Oct 03 06:53:30 AM UTC 24 |
487961300 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3727004295 |
|
|
Oct 03 06:44:14 AM UTC 24 |
Oct 03 06:53:30 AM UTC 24 |
876355300 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2551832380 |
|
|
Oct 03 06:44:29 AM UTC 24 |
Oct 03 06:53:35 AM UTC 24 |
373584700 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2591799615 |
|
|
Oct 03 06:44:35 AM UTC 24 |
Oct 03 06:53:50 AM UTC 24 |
676948900 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.123692840 |
|
|
Oct 03 06:44:41 AM UTC 24 |
Oct 03 06:53:58 AM UTC 24 |
1802155100 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1285097110 |
|
|
Oct 03 06:44:56 AM UTC 24 |
Oct 03 06:54:11 AM UTC 24 |
411569200 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.857045643 |
|
|
Oct 03 06:45:19 AM UTC 24 |
Oct 03 06:54:33 AM UTC 24 |
1394216000 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.729279780 |
|
|
Oct 03 06:45:35 AM UTC 24 |
Oct 03 06:54:43 AM UTC 24 |
435008500 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.148681204 |
|
|
Oct 03 06:45:42 AM UTC 24 |
Oct 03 06:54:55 AM UTC 24 |
530027400 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3990181715 |
|
|
Oct 03 06:44:10 AM UTC 24 |
Oct 03 06:59:14 AM UTC 24 |
347653300 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.657249235 |
|
|
Oct 03 06:45:28 AM UTC 24 |
Oct 03 07:00:18 AM UTC 24 |
1324426900 ps |