| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.02 | 95.22 | 93.82 | 98.31 | 92.52 | 97.12 | 96.99 | 98.15 |
| T361 | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.122770950 | Oct 03 06:44:10 AM UTC 24 | Oct 03 07:02:20 AM UTC 24 | 1567260800 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2686550855 | Oct 03 06:44:37 AM UTC 24 | Oct 03 07:03:08 AM UTC 24 | 3819583100 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2984270213 | Oct 03 06:44:52 AM UTC 24 | Oct 03 07:03:25 AM UTC 24 | 1294945900 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.880758982 | Oct 03 06:45:11 AM UTC 24 | Oct 03 07:03:59 AM UTC 24 | 937996300 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1876402755 | Oct 03 06:45:05 AM UTC 24 | Oct 03 07:04:00 AM UTC 24 | 840526700 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1156469350 | Oct 03 06:45:25 AM UTC 24 | Oct 03 07:04:23 AM UTC 24 | 712717200 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2263987491 | Oct 03 06:45:25 AM UTC 24 | Oct 03 07:04:28 AM UTC 24 | 718239000 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.827599446 | Oct 03 06:45:46 AM UTC 24 | Oct 03 07:04:29 AM UTC 24 | 941397000 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2467602662 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2585929600 ps |
| CPU time | 101 seconds |
| Started | Oct 03 07:08:10 AM UTC 24 |
| Finished | Oct 03 07:09:54 AM UTC 24 |
| Peak memory | 272924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467602662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2467602662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.333857502 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1761748500 ps |
| CPU time | 246.12 seconds |
| Started | Oct 03 07:12:15 AM UTC 24 |
| Finished | Oct 03 07:16:26 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=333857502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.333857502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3150807015 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 181738700 ps |
| CPU time | 21.71 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:33 AM UTC 24 |
| Peak memory | 286624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3150807015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3150807015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.1711548754 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 100146828100 ps |
| CPU time | 936.64 seconds |
| Started | Oct 03 07:05:05 AM UTC 24 |
| Finished | Oct 03 07:20:56 AM UTC 24 |
| Peak memory | 275176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711548754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.1711548754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.1099436274 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 15801857800 ps |
| CPU time | 698.58 seconds |
| Started | Oct 03 07:05:42 AM UTC 24 |
| Finished | Oct 03 07:17:31 AM UTC 24 |
| Peak memory | 283352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1099436274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.1099436274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.3783799148 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3470743000 ps |
| CPU time | 125.39 seconds |
| Started | Oct 03 07:05:01 AM UTC 24 |
| Finished | Oct 03 07:07:09 AM UTC 24 |
| Peak memory | 270988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783799148 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.3783799148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2541033743 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 977157200 ps |
| CPU time | 7200.31 seconds |
| Started | Oct 03 07:20:00 AM UTC 24 |
| Finished | Oct 03 09:21:30 AM UTC 24 |
| Peak memory | 314192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541033743 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.2541033743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2531051348 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 406395300 ps |
| CPU time | 21.89 seconds |
| Started | Oct 03 06:44:28 AM UTC 24 |
| Finished | Oct 03 06:44:50 AM UTC 24 |
| Peak memory | 286624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2531051348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2531051348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.2230307686 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 6318445900 ps |
| CPU time | 493.16 seconds |
| Started | Oct 03 07:05:04 AM UTC 24 |
| Finished | Oct 03 07:13:25 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230307686 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2230307686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.1371639107 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 201779500 ps |
| CPU time | 47.48 seconds |
| Started | Oct 03 07:19:07 AM UTC 24 |
| Finished | Oct 03 07:19:56 AM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1371639107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct rl_rw_evict_all_en.1371639107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2708960698 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 325629000 ps |
| CPU time | 36.92 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:44:50 AM UTC 24 |
| Peak memory | 276324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708960698 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.2708960698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.572710968 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 155757900 ps |
| CPU time | 128.63 seconds |
| Started | Oct 03 08:48:23 AM UTC 24 |
| Finished | Oct 03 08:50:34 AM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572710968 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.572710968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.1594722586 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 79029375400 ps |
| CPU time | 1008.55 seconds |
| Started | Oct 03 07:22:28 AM UTC 24 |
| Finished | Oct 03 07:39:32 AM UTC 24 |
| Peak memory | 272972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1594722586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. flash_ctrl_rma_err.1594722586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.2013004297 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 40276100 ps |
| CPU time | 224.46 seconds |
| Started | Oct 03 07:43:53 AM UTC 24 |
| Finished | Oct 03 07:47:42 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013004297 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.2013004297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1315220989 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 303245500 ps |
| CPU time | 36.25 seconds |
| Started | Oct 03 07:05:43 AM UTC 24 |
| Finished | Oct 03 07:06:21 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 15220989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc h_code.1315220989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2592878063 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 56664100 ps |
| CPU time | 19.78 seconds |
| Started | Oct 03 06:44:57 AM UTC 24 |
| Finished | Oct 03 06:45:18 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592878063 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2592878063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2973900780 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 172527534400 ps |
| CPU time | 337.34 seconds |
| Started | Oct 03 07:17:33 AM UTC 24 |
| Finished | Oct 03 07:23:16 AM UTC 24 |
| Peak memory | 303856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2973900780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_intr_rd_slow_flash.2973900780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.683651058 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1898435200 ps |
| CPU time | 121.04 seconds |
| Started | Oct 03 07:41:00 AM UTC 24 |
| Finished | Oct 03 07:43:03 AM UTC 24 |
| Peak memory | 270880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683651058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.683651058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.123692840 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1802155100 ps |
| CPU time | 550.58 seconds |
| Started | Oct 03 06:44:41 AM UTC 24 |
| Finished | Oct 03 06:53:58 AM UTC 24 |
| Peak memory | 276592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123692840 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.123692840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3306483176 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 10020510400 ps |
| CPU time | 201.33 seconds |
| Started | Oct 03 07:23:01 AM UTC 24 |
| Finished | Oct 03 07:26:26 AM UTC 24 |
| Peak memory | 304132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3306483176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3306483176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1589179429 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 196264800 ps |
| CPU time | 20.75 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:33 AM UTC 24 |
| Peak memory | 276332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589179429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.1589179429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3442718529 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 69923300 ps |
| CPU time | 30.34 seconds |
| Started | Oct 03 07:42:50 AM UTC 24 |
| Finished | Oct 03 07:43:22 AM UTC 24 |
| Peak memory | 271248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442718529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_wr_intg.3442718529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3262125934 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 50587800 ps |
| CPU time | 18.54 seconds |
| Started | Oct 03 06:44:29 AM UTC 24 |
| Finished | Oct 03 06:44:48 AM UTC 24 |
| Peak memory | 276532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262125934 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3262125934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4148568260 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5446843500 ps |
| CPU time | 87.88 seconds |
| Started | Oct 03 07:08:03 AM UTC 24 |
| Finished | Oct 03 07:09:33 AM UTC 24 |
| Peak memory | 270920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148568260 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.4148568260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3330855518 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 5463220800 ps |
| CPU time | 102.26 seconds |
| Started | Oct 03 08:13:35 AM UTC 24 |
| Finished | Oct 03 08:15:20 AM UTC 24 |
| Peak memory | 275156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330855518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.3330855518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.385491600 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 5301191300 ps |
| CPU time | 200.87 seconds |
| Started | Oct 03 07:14:27 AM UTC 24 |
| Finished | Oct 03 07:17:51 AM UTC 24 |
| Peak memory | 296080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=385491600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.flash_ctrl_rw_derr.385491600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.1620019104 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 241544490800 ps |
| CPU time | 2548.6 seconds |
| Started | Oct 03 07:36:39 AM UTC 24 |
| Finished | Oct 03 08:19:35 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620019104 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.1620019104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2142559370 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 121548400 ps |
| CPU time | 21.52 seconds |
| Started | Oct 03 07:24:02 AM UTC 24 |
| Finished | Oct 03 07:24:25 AM UTC 24 |
| Peak memory | 269316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142559370 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2142559370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.774424558 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1112656500 ps |
| CPU time | 261.29 seconds |
| Started | Oct 03 07:51:37 AM UTC 24 |
| Finished | Oct 03 07:56:03 AM UTC 24 |
| Peak memory | 289992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=774424558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 4.flash_ctrl_derr_detect.774424558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.2184913215 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 43490800 ps |
| CPU time | 188.54 seconds |
| Started | Oct 03 07:40:41 AM UTC 24 |
| Finished | Oct 03 07:43:53 AM UTC 24 |
| Peak memory | 271348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184913215 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.2184913215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.1812234444 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 335881500 ps |
| CPU time | 176.48 seconds |
| Started | Oct 03 08:47:30 AM UTC 24 |
| Finished | Oct 03 08:50:31 AM UTC 24 |
| Peak memory | 271204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812234444 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.1812234444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.797826618 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 181150200 ps |
| CPU time | 48.41 seconds |
| Started | Oct 03 07:19:09 AM UTC 24 |
| Finished | Oct 03 07:19:59 AM UTC 24 |
| Peak memory | 283580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797826618 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.797826618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.224353833 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 910316000 ps |
| CPU time | 147.54 seconds |
| Started | Oct 03 08:21:15 AM UTC 24 |
| Finished | Oct 03 08:23:45 AM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224353833 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.224353833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2778060718 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 10032815300 ps |
| CPU time | 99.93 seconds |
| Started | Oct 03 07:48:18 AM UTC 24 |
| Finished | Oct 03 07:50:01 AM UTC 24 |
| Peak memory | 301904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2778060718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2778060718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.2017805374 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 48461600 ps |
| CPU time | 20.77 seconds |
| Started | Oct 03 07:22:37 AM UTC 24 |
| Finished | Oct 03 07:22:59 AM UTC 24 |
| Peak memory | 271372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2017805374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_lcmgr_intg.2017805374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.4211033874 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 145892506300 ps |
| CPU time | 588.67 seconds |
| Started | Oct 03 07:38:15 AM UTC 24 |
| Finished | Oct 03 07:48:12 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=4211033874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.4211033874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1517381830 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 71984500 ps |
| CPU time | 20.45 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:32 AM UTC 24 |
| Peak memory | 276528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517381830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.1517381830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2984270213 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1294945900 ps |
| CPU time | 1100.82 seconds |
| Started | Oct 03 06:44:52 AM UTC 24 |
| Finished | Oct 03 07:03:25 AM UTC 24 |
| Peak memory | 278516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984270213 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.2984270213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.299151715 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1581774100 ps |
| CPU time | 232.79 seconds |
| Started | Oct 03 07:15:11 AM UTC 24 |
| Finished | Oct 03 07:19:08 AM UTC 24 |
| Peak memory | 302092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=299151715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_oversize_error.299151715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.4279128077 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 27222035600 ps |
| CPU time | 197.27 seconds |
| Started | Oct 03 07:48:53 AM UTC 24 |
| Finished | Oct 03 07:52:14 AM UTC 24 |
| Peak memory | 273296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279128077 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.4279128077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.1263649715 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 895714600 ps |
| CPU time | 27.93 seconds |
| Started | Oct 03 07:47:55 AM UTC 24 |
| Finished | Oct 03 07:48:24 AM UTC 24 |
| Peak memory | 275560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=1263649715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1263649715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3237475264 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 15527800 ps |
| CPU time | 24.84 seconds |
| Started | Oct 03 07:48:13 AM UTC 24 |
| Finished | Oct 03 07:48:40 AM UTC 24 |
| Peak memory | 271084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3237475264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.3237475264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.1318121222 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 84089900 ps |
| CPU time | 38.21 seconds |
| Started | Oct 03 08:02:47 AM UTC 24 |
| Finished | Oct 03 08:03:26 AM UTC 24 |
| Peak memory | 285652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1318121222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c trl_disable.1318121222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.568852472 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 68190100 ps |
| CPU time | 27.73 seconds |
| Started | Oct 03 06:44:41 AM UTC 24 |
| Finished | Oct 03 06:45:10 AM UTC 24 |
| Peak memory | 276332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568852472 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.568852472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.3608882933 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2563236600 ps |
| CPU time | 143.23 seconds |
| Started | Oct 03 07:14:22 AM UTC 24 |
| Finished | Oct 03 07:16:48 AM UTC 24 |
| Peak memory | 291848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608882933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.3608882933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.233608578 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1982284200 ps |
| CPU time | 224.11 seconds |
| Started | Oct 03 07:16:26 AM UTC 24 |
| Finished | Oct 03 07:20:14 AM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233608578 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.233608578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1391635218 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4548725400 ps |
| CPU time | 68.35 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:45:20 AM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391635218 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.1391635218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.2013922260 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 201171800 ps |
| CPU time | 52.66 seconds |
| Started | Oct 03 08:06:06 AM UTC 24 |
| Finished | Oct 03 08:07:00 AM UTC 24 |
| Peak memory | 283588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013922260 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.2013922260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.562532590 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 107365400 ps |
| CPU time | 24.22 seconds |
| Started | Oct 03 07:43:05 AM UTC 24 |
| Finished | Oct 03 07:43:30 AM UTC 24 |
| Peak memory | 293120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562532590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.562532590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.332295653 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 33799700 ps |
| CPU time | 21.73 seconds |
| Started | Oct 03 07:21:35 AM UTC 24 |
| Finished | Oct 03 07:21:58 AM UTC 24 |
| Peak memory | 273292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=332295653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.332295653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.133324180 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 525379000 ps |
| CPU time | 36.35 seconds |
| Started | Oct 03 07:40:43 AM UTC 24 |
| Finished | Oct 03 07:41:21 AM UTC 24 |
| Peak memory | 273104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13 3324180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch _code.133324180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.4267073199 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 20820500 ps |
| CPU time | 20.95 seconds |
| Started | Oct 03 07:40:00 AM UTC 24 |
| Finished | Oct 03 07:40:22 AM UTC 24 |
| Peak memory | 273508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=4267073199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.4267073199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.1231927835 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 29839100 ps |
| CPU time | 45.52 seconds |
| Started | Oct 03 07:18:19 AM UTC 24 |
| Finished | Oct 03 07:19:06 AM UTC 24 |
| Peak memory | 285656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231927835 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.1231927835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3990181715 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 347653300 ps |
| CPU time | 893.94 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:59:14 AM UTC 24 |
| Peak memory | 278540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990181715 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.3990181715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.3020074660 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 27000100 ps |
| CPU time | 28.48 seconds |
| Started | Oct 03 08:20:13 AM UTC 24 |
| Finished | Oct 03 08:20:43 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3020074660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_lcmgr_intg.3020074660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3931373919 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 24901100 ps |
| CPU time | 19.57 seconds |
| Started | Oct 03 06:45:06 AM UTC 24 |
| Finished | Oct 03 06:45:27 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931373919 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.3931373919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.3473143158 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 15534900 ps |
| CPU time | 21.16 seconds |
| Started | Oct 03 07:22:46 AM UTC 24 |
| Finished | Oct 03 07:23:08 AM UTC 24 |
| Peak memory | 269248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3473143158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3473143158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2723084756 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 10019788900 ps |
| CPU time | 115.67 seconds |
| Started | Oct 03 07:40:16 AM UTC 24 |
| Finished | Oct 03 07:42:14 AM UTC 24 |
| Peak memory | 296148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2723084756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2723084756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.2133240114 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 16380500 ps |
| CPU time | 23.91 seconds |
| Started | Oct 03 07:20:44 AM UTC 24 |
| Finished | Oct 03 07:21:09 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133240114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2133240114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.2709915280 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 7274110400 ps |
| CPU time | 563.74 seconds |
| Started | Oct 03 07:41:13 AM UTC 24 |
| Finished | Oct 03 07:50:44 AM UTC 24 |
| Peak memory | 320512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709915280 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.2709915280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.2982907950 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3801257300 ps |
| CPU time | 3519.43 seconds |
| Started | Oct 03 07:06:22 AM UTC 24 |
| Finished | Oct 03 08:05:48 AM UTC 24 |
| Peak memory | 277940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29 82907950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _error_prog_type.2982907950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1253576780 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 586885600 ps |
| CPU time | 1211.19 seconds |
| Started | Oct 03 07:07:10 AM UTC 24 |
| Finished | Oct 03 07:27:39 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253576780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1253576780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.2170981678 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 160170714900 ps |
| CPU time | 806.38 seconds |
| Started | Oct 03 07:43:51 AM UTC 24 |
| Finished | Oct 03 07:57:28 AM UTC 24 |
| Peak memory | 275048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170981678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.2170981678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2988282676 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1299536100 ps |
| CPU time | 45.83 seconds |
| Started | Oct 03 07:21:40 AM UTC 24 |
| Finished | Oct 03 07:22:28 AM UTC 24 |
| Peak memory | 273444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988282 676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_f s_sup.2988282676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1727011582 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 163502200 ps |
| CPU time | 48.74 seconds |
| Started | Oct 03 08:09:30 AM UTC 24 |
| Finished | Oct 03 08:10:20 AM UTC 24 |
| Peak memory | 287684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727011582 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.1727011582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.859243433 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2760239400 ps |
| CPU time | 6787.7 seconds |
| Started | Oct 03 07:39:33 AM UTC 24 |
| Finished | Oct 03 09:34:00 AM UTC 24 |
| Peak memory | 314200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859243433 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.859243433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1876402755 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 840526700 ps |
| CPU time | 1121.67 seconds |
| Started | Oct 03 06:45:05 AM UTC 24 |
| Finished | Oct 03 07:04:00 AM UTC 24 |
| Peak memory | 278508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876402755 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.1876402755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2263987491 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 718239000 ps |
| CPU time | 1130.31 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 07:04:28 AM UTC 24 |
| Peak memory | 278488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263987491 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.2263987491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.95269151 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 696765900 ps |
| CPU time | 55.17 seconds |
| Started | Oct 03 08:15:33 AM UTC 24 |
| Finished | Oct 03 08:16:30 AM UTC 24 |
| Peak memory | 285592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95269151 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.95269151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2281169117 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1762117500 ps |
| CPU time | 82.27 seconds |
| Started | Oct 03 08:16:03 AM UTC 24 |
| Finished | Oct 03 08:17:27 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281169117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2281169117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.3285474283 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1668358400 ps |
| CPU time | 85.52 seconds |
| Started | Oct 03 08:24:12 AM UTC 24 |
| Finished | Oct 03 08:25:39 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285474283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3285474283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.2074310429 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2995670300 ps |
| CPU time | 93.13 seconds |
| Started | Oct 03 08:32:52 AM UTC 24 |
| Finished | Oct 03 08:34:27 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074310429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2074310429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.2036784077 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 39415500 ps |
| CPU time | 54.56 seconds |
| Started | Oct 03 08:40:46 AM UTC 24 |
| Finished | Oct 03 08:41:43 AM UTC 24 |
| Peak memory | 287604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2036784077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_c trl_rw_evict_all_en.2036784077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.3000930557 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3363237700 ps |
| CPU time | 89.11 seconds |
| Started | Oct 03 08:46:24 AM UTC 24 |
| Finished | Oct 03 08:47:56 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000930557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.3000930557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.2561685904 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 69156600 ps |
| CPU time | 50.54 seconds |
| Started | Oct 03 07:39:46 AM UTC 24 |
| Finished | Oct 03 07:40:38 AM UTC 24 |
| Peak memory | 287548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256168590 4 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.2561685904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.3977410483 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 719291300 ps |
| CPU time | 24.67 seconds |
| Started | Oct 03 07:21:47 AM UTC 24 |
| Finished | Oct 03 07:22:13 AM UTC 24 |
| Peak memory | 273696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3977410483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3977410483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2655165902 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 418772700 ps |
| CPU time | 21.52 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:48 AM UTC 24 |
| Peak memory | 276340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655165902 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.2655165902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.1939940751 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 24914500 ps |
| CPU time | 22.75 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:44:36 AM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939940751 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.1939940751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.15937201 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 123097600 ps |
| CPU time | 40.43 seconds |
| Started | Oct 03 08:34:08 AM UTC 24 |
| Finished | Oct 03 08:34:50 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15937201 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.15937201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.2989159040 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 11437204300 ps |
| CPU time | 3333.57 seconds |
| Started | Oct 03 07:40:55 AM UTC 24 |
| Finished | Oct 03 08:37:07 AM UTC 24 |
| Peak memory | 275808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989159040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.2989159040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2536001606 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 766580000 ps |
| CPU time | 25.64 seconds |
| Started | Oct 03 07:53:41 AM UTC 24 |
| Finished | Oct 03 07:54:08 AM UTC 24 |
| Peak memory | 275528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=2536001606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2536001606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2934197652 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 582161100 ps |
| CPU time | 178.21 seconds |
| Started | Oct 03 07:05:08 AM UTC 24 |
| Finished | Oct 03 07:08:10 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934197652 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.2934197652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1156469350 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 712717200 ps |
| CPU time | 1124.89 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 07:04:23 AM UTC 24 |
| Peak memory | 278508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156469350 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.1156469350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.729279780 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 435008500 ps |
| CPU time | 541.08 seconds |
| Started | Oct 03 06:45:35 AM UTC 24 |
| Finished | Oct 03 06:54:43 AM UTC 24 |
| Peak memory | 276396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729279780 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.729279780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2190368723 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 57089400 ps |
| CPU time | 21.14 seconds |
| Started | Oct 03 07:22:22 AM UTC 24 |
| Finished | Oct 03 07:22:45 AM UTC 24 |
| Peak memory | 273252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190368723 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.2190368723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.1569273664 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 37399200 ps |
| CPU time | 32.57 seconds |
| Started | Oct 03 07:19:57 AM UTC 24 |
| Finished | Oct 03 07:20:31 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1569273664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_disable.1569273664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.2291310558 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 16862000 ps |
| CPU time | 33.33 seconds |
| Started | Oct 03 07:39:32 AM UTC 24 |
| Finished | Oct 03 07:40:07 AM UTC 24 |
| Peak memory | 285432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2291310558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_disable.2291310558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.3287703478 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 40121594700 ps |
| CPU time | 967 seconds |
| Started | Oct 03 07:30:27 AM UTC 24 |
| Finished | Oct 03 07:46:48 AM UTC 24 |
| Peak memory | 275048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287703478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.3287703478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.2963505282 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 80664500 ps |
| CPU time | 48.68 seconds |
| Started | Oct 03 07:39:27 AM UTC 24 |
| Finished | Oct 03 07:40:17 AM UTC 24 |
| Peak memory | 287612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2963505282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct rl_rw_evict_all_en.2963505282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.1538632203 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 28345100 ps |
| CPU time | 42.12 seconds |
| Started | Oct 03 08:17:38 AM UTC 24 |
| Finished | Oct 03 08:18:22 AM UTC 24 |
| Peak memory | 287868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1538632203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c trl_rw_evict_all_en.1538632203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.4228070590 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 346422300 ps |
| CPU time | 47 seconds |
| Started | Oct 03 08:22:15 AM UTC 24 |
| Finished | Oct 03 08:23:03 AM UTC 24 |
| Peak memory | 283576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228070590 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.4228070590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.935337526 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 9063527900 ps |
| CPU time | 69.18 seconds |
| Started | Oct 03 08:26:32 AM UTC 24 |
| Finished | Oct 03 08:27:43 AM UTC 24 |
| Peak memory | 275156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935337526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.935337526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1797762860 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 21004200 ps |
| CPU time | 38.67 seconds |
| Started | Oct 03 08:30:31 AM UTC 24 |
| Finished | Oct 03 08:31:12 AM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1797762860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ ctrl_disable.1797762860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.3597860579 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 23671900 ps |
| CPU time | 35.6 seconds |
| Started | Oct 03 08:34:27 AM UTC 24 |
| Finished | Oct 03 08:35:04 AM UTC 24 |
| Peak memory | 285516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3597860579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ ctrl_disable.3597860579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.4179771433 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 16495000 ps |
| CPU time | 36.57 seconds |
| Started | Oct 03 08:36:18 AM UTC 24 |
| Finished | Oct 03 08:36:56 AM UTC 24 |
| Peak memory | 285820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4179771433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ ctrl_disable.4179771433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.3923813954 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 12759000 ps |
| CPU time | 30.03 seconds |
| Started | Oct 03 08:37:41 AM UTC 24 |
| Finished | Oct 03 08:38:13 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3923813954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ ctrl_disable.3923813954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.4195374985 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4927471800 ps |
| CPU time | 87.66 seconds |
| Started | Oct 03 07:16:48 AM UTC 24 |
| Finished | Oct 03 07:18:18 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195374985 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.4195374985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.3395379378 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 88730600 ps |
| CPU time | 21.95 seconds |
| Started | Oct 03 07:40:08 AM UTC 24 |
| Finished | Oct 03 07:40:31 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395379378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3395379378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.3393425776 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3363992700 ps |
| CPU time | 561.27 seconds |
| Started | Oct 03 08:17:03 AM UTC 24 |
| Finished | Oct 03 08:26:31 AM UTC 24 |
| Peak memory | 330740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393425776 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.3393425776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.4207193962 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 301638530000 ps |
| CPU time | 2549.5 seconds |
| Started | Oct 03 07:05:08 AM UTC 24 |
| Finished | Oct 03 07:48:12 AM UTC 24 |
| Peak memory | 278060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207193962 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.4207193962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.3643636202 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 219979500 ps |
| CPU time | 86.27 seconds |
| Started | Oct 03 07:26:26 AM UTC 24 |
| Finished | Oct 03 07:27:55 AM UTC 24 |
| Peak memory | 273288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643636202 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3643636202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.1430416810 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 38458200 ps |
| CPU time | 26.2 seconds |
| Started | Oct 03 07:42:54 AM UTC 24 |
| Finished | Oct 03 07:43:22 AM UTC 24 |
| Peak memory | 275364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=1430416810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1430416810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.762291863 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1758699700 ps |
| CPU time | 152.28 seconds |
| Started | Oct 03 07:56:30 AM UTC 24 |
| Finished | Oct 03 07:59:05 AM UTC 24 |
| Peak memory | 291848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762291863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.762291863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.576687754 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3107471600 ps |
| CPU time | 199.16 seconds |
| Started | Oct 03 08:04:52 AM UTC 24 |
| Finished | Oct 03 08:08:15 AM UTC 24 |
| Peak memory | 298000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=576687754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.flash_ctrl_rw_derr.576687754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3914422711 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2182698900 ps |
| CPU time | 118.59 seconds |
| Started | Oct 03 08:11:14 AM UTC 24 |
| Finished | Oct 03 08:13:15 AM UTC 24 |
| Peak memory | 291856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3914422711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash _ctrl_ro_serr.3914422711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1090960426 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 221751800 ps |
| CPU time | 30.87 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:42 AM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090960426 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.1090960426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3803032990 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 51802700 ps |
| CPU time | 37.62 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:49 AM UTC 24 |
| Peak memory | 276332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803032990 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.3803032990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3794187592 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 198784700 ps |
| CPU time | 19.46 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:31 AM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794187592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.3794187592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.214722897 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 28248200 ps |
| CPU time | 16.61 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:28 AM UTC 24 |
| Peak memory | 274480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214722897 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.214722897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.513661652 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 29204400 ps |
| CPU time | 19.75 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:31 AM UTC 24 |
| Peak memory | 276532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513661652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.513661652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2271515953 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 22622100 ps |
| CPU time | 17.21 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:28 AM UTC 24 |
| Peak memory | 274412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271515953 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.2271515953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2773485973 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 248590800 ps |
| CPU time | 39.61 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:51 AM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2773485973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ same_csr_outstanding.2773485973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3421707932 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 13288400 ps |
| CPU time | 22.72 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:34 AM UTC 24 |
| Peak memory | 273880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342 1707932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sha dow_reg_errors.3421707932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.746065697 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 24961500 ps |
| CPU time | 21.19 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:32 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=746065697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_shadow_reg_errors_with_csr_rw.746065697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.4169734088 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 72990200 ps |
| CPU time | 22.52 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:34 AM UTC 24 |
| Peak memory | 276336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169734088 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.4169734088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3827173029 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 1351391400 ps |
| CPU time | 72.44 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:45:26 AM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827173029 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.3827173029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1928728843 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 78587500 ps |
| CPU time | 69.05 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:45:21 AM UTC 24 |
| Peak memory | 276588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928728843 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.1928728843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3548048011 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 51800500 ps |
| CPU time | 22.68 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:44:36 AM UTC 24 |
| Peak memory | 276388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3548048011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3548048011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.1397306468 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 15873100 ps |
| CPU time | 16.33 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:28 AM UTC 24 |
| Peak memory | 274292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397306468 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.1397306468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4055884636 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 43175400 ps |
| CPU time | 21.98 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:34 AM UTC 24 |
| Peak memory | 274412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055884636 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.4055884636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3764980231 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 324747500 ps |
| CPU time | 45.15 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:44:59 AM UTC 24 |
| Peak memory | 276376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3764980231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ same_csr_outstanding.3764980231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2435159909 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 20791500 ps |
| CPU time | 15.5 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:27 AM UTC 24 |
| Peak memory | 274276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243 5159909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sha dow_reg_errors.2435159909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.560539192 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 157846300 ps |
| CPU time | 18.63 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:30 AM UTC 24 |
| Peak memory | 274204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=560539192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_shadow_reg_errors_with_csr_rw.560539192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2420659361 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 107603600 ps |
| CPU time | 17.94 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 06:44:29 AM UTC 24 |
| Peak memory | 276336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420659361 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2420659361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.122770950 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1567260800 ps |
| CPU time | 1077.99 seconds |
| Started | Oct 03 06:44:10 AM UTC 24 |
| Finished | Oct 03 07:02:20 AM UTC 24 |
| Peak memory | 278576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122770950 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.122770950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.688565505 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 555175300 ps |
| CPU time | 21.59 seconds |
| Started | Oct 03 06:45:04 AM UTC 24 |
| Finished | Oct 03 06:45:27 AM UTC 24 |
| Peak memory | 286628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=688565505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.688565505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1642102740 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 239103200 ps |
| CPU time | 21.34 seconds |
| Started | Oct 03 06:45:04 AM UTC 24 |
| Finished | Oct 03 06:45:26 AM UTC 24 |
| Peak memory | 274412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642102740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.1642102740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2569195700 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 20171900 ps |
| CPU time | 22.35 seconds |
| Started | Oct 03 06:45:03 AM UTC 24 |
| Finished | Oct 03 06:45:26 AM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569195700 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.2569195700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.763534728 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 209973000 ps |
| CPU time | 29.53 seconds |
| Started | Oct 03 06:45:04 AM UTC 24 |
| Finished | Oct 03 06:45:35 AM UTC 24 |
| Peak memory | 276388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 763534728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ same_csr_outstanding.763534728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2577547062 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 18961500 ps |
| CPU time | 21.11 seconds |
| Started | Oct 03 06:45:02 AM UTC 24 |
| Finished | Oct 03 06:45:24 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257 7547062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sh adow_reg_errors.2577547062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1683859580 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 11572000 ps |
| CPU time | 22.33 seconds |
| Started | Oct 03 06:45:02 AM UTC 24 |
| Finished | Oct 03 06:45:25 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1683859580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.f lash_ctrl_shadow_reg_errors_with_csr_rw.1683859580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1553356300 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 70625400 ps |
| CPU time | 19.9 seconds |
| Started | Oct 03 06:45:02 AM UTC 24 |
| Finished | Oct 03 06:45:23 AM UTC 24 |
| Peak memory | 276596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553356300 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.1553356300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3667890924 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1760176400 ps |
| CPU time | 467.31 seconds |
| Started | Oct 03 06:45:02 AM UTC 24 |
| Finished | Oct 03 06:52:55 AM UTC 24 |
| Peak memory | 276396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667890924 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.3667890924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1724038004 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 83476100 ps |
| CPU time | 24.04 seconds |
| Started | Oct 03 06:45:10 AM UTC 24 |
| Finished | Oct 03 06:45:35 AM UTC 24 |
| Peak memory | 286624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1724038004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1724038004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.4198078671 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 227940200 ps |
| CPU time | 27.89 seconds |
| Started | Oct 03 06:45:08 AM UTC 24 |
| Finished | Oct 03 06:45:37 AM UTC 24 |
| Peak memory | 276324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198078671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.4198078671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1550721450 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 142092900 ps |
| CPU time | 20.35 seconds |
| Started | Oct 03 06:45:08 AM UTC 24 |
| Finished | Oct 03 06:45:29 AM UTC 24 |
| Peak memory | 274528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1550721450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl _same_csr_outstanding.1550721450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3929688799 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 20004600 ps |
| CPU time | 22.62 seconds |
| Started | Oct 03 06:45:05 AM UTC 24 |
| Finished | Oct 03 06:45:29 AM UTC 24 |
| Peak memory | 274280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392 9688799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh adow_reg_errors.3929688799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2336557389 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 24311200 ps |
| CPU time | 19.84 seconds |
| Started | Oct 03 06:45:06 AM UTC 24 |
| Finished | Oct 03 06:45:27 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2336557389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.f lash_ctrl_shadow_reg_errors_with_csr_rw.2336557389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1006019162 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 207321500 ps |
| CPU time | 24.92 seconds |
| Started | Oct 03 06:45:05 AM UTC 24 |
| Finished | Oct 03 06:45:31 AM UTC 24 |
| Peak memory | 276168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006019162 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.1006019162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4014616435 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 92571900 ps |
| CPU time | 21.47 seconds |
| Started | Oct 03 06:45:18 AM UTC 24 |
| Finished | Oct 03 06:45:41 AM UTC 24 |
| Peak memory | 286824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4014616435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.4014616435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1426288686 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 21303300 ps |
| CPU time | 22.64 seconds |
| Started | Oct 03 06:45:15 AM UTC 24 |
| Finished | Oct 03 06:45:39 AM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426288686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.1426288686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3330162473 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 16074200 ps |
| CPU time | 18.15 seconds |
| Started | Oct 03 06:45:15 AM UTC 24 |
| Finished | Oct 03 06:45:34 AM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330162473 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.3330162473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1146411096 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 329126600 ps |
| CPU time | 23.92 seconds |
| Started | Oct 03 06:45:16 AM UTC 24 |
| Finished | Oct 03 06:45:41 AM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1146411096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl _same_csr_outstanding.1146411096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3229948108 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 91664800 ps |
| CPU time | 21.75 seconds |
| Started | Oct 03 06:45:12 AM UTC 24 |
| Finished | Oct 03 06:45:35 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322 9948108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sh adow_reg_errors.3229948108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2301433028 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 14953600 ps |
| CPU time | 22.93 seconds |
| Started | Oct 03 06:45:13 AM UTC 24 |
| Finished | Oct 03 06:45:37 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2301433028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f lash_ctrl_shadow_reg_errors_with_csr_rw.2301433028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.518417560 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 35267600 ps |
| CPU time | 26.07 seconds |
| Started | Oct 03 06:45:11 AM UTC 24 |
| Finished | Oct 03 06:45:38 AM UTC 24 |
| Peak memory | 276336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518417560 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.518417560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.880758982 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 937996300 ps |
| CPU time | 1114.83 seconds |
| Started | Oct 03 06:45:11 AM UTC 24 |
| Finished | Oct 03 07:03:59 AM UTC 24 |
| Peak memory | 278516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880758982 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.880758982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1588615427 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 69381200 ps |
| CPU time | 24.73 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:51 AM UTC 24 |
| Peak memory | 276392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1588615427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1588615427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2084028337 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 70119200 ps |
| CPU time | 24.07 seconds |
| Started | Oct 03 06:45:24 AM UTC 24 |
| Finished | Oct 03 06:45:50 AM UTC 24 |
| Peak memory | 274252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084028337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.2084028337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.616921876 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 29989900 ps |
| CPU time | 17.67 seconds |
| Started | Oct 03 06:45:24 AM UTC 24 |
| Finished | Oct 03 06:45:43 AM UTC 24 |
| Peak memory | 274200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616921876 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.616921876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1563009858 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 864337500 ps |
| CPU time | 44.4 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:46:10 AM UTC 24 |
| Peak memory | 274332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1563009858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl _same_csr_outstanding.1563009858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2331632848 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 37524400 ps |
| CPU time | 17.39 seconds |
| Started | Oct 03 06:45:19 AM UTC 24 |
| Finished | Oct 03 06:45:38 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233 1632848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sh adow_reg_errors.2331632848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3930784015 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 31136200 ps |
| CPU time | 21.95 seconds |
| Started | Oct 03 06:45:24 AM UTC 24 |
| Finished | Oct 03 06:45:48 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3930784015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.f lash_ctrl_shadow_reg_errors_with_csr_rw.3930784015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1633743430 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 113805700 ps |
| CPU time | 23.6 seconds |
| Started | Oct 03 06:45:19 AM UTC 24 |
| Finished | Oct 03 06:45:44 AM UTC 24 |
| Peak memory | 276336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633743430 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.1633743430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.857045643 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1394216000 ps |
| CPU time | 546.97 seconds |
| Started | Oct 03 06:45:19 AM UTC 24 |
| Finished | Oct 03 06:54:33 AM UTC 24 |
| Peak memory | 276400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857045643 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.857045643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2463269681 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 419158200 ps |
| CPU time | 28.27 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:54 AM UTC 24 |
| Peak memory | 293032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2463269681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2463269681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1406497994 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 64567600 ps |
| CPU time | 26.12 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:52 AM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406497994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.1406497994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.1347286220 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 19837500 ps |
| CPU time | 16.36 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:42 AM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347286220 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.1347286220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2362792968 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 411849400 ps |
| CPU time | 23.01 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:49 AM UTC 24 |
| Peak memory | 276392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2362792968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl _same_csr_outstanding.2362792968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1126992482 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 22969300 ps |
| CPU time | 19.44 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:45 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112 6992482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh adow_reg_errors.1126992482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4118350020 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 79489200 ps |
| CPU time | 17.84 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:44 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4118350020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.f lash_ctrl_shadow_reg_errors_with_csr_rw.4118350020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2138410110 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 209640900 ps |
| CPU time | 22.1 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:48 AM UTC 24 |
| Peak memory | 276400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138410110 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.2138410110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4153311702 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 593581100 ps |
| CPU time | 28.05 seconds |
| Started | Oct 03 06:45:28 AM UTC 24 |
| Finished | Oct 03 06:45:57 AM UTC 24 |
| Peak memory | 286624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4153311702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.4153311702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4263313316 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 77187500 ps |
| CPU time | 22.89 seconds |
| Started | Oct 03 06:45:26 AM UTC 24 |
| Finished | Oct 03 06:45:51 AM UTC 24 |
| Peak memory | 274412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263313316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.4263313316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.545328526 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 251081300 ps |
| CPU time | 16.15 seconds |
| Started | Oct 03 06:45:26 AM UTC 24 |
| Finished | Oct 03 06:45:44 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545328526 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.545328526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.725681240 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 461332000 ps |
| CPU time | 27.09 seconds |
| Started | Oct 03 06:45:28 AM UTC 24 |
| Finished | Oct 03 06:45:56 AM UTC 24 |
| Peak memory | 274340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 725681240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ same_csr_outstanding.725681240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3784771971 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 32648500 ps |
| CPU time | 16.75 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:43 AM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378 4771971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sh adow_reg_errors.3784771971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3440639436 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 43515300 ps |
| CPU time | 18.04 seconds |
| Started | Oct 03 06:45:25 AM UTC 24 |
| Finished | Oct 03 06:45:44 AM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3440639436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.f lash_ctrl_shadow_reg_errors_with_csr_rw.3440639436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2881715722 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 176357100 ps |
| CPU time | 22.09 seconds |
| Started | Oct 03 06:45:35 AM UTC 24 |
| Finished | Oct 03 06:45:59 AM UTC 24 |
| Peak memory | 286756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2881715722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2881715722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2909225648 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 70887400 ps |
| CPU time | 23.07 seconds |
| Started | Oct 03 06:45:30 AM UTC 24 |
| Finished | Oct 03 06:45:54 AM UTC 24 |
| Peak memory | 274272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909225648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.2909225648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.458326130 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 47237700 ps |
| CPU time | 17.86 seconds |
| Started | Oct 03 06:45:30 AM UTC 24 |
| Finished | Oct 03 06:45:49 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458326130 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.458326130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2399121928 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 37145800 ps |
| CPU time | 24 seconds |
| Started | Oct 03 06:45:32 AM UTC 24 |
| Finished | Oct 03 06:45:57 AM UTC 24 |
| Peak memory | 274344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2399121928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl _same_csr_outstanding.2399121928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.344820960 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 11329400 ps |
| CPU time | 17.55 seconds |
| Started | Oct 03 06:45:28 AM UTC 24 |
| Finished | Oct 03 06:45:46 AM UTC 24 |
| Peak memory | 274344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344 820960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sha dow_reg_errors.344820960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.4150474225 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 11405200 ps |
| CPU time | 19.17 seconds |
| Started | Oct 03 06:45:29 AM UTC 24 |
| Finished | Oct 03 06:45:50 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4150474225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.f lash_ctrl_shadow_reg_errors_with_csr_rw.4150474225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.983398815 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 55995000 ps |
| CPU time | 21.95 seconds |
| Started | Oct 03 06:45:28 AM UTC 24 |
| Finished | Oct 03 06:45:51 AM UTC 24 |
| Peak memory | 276528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983398815 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.983398815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.657249235 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1324426900 ps |
| CPU time | 880.04 seconds |
| Started | Oct 03 06:45:28 AM UTC 24 |
| Finished | Oct 03 07:00:18 AM UTC 24 |
| Peak memory | 276404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657249235 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.657249235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3386429217 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 346113000 ps |
| CPU time | 21.82 seconds |
| Started | Oct 03 06:45:40 AM UTC 24 |
| Finished | Oct 03 06:46:03 AM UTC 24 |
| Peak memory | 286632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3386429217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.3386429217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2118412463 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 123041100 ps |
| CPU time | 22.72 seconds |
| Started | Oct 03 06:45:39 AM UTC 24 |
| Finished | Oct 03 06:46:02 AM UTC 24 |
| Peak memory | 274476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118412463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.2118412463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.2783453313 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 32935100 ps |
| CPU time | 17.47 seconds |
| Started | Oct 03 06:45:38 AM UTC 24 |
| Finished | Oct 03 06:45:57 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783453313 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.2783453313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.109315400 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 167874200 ps |
| CPU time | 23.07 seconds |
| Started | Oct 03 06:45:39 AM UTC 24 |
| Finished | Oct 03 06:46:03 AM UTC 24 |
| Peak memory | 276584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 109315400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ same_csr_outstanding.109315400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.592758634 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 41250100 ps |
| CPU time | 21.56 seconds |
| Started | Oct 03 06:45:36 AM UTC 24 |
| Finished | Oct 03 06:45:59 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592 758634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sha dow_reg_errors.592758634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3121788022 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 38527900 ps |
| CPU time | 21.87 seconds |
| Started | Oct 03 06:45:37 AM UTC 24 |
| Finished | Oct 03 06:46:01 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3121788022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.f lash_ctrl_shadow_reg_errors_with_csr_rw.3121788022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4221187106 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 64208400 ps |
| CPU time | 28.16 seconds |
| Started | Oct 03 06:45:35 AM UTC 24 |
| Finished | Oct 03 06:46:05 AM UTC 24 |
| Peak memory | 276448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221187106 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.4221187106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2328077105 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 323717300 ps |
| CPU time | 27.1 seconds |
| Started | Oct 03 06:45:45 AM UTC 24 |
| Finished | Oct 03 06:46:14 AM UTC 24 |
| Peak memory | 286632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2328077105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.2328077105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.543431629 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 33983000 ps |
| CPU time | 22.07 seconds |
| Started | Oct 03 06:45:44 AM UTC 24 |
| Finished | Oct 03 06:46:08 AM UTC 24 |
| Peak memory | 274340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543431629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.543431629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2287425852 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 29906200 ps |
| CPU time | 16.97 seconds |
| Started | Oct 03 06:45:44 AM UTC 24 |
| Finished | Oct 03 06:46:03 AM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287425852 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.2287425852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.17625016 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 228389400 ps |
| CPU time | 44.28 seconds |
| Started | Oct 03 06:45:45 AM UTC 24 |
| Finished | Oct 03 06:46:32 AM UTC 24 |
| Peak memory | 276588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 17625016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_s ame_csr_outstanding.17625016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.402998615 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 19416400 ps |
| CPU time | 24.6 seconds |
| Started | Oct 03 06:45:43 AM UTC 24 |
| Finished | Oct 03 06:46:09 AM UTC 24 |
| Peak memory | 274408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402 998615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sha dow_reg_errors.402998615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4231640000 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 36333200 ps |
| CPU time | 21.99 seconds |
| Started | Oct 03 06:45:44 AM UTC 24 |
| Finished | Oct 03 06:46:08 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4231640000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.f lash_ctrl_shadow_reg_errors_with_csr_rw.4231640000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3772704976 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 69282900 ps |
| CPU time | 31.13 seconds |
| Started | Oct 03 06:45:42 AM UTC 24 |
| Finished | Oct 03 06:46:14 AM UTC 24 |
| Peak memory | 276340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772704976 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.3772704976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.148681204 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 530027400 ps |
| CPU time | 546.68 seconds |
| Started | Oct 03 06:45:42 AM UTC 24 |
| Finished | Oct 03 06:54:55 AM UTC 24 |
| Peak memory | 276396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148681204 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.148681204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2040878249 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 363404700 ps |
| CPU time | 19.47 seconds |
| Started | Oct 03 06:45:50 AM UTC 24 |
| Finished | Oct 03 06:46:11 AM UTC 24 |
| Peak memory | 286020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2040878249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2040878249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1829107417 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 35500100 ps |
| CPU time | 28.71 seconds |
| Started | Oct 03 06:45:49 AM UTC 24 |
| Finished | Oct 03 06:46:19 AM UTC 24 |
| Peak memory | 274276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829107417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.1829107417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3737689081 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 73432600 ps |
| CPU time | 19.74 seconds |
| Started | Oct 03 06:45:49 AM UTC 24 |
| Finished | Oct 03 06:46:10 AM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737689081 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.3737689081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.416838888 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 311364700 ps |
| CPU time | 46.53 seconds |
| Started | Oct 03 06:45:50 AM UTC 24 |
| Finished | Oct 03 06:46:38 AM UTC 24 |
| Peak memory | 276388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 416838888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ same_csr_outstanding.416838888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2896862450 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 24657900 ps |
| CPU time | 20.22 seconds |
| Started | Oct 03 06:45:47 AM UTC 24 |
| Finished | Oct 03 06:46:09 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289 6862450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh adow_reg_errors.2896862450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1178865712 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 12917000 ps |
| CPU time | 19.41 seconds |
| Started | Oct 03 06:45:49 AM UTC 24 |
| Finished | Oct 03 06:46:09 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1178865712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.f lash_ctrl_shadow_reg_errors_with_csr_rw.1178865712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2213524880 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 40882800 ps |
| CPU time | 18.44 seconds |
| Started | Oct 03 06:45:45 AM UTC 24 |
| Finished | Oct 03 06:46:06 AM UTC 24 |
| Peak memory | 276336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213524880 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.2213524880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.827599446 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 941397000 ps |
| CPU time | 1109.65 seconds |
| Started | Oct 03 06:45:46 AM UTC 24 |
| Finished | Oct 03 07:04:29 AM UTC 24 |
| Peak memory | 278508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827599446 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.827599446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2864937041 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 931743700 ps |
| CPU time | 38.97 seconds |
| Started | Oct 03 06:44:13 AM UTC 24 |
| Finished | Oct 03 06:44:53 AM UTC 24 |
| Peak memory | 274468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864937041 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.2864937041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2344757517 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 635922400 ps |
| CPU time | 71.15 seconds |
| Started | Oct 03 06:44:13 AM UTC 24 |
| Finished | Oct 03 06:45:26 AM UTC 24 |
| Peak memory | 276460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344757517 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.2344757517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.523147389 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 25507200 ps |
| CPU time | 49.65 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:45:04 AM UTC 24 |
| Peak memory | 276320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523147389 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.523147389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1867338227 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 181355500 ps |
| CPU time | 22.32 seconds |
| Started | Oct 03 06:44:13 AM UTC 24 |
| Finished | Oct 03 06:44:36 AM UTC 24 |
| Peak memory | 286884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=1867338227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1867338227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.613831416 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 86674800 ps |
| CPU time | 24.75 seconds |
| Started | Oct 03 06:44:13 AM UTC 24 |
| Finished | Oct 03 06:44:39 AM UTC 24 |
| Peak memory | 274384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613831416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.613831416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2835589852 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 32429400 ps |
| CPU time | 22.43 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:44:36 AM UTC 24 |
| Peak memory | 276336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835589852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.2835589852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1130381883 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 27441200 ps |
| CPU time | 20.51 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:44:34 AM UTC 24 |
| Peak memory | 274412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130381883 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.1130381883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1159908090 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 750990500 ps |
| CPU time | 41.22 seconds |
| Started | Oct 03 06:44:13 AM UTC 24 |
| Finished | Oct 03 06:44:55 AM UTC 24 |
| Peak memory | 276288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1159908090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ same_csr_outstanding.1159908090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3301045432 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 13675000 ps |
| CPU time | 21.68 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:44:35 AM UTC 24 |
| Peak memory | 274404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330 1045432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha dow_reg_errors.3301045432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1923607173 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 19789500 ps |
| CPU time | 23.53 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:44:37 AM UTC 24 |
| Peak memory | 274200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1923607173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_shadow_reg_errors_with_csr_rw.1923607173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1625167898 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 38721200 ps |
| CPU time | 26.86 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:44:40 AM UTC 24 |
| Peak memory | 276336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625167898 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.1625167898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.835477258 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 487961300 ps |
| CPU time | 550.91 seconds |
| Started | Oct 03 06:44:12 AM UTC 24 |
| Finished | Oct 03 06:53:30 AM UTC 24 |
| Peak memory | 278512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835477258 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.835477258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.4272673770 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 28177600 ps |
| CPU time | 19.9 seconds |
| Started | Oct 03 06:45:50 AM UTC 24 |
| Finished | Oct 03 06:46:11 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272673770 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.4272673770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.800387468 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 17869900 ps |
| CPU time | 18.03 seconds |
| Started | Oct 03 06:45:50 AM UTC 24 |
| Finished | Oct 03 06:46:09 AM UTC 24 |
| Peak memory | 273544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800387468 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.800387468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.506627200 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 17752400 ps |
| CPU time | 16.9 seconds |
| Started | Oct 03 06:45:51 AM UTC 24 |
| Finished | Oct 03 06:46:09 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506627200 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.506627200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.1359538068 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 42110100 ps |
| CPU time | 16.06 seconds |
| Started | Oct 03 06:45:51 AM UTC 24 |
| Finished | Oct 03 06:46:08 AM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359538068 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.1359538068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.708263817 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 58828400 ps |
| CPU time | 22.64 seconds |
| Started | Oct 03 06:45:51 AM UTC 24 |
| Finished | Oct 03 06:46:15 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708263817 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.708263817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.3783374177 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 67750300 ps |
| CPU time | 17.82 seconds |
| Started | Oct 03 06:45:51 AM UTC 24 |
| Finished | Oct 03 06:46:10 AM UTC 24 |
| Peak memory | 274224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783374177 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.3783374177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2668552783 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 81740800 ps |
| CPU time | 21.43 seconds |
| Started | Oct 03 06:45:53 AM UTC 24 |
| Finished | Oct 03 06:46:16 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668552783 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.2668552783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3471649742 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 25698000 ps |
| CPU time | 17.9 seconds |
| Started | Oct 03 06:45:55 AM UTC 24 |
| Finished | Oct 03 06:46:15 AM UTC 24 |
| Peak memory | 274484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471649742 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.3471649742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.428337163 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 18464900 ps |
| CPU time | 21.53 seconds |
| Started | Oct 03 06:45:56 AM UTC 24 |
| Finished | Oct 03 06:46:18 AM UTC 24 |
| Peak memory | 274288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428337163 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.428337163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.4057290815 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 58518600 ps |
| CPU time | 18.2 seconds |
| Started | Oct 03 06:45:57 AM UTC 24 |
| Finished | Oct 03 06:46:16 AM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057290815 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.4057290815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1158366959 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3096081400 ps |
| CPU time | 42.74 seconds |
| Started | Oct 03 06:44:21 AM UTC 24 |
| Finished | Oct 03 06:45:05 AM UTC 24 |
| Peak memory | 274540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158366959 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.1158366959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3784734444 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 649246000 ps |
| CPU time | 62.19 seconds |
| Started | Oct 03 06:44:18 AM UTC 24 |
| Finished | Oct 03 06:45:22 AM UTC 24 |
| Peak memory | 276332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784734444 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.3784734444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3064437982 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 196186400 ps |
| CPU time | 61.62 seconds |
| Started | Oct 03 06:44:16 AM UTC 24 |
| Finished | Oct 03 06:45:19 AM UTC 24 |
| Peak memory | 276332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064437982 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.3064437982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1533880109 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 152189600 ps |
| CPU time | 22.76 seconds |
| Started | Oct 03 06:44:18 AM UTC 24 |
| Finished | Oct 03 06:44:42 AM UTC 24 |
| Peak memory | 274412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533880109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.1533880109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.3639770227 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 28044600 ps |
| CPU time | 17.03 seconds |
| Started | Oct 03 06:44:14 AM UTC 24 |
| Finished | Oct 03 06:44:32 AM UTC 24 |
| Peak memory | 274228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639770227 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3639770227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4131478567 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 17381900 ps |
| CPU time | 22.73 seconds |
| Started | Oct 03 06:44:16 AM UTC 24 |
| Finished | Oct 03 06:44:40 AM UTC 24 |
| Peak memory | 276336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131478567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.4131478567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2058568545 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 30119500 ps |
| CPU time | 18.59 seconds |
| Started | Oct 03 06:44:16 AM UTC 24 |
| Finished | Oct 03 06:44:35 AM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058568545 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.2058568545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1175215899 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 118001900 ps |
| CPU time | 19.48 seconds |
| Started | Oct 03 06:44:24 AM UTC 24 |
| Finished | Oct 03 06:44:45 AM UTC 24 |
| Peak memory | 276380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1175215899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ same_csr_outstanding.1175215899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.293129988 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 41928600 ps |
| CPU time | 22.69 seconds |
| Started | Oct 03 06:44:14 AM UTC 24 |
| Finished | Oct 03 06:44:38 AM UTC 24 |
| Peak memory | 274208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293 129988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shad ow_reg_errors.293129988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.630308509 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 13923400 ps |
| CPU time | 22.47 seconds |
| Started | Oct 03 06:44:14 AM UTC 24 |
| Finished | Oct 03 06:44:38 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=630308509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_shadow_reg_errors_with_csr_rw.630308509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4084802214 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 35991700 ps |
| CPU time | 22.22 seconds |
| Started | Oct 03 06:44:14 AM UTC 24 |
| Finished | Oct 03 06:44:38 AM UTC 24 |
| Peak memory | 276340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084802214 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.4084802214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3727004295 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 876355300 ps |
| CPU time | 549.3 seconds |
| Started | Oct 03 06:44:14 AM UTC 24 |
| Finished | Oct 03 06:53:30 AM UTC 24 |
| Peak memory | 278508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727004295 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.3727004295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1443718274 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 15347700 ps |
| CPU time | 17.74 seconds |
| Started | Oct 03 06:45:58 AM UTC 24 |
| Finished | Oct 03 06:46:17 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443718274 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.1443718274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.3165590861 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 17377600 ps |
| CPU time | 21.02 seconds |
| Started | Oct 03 06:45:58 AM UTC 24 |
| Finished | Oct 03 06:46:20 AM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165590861 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.3165590861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.1683258394 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 14722700 ps |
| CPU time | 18.44 seconds |
| Started | Oct 03 06:45:59 AM UTC 24 |
| Finished | Oct 03 06:46:19 AM UTC 24 |
| Peak memory | 274220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683258394 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.1683258394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.1418113935 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 16037300 ps |
| CPU time | 20.42 seconds |
| Started | Oct 03 06:46:00 AM UTC 24 |
| Finished | Oct 03 06:46:22 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418113935 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.1418113935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.3121956606 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 30890200 ps |
| CPU time | 19.71 seconds |
| Started | Oct 03 06:46:00 AM UTC 24 |
| Finished | Oct 03 06:46:21 AM UTC 24 |
| Peak memory | 274356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121956606 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.3121956606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.124004346 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 81066000 ps |
| CPU time | 19.74 seconds |
| Started | Oct 03 06:46:01 AM UTC 24 |
| Finished | Oct 03 06:46:22 AM UTC 24 |
| Peak memory | 274480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124004346 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.124004346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.707022035 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 31836100 ps |
| CPU time | 16.29 seconds |
| Started | Oct 03 06:46:03 AM UTC 24 |
| Finished | Oct 03 06:46:21 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707022035 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.707022035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.2256929182 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 16358600 ps |
| CPU time | 17.65 seconds |
| Started | Oct 03 06:46:03 AM UTC 24 |
| Finished | Oct 03 06:46:22 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256929182 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.2256929182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.652779588 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 22031300 ps |
| CPU time | 18.44 seconds |
| Started | Oct 03 06:46:04 AM UTC 24 |
| Finished | Oct 03 06:46:24 AM UTC 24 |
| Peak memory | 274352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652779588 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.652779588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.2110095252 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 16531600 ps |
| CPU time | 17.64 seconds |
| Started | Oct 03 06:46:04 AM UTC 24 |
| Finished | Oct 03 06:46:23 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110095252 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.2110095252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2459649579 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 4319927600 ps |
| CPU time | 47.62 seconds |
| Started | Oct 03 06:44:34 AM UTC 24 |
| Finished | Oct 03 06:45:23 AM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459649579 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.2459649579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2396701289 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5687565600 ps |
| CPU time | 73.41 seconds |
| Started | Oct 03 06:44:34 AM UTC 24 |
| Finished | Oct 03 06:45:49 AM UTC 24 |
| Peak memory | 276588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396701289 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.2396701289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3939036414 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 189574700 ps |
| CPU time | 46.99 seconds |
| Started | Oct 03 06:44:31 AM UTC 24 |
| Finished | Oct 03 06:45:20 AM UTC 24 |
| Peak memory | 276332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939036414 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.3939036414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3694693013 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 237322300 ps |
| CPU time | 28.59 seconds |
| Started | Oct 03 06:44:34 AM UTC 24 |
| Finished | Oct 03 06:45:04 AM UTC 24 |
| Peak memory | 286820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3694693013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3694693013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1638325886 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 125211300 ps |
| CPU time | 21.58 seconds |
| Started | Oct 03 06:44:32 AM UTC 24 |
| Finished | Oct 03 06:44:55 AM UTC 24 |
| Peak memory | 274476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638325886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.1638325886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.4082739732 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 231399600 ps |
| CPU time | 17.52 seconds |
| Started | Oct 03 06:44:30 AM UTC 24 |
| Finished | Oct 03 06:44:49 AM UTC 24 |
| Peak memory | 274420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082739732 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.4082739732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3483020554 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 15069300 ps |
| CPU time | 23.83 seconds |
| Started | Oct 03 06:44:31 AM UTC 24 |
| Finished | Oct 03 06:44:56 AM UTC 24 |
| Peak memory | 276336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483020554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.3483020554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3447524763 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 53809800 ps |
| CPU time | 18.31 seconds |
| Started | Oct 03 06:44:31 AM UTC 24 |
| Finished | Oct 03 06:44:51 AM UTC 24 |
| Peak memory | 274412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447524763 -assert nopostproc +UVM_TEST NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.3447524763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.322303276 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 36402700 ps |
| CPU time | 25.76 seconds |
| Started | Oct 03 06:44:34 AM UTC 24 |
| Finished | Oct 03 06:45:01 AM UTC 24 |
| Peak memory | 276576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 322303276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_s ame_csr_outstanding.322303276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3905783199 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 29637500 ps |
| CPU time | 19.95 seconds |
| Started | Oct 03 06:44:29 AM UTC 24 |
| Finished | Oct 03 06:44:50 AM UTC 24 |
| Peak memory | 274208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390 5783199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sha dow_reg_errors.3905783199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4134077396 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 13855000 ps |
| CPU time | 20.14 seconds |
| Started | Oct 03 06:44:29 AM UTC 24 |
| Finished | Oct 03 06:44:50 AM UTC 24 |
| Peak memory | 274204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4134077396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_shadow_reg_errors_with_csr_rw.4134077396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2551832380 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 373584700 ps |
| CPU time | 540.09 seconds |
| Started | Oct 03 06:44:29 AM UTC 24 |
| Finished | Oct 03 06:53:35 AM UTC 24 |
| Peak memory | 276504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551832380 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.2551832380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.1971011739 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 14382000 ps |
| CPU time | 16.35 seconds |
| Started | Oct 03 06:46:05 AM UTC 24 |
| Finished | Oct 03 06:46:23 AM UTC 24 |
| Peak memory | 274228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971011739 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.1971011739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2890714330 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 14414900 ps |
| CPU time | 21.88 seconds |
| Started | Oct 03 06:46:06 AM UTC 24 |
| Finished | Oct 03 06:46:29 AM UTC 24 |
| Peak memory | 274228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890714330 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.2890714330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.3654388526 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 17119100 ps |
| CPU time | 20.06 seconds |
| Started | Oct 03 06:46:09 AM UTC 24 |
| Finished | Oct 03 06:46:30 AM UTC 24 |
| Peak memory | 274292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654388526 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.3654388526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2943512260 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 51190300 ps |
| CPU time | 19.08 seconds |
| Started | Oct 03 06:46:09 AM UTC 24 |
| Finished | Oct 03 06:46:29 AM UTC 24 |
| Peak memory | 274216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943512260 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.2943512260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.1660824751 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 46595400 ps |
| CPU time | 17.26 seconds |
| Started | Oct 03 06:46:10 AM UTC 24 |
| Finished | Oct 03 06:46:28 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660824751 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.1660824751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.1812437800 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 56133600 ps |
| CPU time | 16.7 seconds |
| Started | Oct 03 06:46:10 AM UTC 24 |
| Finished | Oct 03 06:46:28 AM UTC 24 |
| Peak memory | 274228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812437800 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.1812437800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.2942074040 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 18636100 ps |
| CPU time | 18.02 seconds |
| Started | Oct 03 06:46:10 AM UTC 24 |
| Finished | Oct 03 06:46:29 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942074040 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.2942074040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.3632626317 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 41641500 ps |
| CPU time | 17.82 seconds |
| Started | Oct 03 06:46:10 AM UTC 24 |
| Finished | Oct 03 06:46:29 AM UTC 24 |
| Peak memory | 274416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632626317 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.3632626317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.2506418157 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 48044000 ps |
| CPU time | 16.87 seconds |
| Started | Oct 03 06:46:10 AM UTC 24 |
| Finished | Oct 03 06:46:28 AM UTC 24 |
| Peak memory | 274480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506418157 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.2506418157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.414339761 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 135857800 ps |
| CPU time | 17.4 seconds |
| Started | Oct 03 06:46:13 AM UTC 24 |
| Finished | Oct 03 06:46:32 AM UTC 24 |
| Peak memory | 274480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414339761 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.414339761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3531896504 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 54224300 ps |
| CPU time | 26.23 seconds |
| Started | Oct 03 06:44:37 AM UTC 24 |
| Finished | Oct 03 06:45:05 AM UTC 24 |
| Peak memory | 286628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=3531896504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3531896504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1138927910 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 129637200 ps |
| CPU time | 23.21 seconds |
| Started | Oct 03 06:44:36 AM UTC 24 |
| Finished | Oct 03 06:45:01 AM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138927910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.1138927910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.809615529 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 16094100 ps |
| CPU time | 15.77 seconds |
| Started | Oct 03 06:44:35 AM UTC 24 |
| Finished | Oct 03 06:44:52 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809615529 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.809615529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4251002813 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 295370600 ps |
| CPU time | 26.29 seconds |
| Started | Oct 03 06:44:36 AM UTC 24 |
| Finished | Oct 03 06:45:04 AM UTC 24 |
| Peak memory | 276384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4251002813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ same_csr_outstanding.4251002813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3090688180 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 41687000 ps |
| CPU time | 22.06 seconds |
| Started | Oct 03 06:44:35 AM UTC 24 |
| Finished | Oct 03 06:44:58 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309 0688180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha dow_reg_errors.3090688180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.528429276 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 16050200 ps |
| CPU time | 15.28 seconds |
| Started | Oct 03 06:44:35 AM UTC 24 |
| Finished | Oct 03 06:44:51 AM UTC 24 |
| Peak memory | 274204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=528429276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_shadow_reg_errors_with_csr_rw.528429276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2196813987 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 75111000 ps |
| CPU time | 19.82 seconds |
| Started | Oct 03 06:44:34 AM UTC 24 |
| Finished | Oct 03 06:44:55 AM UTC 24 |
| Peak memory | 276340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196813987 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2196813987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2591799615 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 676948900 ps |
| CPU time | 548.34 seconds |
| Started | Oct 03 06:44:35 AM UTC 24 |
| Finished | Oct 03 06:53:50 AM UTC 24 |
| Peak memory | 276500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591799615 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.2591799615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4116658865 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 68522000 ps |
| CPU time | 25.35 seconds |
| Started | Oct 03 06:44:40 AM UTC 24 |
| Finished | Oct 03 06:45:06 AM UTC 24 |
| Peak memory | 286756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4116658865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.4116658865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1237267994 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 20492900 ps |
| CPU time | 20.84 seconds |
| Started | Oct 03 06:44:39 AM UTC 24 |
| Finished | Oct 03 06:45:01 AM UTC 24 |
| Peak memory | 274476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237267994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.1237267994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.921900494 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 24251400 ps |
| CPU time | 21.52 seconds |
| Started | Oct 03 06:44:39 AM UTC 24 |
| Finished | Oct 03 06:45:01 AM UTC 24 |
| Peak memory | 274288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921900494 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.921900494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2010659512 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 104174000 ps |
| CPU time | 23.12 seconds |
| Started | Oct 03 06:44:39 AM UTC 24 |
| Finished | Oct 03 06:45:03 AM UTC 24 |
| Peak memory | 276376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2010659512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ same_csr_outstanding.2010659512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2501988754 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 36397000 ps |
| CPU time | 27.46 seconds |
| Started | Oct 03 06:44:37 AM UTC 24 |
| Finished | Oct 03 06:45:06 AM UTC 24 |
| Peak memory | 274212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250 1988754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sha dow_reg_errors.2501988754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3321269073 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 13765300 ps |
| CPU time | 18.27 seconds |
| Started | Oct 03 06:44:39 AM UTC 24 |
| Finished | Oct 03 06:44:58 AM UTC 24 |
| Peak memory | 274200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3321269073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3321269073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1268312822 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 125322400 ps |
| CPU time | 21.9 seconds |
| Started | Oct 03 06:44:37 AM UTC 24 |
| Finished | Oct 03 06:45:00 AM UTC 24 |
| Peak memory | 276404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268312822 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1268312822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2686550855 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3819583100 ps |
| CPU time | 1097.99 seconds |
| Started | Oct 03 06:44:37 AM UTC 24 |
| Finished | Oct 03 07:03:08 AM UTC 24 |
| Peak memory | 278516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686550855 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.2686550855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4024090131 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 98291100 ps |
| CPU time | 26.29 seconds |
| Started | Oct 03 06:44:50 AM UTC 24 |
| Finished | Oct 03 06:45:18 AM UTC 24 |
| Peak memory | 286624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=4024090131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.4024090131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2603832283 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 32962900 ps |
| CPU time | 23.3 seconds |
| Started | Oct 03 06:44:49 AM UTC 24 |
| Finished | Oct 03 06:45:14 AM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603832283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.2603832283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.616994054 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 118065800 ps |
| CPU time | 17.74 seconds |
| Started | Oct 03 06:44:46 AM UTC 24 |
| Finished | Oct 03 06:45:05 AM UTC 24 |
| Peak memory | 274480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616994054 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.616994054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2869722559 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 75743200 ps |
| CPU time | 18.17 seconds |
| Started | Oct 03 06:44:49 AM UTC 24 |
| Finished | Oct 03 06:45:09 AM UTC 24 |
| Peak memory | 276576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2869722559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ same_csr_outstanding.2869722559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.601027350 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 15130300 ps |
| CPU time | 20.26 seconds |
| Started | Oct 03 06:44:43 AM UTC 24 |
| Finished | Oct 03 06:45:05 AM UTC 24 |
| Peak memory | 274480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601 027350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shad ow_reg_errors.601027350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.787059147 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 42238500 ps |
| CPU time | 27.42 seconds |
| Started | Oct 03 06:44:43 AM UTC 24 |
| Finished | Oct 03 06:45:12 AM UTC 24 |
| Peak memory | 274204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=787059147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_shadow_reg_errors_with_csr_rw.787059147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2711495585 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 29232900 ps |
| CPU time | 17.39 seconds |
| Started | Oct 03 06:44:53 AM UTC 24 |
| Finished | Oct 03 06:45:11 AM UTC 24 |
| Peak memory | 286820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=2711495585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2711495585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.994599671 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 27675800 ps |
| CPU time | 20.92 seconds |
| Started | Oct 03 06:44:53 AM UTC 24 |
| Finished | Oct 03 06:45:15 AM UTC 24 |
| Peak memory | 274276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994599671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.994599671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.3109022305 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 64535700 ps |
| CPU time | 16.52 seconds |
| Started | Oct 03 06:44:52 AM UTC 24 |
| Finished | Oct 03 06:45:09 AM UTC 24 |
| Peak memory | 274228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109022305 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3109022305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2413972939 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 66797900 ps |
| CPU time | 29.65 seconds |
| Started | Oct 03 06:44:53 AM UTC 24 |
| Finished | Oct 03 06:45:24 AM UTC 24 |
| Peak memory | 274336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2413972939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ same_csr_outstanding.2413972939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1361611084 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 24070300 ps |
| CPU time | 30.82 seconds |
| Started | Oct 03 06:44:52 AM UTC 24 |
| Finished | Oct 03 06:45:24 AM UTC 24 |
| Peak memory | 274204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136 1611084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sha dow_reg_errors.1361611084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3529448800 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 123352600 ps |
| CPU time | 21.4 seconds |
| Started | Oct 03 06:44:52 AM UTC 24 |
| Finished | Oct 03 06:45:14 AM UTC 24 |
| Peak memory | 274208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3529448800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3529448800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1495729992 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 289311800 ps |
| CPU time | 28.12 seconds |
| Started | Oct 03 06:44:50 AM UTC 24 |
| Finished | Oct 03 06:45:20 AM UTC 24 |
| Peak memory | 276332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495729992 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1495729992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.647170192 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 105119900 ps |
| CPU time | 21.22 seconds |
| Started | Oct 03 06:45:00 AM UTC 24 |
| Finished | Oct 03 06:45:22 AM UTC 24 |
| Peak memory | 286624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 + csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw /dv/tools/sim.tcl +ntb_random_seed=647170192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.647170192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4137966731 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 74716100 ps |
| CPU time | 21.85 seconds |
| Started | Oct 03 06:44:58 AM UTC 24 |
| Finished | Oct 03 06:45:21 AM UTC 24 |
| Peak memory | 274284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137966731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.4137966731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3832113510 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 39163800 ps |
| CPU time | 20.13 seconds |
| Started | Oct 03 06:44:59 AM UTC 24 |
| Finished | Oct 03 06:45:21 AM UTC 24 |
| Peak memory | 276392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3832113510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ same_csr_outstanding.3832113510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2768409889 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 15709200 ps |
| CPU time | 21.49 seconds |
| Started | Oct 03 06:44:56 AM UTC 24 |
| Finished | Oct 03 06:45:19 AM UTC 24 |
| Peak memory | 274204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276 8409889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha dow_reg_errors.2768409889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3570183562 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 21871800 ps |
| CPU time | 23.6 seconds |
| Started | Oct 03 06:44:56 AM UTC 24 |
| Finished | Oct 03 06:45:21 AM UTC 24 |
| Peak memory | 274400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3570183562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fl ash_ctrl_shadow_reg_errors_with_csr_rw.3570183562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.276488420 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 44300900 ps |
| CPU time | 28.05 seconds |
| Started | Oct 03 06:44:54 AM UTC 24 |
| Finished | Oct 03 06:45:23 AM UTC 24 |
| Peak memory | 276588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276488420 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.276488420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1285097110 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 411569200 ps |
| CPU time | 548.01 seconds |
| Started | Oct 03 06:44:56 AM UTC 24 |
| Finished | Oct 03 06:54:11 AM UTC 24 |
| Peak memory | 276404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285097110 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.1285097110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.4043881851 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4375125600 ps |
| CPU time | 3376.04 seconds |
| Started | Oct 03 07:07:56 AM UTC 24 |
| Finished | Oct 03 08:04:56 AM UTC 24 |
| Peak memory | 277920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043881851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.4043881851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4267781958 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 575344182100 ps |
| CPU time | 2987.49 seconds |
| Started | Oct 03 07:06:06 AM UTC 24 |
| Finished | Oct 03 07:56:34 AM UTC 24 |
| Peak memory | 277956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267781958 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.4267781958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.3878430332 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 27754500 ps |
| CPU time | 42.95 seconds |
| Started | Oct 03 07:23:17 AM UTC 24 |
| Finished | Oct 03 07:24:01 AM UTC 24 |
| Peak memory | 285432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387843033 2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho st_addr_infection.3878430332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.2721266304 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 65254100 ps |
| CPU time | 173.63 seconds |
| Started | Oct 03 07:04:59 AM UTC 24 |
| Finished | Oct 03 07:07:56 AM UTC 24 |
| Peak memory | 273100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721266304 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2721266304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.963337031 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 543603759900 ps |
| CPU time | 2099.92 seconds |
| Started | Oct 03 07:05:04 AM UTC 24 |
| Finished | Oct 03 07:40:35 AM UTC 24 |
| Peak memory | 278152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963337031 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.963337031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.1805505701 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 58709705100 ps |
| CPU time | 648.12 seconds |
| Started | Oct 03 07:15:15 AM UTC 24 |
| Finished | Oct 03 07:26:13 AM UTC 24 |
| Peak memory | 345340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1805505701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integr ity.1805505701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.3065359183 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1634962300 ps |
| CPU time | 557.41 seconds |
| Started | Oct 03 07:05:00 AM UTC 24 |
| Finished | Oct 03 07:14:26 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065359183 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3065359183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1400417032 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3603620000 ps |
| CPU time | 151.68 seconds |
| Started | Oct 03 07:18:08 AM UTC 24 |
| Finished | Oct 03 07:20:43 AM UTC 24 |
| Peak memory | 273228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400417032 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.1400417032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.533546685 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 87750200 ps |
| CPU time | 434.99 seconds |
| Started | Oct 03 07:04:59 AM UTC 24 |
| Finished | Oct 03 07:12:21 AM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533546685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.533546685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.1564749490 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5174285900 ps |
| CPU time | 179.73 seconds |
| Started | Oct 03 07:04:59 AM UTC 24 |
| Finished | Oct 03 07:08:02 AM UTC 24 |
| Peak memory | 273092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564749490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1564749490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.1684492617 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 162022700 ps |
| CPU time | 47.73 seconds |
| Started | Oct 03 07:20:57 AM UTC 24 |
| Finished | Oct 03 07:21:46 AM UTC 24 |
| Peak memory | 287548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168449261 7 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.1684492617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.3764321285 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 99626900 ps |
| CPU time | 66.64 seconds |
| Started | Oct 03 07:23:09 AM UTC 24 |
| Finished | Oct 03 07:24:17 AM UTC 24 |
| Peak memory | 291808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764321285 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.3764321285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.2215506411 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 29607300 ps |
| CPU time | 21.53 seconds |
| Started | Oct 03 07:09:55 AM UTC 24 |
| Finished | Oct 03 07:10:18 AM UTC 24 |
| Peak memory | 275396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215506411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.2215506411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.3246602832 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 32515900 ps |
| CPU time | 33.42 seconds |
| Started | Oct 03 07:13:46 AM UTC 24 |
| Finished | Oct 03 07:14:20 AM UTC 24 |
| Peak memory | 275508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3246602832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_read_word_sweep_derr.3246602832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.966542496 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 159125000 ps |
| CPU time | 32.59 seconds |
| Started | Oct 03 07:11:40 AM UTC 24 |
| Finished | Oct 03 07:12:14 AM UTC 24 |
| Peak memory | 275528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966542496 -assert nopostproc +U VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.966542496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.1251542247 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1460737300 ps |
| CPU time | 123.07 seconds |
| Started | Oct 03 07:10:01 AM UTC 24 |
| Finished | Oct 03 07:12:07 AM UTC 24 |
| Peak memory | 302204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1251542247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.1251542247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.3152686624 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2517024400 ps |
| CPU time | 144.24 seconds |
| Started | Oct 03 07:12:07 AM UTC 24 |
| Finished | Oct 03 07:14:34 AM UTC 24 |
| Peak memory | 291852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3152686624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash _ctrl_ro_serr.3152686624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.4157374027 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3414177100 ps |
| CPU time | 461.19 seconds |
| Started | Oct 03 07:10:19 AM UTC 24 |
| Finished | Oct 03 07:18:07 AM UTC 24 |
| Peak memory | 320520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157374027 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.4157374027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.4268532121 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2399883300 ps |
| CPU time | 82.02 seconds |
| Started | Oct 03 07:20:15 AM UTC 24 |
| Finished | Oct 03 07:21:40 AM UTC 24 |
| Peak memory | 275160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268532121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.4268532121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.3171643358 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 890669100 ps |
| CPU time | 103.88 seconds |
| Started | Oct 03 07:13:27 AM UTC 24 |
| Finished | Oct 03 07:15:14 AM UTC 24 |
| Peak memory | 275400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317 1643358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser r_address.3171643358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.3270505286 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 565739900 ps |
| CPU time | 80.84 seconds |
| Started | Oct 03 07:12:21 AM UTC 24 |
| Finished | Oct 03 07:13:44 AM UTC 24 |
| Peak memory | 285684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 70505286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_se rr_counter.3270505286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.2704958611 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 62963700 ps |
| CPU time | 259.83 seconds |
| Started | Oct 03 07:04:57 AM UTC 24 |
| Finished | Oct 03 07:09:21 AM UTC 24 |
| Peak memory | 289412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704958611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2704958611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.3877036004 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 24858300 ps |
| CPU time | 41.99 seconds |
| Started | Oct 03 07:04:58 AM UTC 24 |
| Finished | Oct 03 07:05:41 AM UTC 24 |
| Peak memory | 271180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877036004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.3877036004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.1633656564 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 309982900 ps |
| CPU time | 1907.75 seconds |
| Started | Oct 03 07:20:33 AM UTC 24 |
| Finished | Oct 03 07:52:46 AM UTC 24 |
| Peak memory | 295632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633656564 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.1633656564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.2071150480 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 52188200 ps |
| CPU time | 41.84 seconds |
| Started | Oct 03 07:04:59 AM UTC 24 |
| Finished | Oct 03 07:05:42 AM UTC 24 |
| Peak memory | 272904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071150480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.2071150480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.2430873485 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 9093085200 ps |
| CPU time | 134.63 seconds |
| Started | Oct 03 07:09:21 AM UTC 24 |
| Finished | Oct 03 07:11:39 AM UTC 24 |
| Peak memory | 275252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2430873485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.2430873485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.1107654185 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 164137600 ps |
| CPU time | 22.6 seconds |
| Started | Oct 03 07:21:10 AM UTC 24 |
| Finished | Oct 03 07:21:34 AM UTC 24 |
| Peak memory | 271264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107654185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_wr_intg.1107654185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2740653881 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 41622700 ps |
| CPU time | 23.55 seconds |
| Started | Oct 03 07:09:35 AM UTC 24 |
| Finished | Oct 03 07:09:59 AM UTC 24 |
| Peak memory | 275392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740653881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.2740653881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.2978022573 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 18112600 ps |
| CPU time | 23.35 seconds |
| Started | Oct 03 07:39:48 AM UTC 24 |
| Finished | Oct 03 07:40:13 AM UTC 24 |
| Peak memory | 275360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all =1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2978022573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2978022573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.4032540416 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 36297100 ps |
| CPU time | 21.28 seconds |
| Started | Oct 03 07:40:19 AM UTC 24 |
| Finished | Oct 03 07:40:41 AM UTC 24 |
| Peak memory | 269252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032540416 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.4032540416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.38844776 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 51803700 ps |
| CPU time | 20.56 seconds |
| Started | Oct 03 07:40:08 AM UTC 24 |
| Finished | Oct 03 07:40:30 AM UTC 24 |
| Peak memory | 274964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38844776 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.38844776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2569092386 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 15693100 ps |
| CPU time | 24.79 seconds |
| Started | Oct 03 07:39:45 AM UTC 24 |
| Finished | Oct 03 07:40:12 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569092386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.2569092386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3694350886 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 773572500 ps |
| CPU time | 424.06 seconds |
| Started | Oct 03 07:29:27 AM UTC 24 |
| Finished | Oct 03 07:36:38 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694350886 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3694350886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.117166395 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 8878996900 ps |
| CPU time | 3354.94 seconds |
| Started | Oct 03 07:38:46 AM UTC 24 |
| Finished | Oct 03 08:35:20 AM UTC 24 |
| Peak memory | 275884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117166395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.117166395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.3679715406 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1867550800 ps |
| CPU time | 2423.22 seconds |
| Started | Oct 03 07:38:45 AM UTC 24 |
| Finished | Oct 03 08:19:36 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 79715406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl _error_prog_type.3679715406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.230365725 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 689131400 ps |
| CPU time | 1370.21 seconds |
| Started | Oct 03 07:38:45 AM UTC 24 |
| Finished | Oct 03 08:01:52 AM UTC 24 |
| Peak memory | 285392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230365725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.230365725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.4287852936 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 227913800 ps |
| CPU time | 27.91 seconds |
| Started | Oct 03 07:38:41 AM UTC 24 |
| Finished | Oct 03 07:39:10 AM UTC 24 |
| Peak memory | 273092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 87852936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetc h_code.4287852936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.784913135 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1220412400 ps |
| CPU time | 45.8 seconds |
| Started | Oct 03 07:39:54 AM UTC 24 |
| Finished | Oct 03 07:40:41 AM UTC 24 |
| Peak memory | 273196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7849131 35 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fs _sup.784913135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.1443073964 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 50872470700 ps |
| CPU time | 4056.12 seconds |
| Started | Oct 03 07:38:44 AM UTC 24 |
| Finished | Oct 03 08:47:07 AM UTC 24 |
| Peak memory | 277824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443073964 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.1443073964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.1635992464 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 28062900 ps |
| CPU time | 45.74 seconds |
| Started | Oct 03 07:40:17 AM UTC 24 |
| Finished | Oct 03 07:41:04 AM UTC 24 |
| Peak memory | 285400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163599246 4 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ho st_addr_infection.1635992464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3705813224 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 50340200 ps |
| CPU time | 22.75 seconds |
| Started | Oct 03 07:40:13 AM UTC 24 |
| Finished | Oct 03 07:40:38 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3705813224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3705813224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2992939401 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 334112650900 ps |
| CPU time | 1929.92 seconds |
| Started | Oct 03 07:30:04 AM UTC 24 |
| Finished | Oct 03 08:02:38 AM UTC 24 |
| Peak memory | 275104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992939401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.2992939401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.687919214 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2011683100 ps |
| CPU time | 88.28 seconds |
| Started | Oct 03 07:27:56 AM UTC 24 |
| Finished | Oct 03 07:29:26 AM UTC 24 |
| Peak memory | 273228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687919214 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.687919214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.1508691879 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 17024440500 ps |
| CPU time | 680.1 seconds |
| Started | Oct 03 07:39:13 AM UTC 24 |
| Finished | Oct 03 07:50:43 AM UTC 24 |
| Peak memory | 345316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1508691879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integr ity.1508691879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.2278812609 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 6759524500 ps |
| CPU time | 252.55 seconds |
| Started | Oct 03 07:39:13 AM UTC 24 |
| Finished | Oct 03 07:43:30 AM UTC 24 |
| Peak memory | 301932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278812609 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.2278812609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3872416113 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6094608300 ps |
| CPU time | 176.04 seconds |
| Started | Oct 03 07:39:20 AM UTC 24 |
| Finished | Oct 03 07:42:19 AM UTC 24 |
| Peak memory | 303848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3872416113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_intr_rd_slow_flash.3872416113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.1526915490 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10841481500 ps |
| CPU time | 94.19 seconds |
| Started | Oct 03 07:39:15 AM UTC 24 |
| Finished | Oct 03 07:40:53 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526915490 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.1526915490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3587129414 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 80720790700 ps |
| CPU time | 314.68 seconds |
| Started | Oct 03 07:39:22 AM UTC 24 |
| Finished | Oct 03 07:44:42 AM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587129414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3587129414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.4271985281 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 3417184700 ps |
| CPU time | 80.87 seconds |
| Started | Oct 03 07:38:50 AM UTC 24 |
| Finished | Oct 03 07:40:13 AM UTC 24 |
| Peak memory | 270912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271985281 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.4271985281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.2767695049 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 99480000 ps |
| CPU time | 23.08 seconds |
| Started | Oct 03 07:40:13 AM UTC 24 |
| Finished | Oct 03 07:40:38 AM UTC 24 |
| Peak memory | 271108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2767695049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_lcmgr_intg.2767695049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.708297360 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3294362900 ps |
| CPU time | 104.11 seconds |
| Started | Oct 03 07:38:51 AM UTC 24 |
| Finished | Oct 03 07:40:37 AM UTC 24 |
| Peak memory | 271136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708297360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.708297360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1826058527 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 51742100 ps |
| CPU time | 204.05 seconds |
| Started | Oct 03 07:34:47 AM UTC 24 |
| Finished | Oct 03 07:38:15 AM UTC 24 |
| Peak memory | 271132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826058527 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.1826058527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.1653945234 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 4506501000 ps |
| CPU time | 245.58 seconds |
| Started | Oct 03 07:39:10 AM UTC 24 |
| Finished | Oct 03 07:43:21 AM UTC 24 |
| Peak memory | 291828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1653945234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1653945234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2199439927 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2851767900 ps |
| CPU time | 830.27 seconds |
| Started | Oct 03 07:27:40 AM UTC 24 |
| Finished | Oct 03 07:41:42 AM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199439927 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2199439927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.298056034 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 835255500 ps |
| CPU time | 37.53 seconds |
| Started | Oct 03 07:39:58 AM UTC 24 |
| Finished | Oct 03 07:40:37 AM UTC 24 |
| Peak memory | 275720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=298056034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.298056034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.2665047045 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 20236400 ps |
| CPU time | 20.53 seconds |
| Started | Oct 03 07:39:23 AM UTC 24 |
| Finished | Oct 03 07:39:45 AM UTC 24 |
| Peak memory | 269248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665047045 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.2665047045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.752712819 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 87272800 ps |
| CPU time | 571.43 seconds |
| Started | Oct 03 07:25:05 AM UTC 24 |
| Finished | Oct 03 07:34:45 AM UTC 24 |
| Peak memory | 287372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752712819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.752712819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.1108612134 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1376609300 ps |
| CPU time | 205.38 seconds |
| Started | Oct 03 07:26:58 AM UTC 24 |
| Finished | Oct 03 07:30:27 AM UTC 24 |
| Peak memory | 273288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108612134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.1108612134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.354102470 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 728997800 ps |
| CPU time | 52.25 seconds |
| Started | Oct 03 07:39:31 AM UTC 24 |
| Finished | Oct 03 07:40:25 AM UTC 24 |
| Peak memory | 287740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354102470 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.354102470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.2367060930 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 124718400 ps |
| CPU time | 32.8 seconds |
| Started | Oct 03 07:39:05 AM UTC 24 |
| Finished | Oct 03 07:39:40 AM UTC 24 |
| Peak memory | 275320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2367060930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_read_word_sweep_derr.2367060930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3356737718 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 39281500 ps |
| CPU time | 33.55 seconds |
| Started | Oct 03 07:38:54 AM UTC 24 |
| Finished | Oct 03 07:39:30 AM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356737718 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.3356737718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.1757277114 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 219247735400 ps |
| CPU time | 1078.11 seconds |
| Started | Oct 03 07:40:12 AM UTC 24 |
| Finished | Oct 03 07:58:25 AM UTC 24 |
| Peak memory | 273100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1757277114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. flash_ctrl_rma_err.1757277114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.935287200 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 963392100 ps |
| CPU time | 124.45 seconds |
| Started | Oct 03 07:38:52 AM UTC 24 |
| Finished | Oct 03 07:40:59 AM UTC 24 |
| Peak memory | 302080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=935287200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.935287200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.2850575365 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1269571600 ps |
| CPU time | 181.68 seconds |
| Started | Oct 03 07:39:07 AM UTC 24 |
| Finished | Oct 03 07:42:13 AM UTC 24 |
| Peak memory | 292040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850575365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2850575365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.1909326468 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 594855300 ps |
| CPU time | 141.74 seconds |
| Started | Oct 03 07:38:57 AM UTC 24 |
| Finished | Oct 03 07:41:22 AM UTC 24 |
| Peak memory | 306168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1909326468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_ro_serr.1909326468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.4073608959 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 12001333500 ps |
| CPU time | 616.93 seconds |
| Started | Oct 03 07:38:54 AM UTC 24 |
| Finished | Oct 03 07:49:19 AM UTC 24 |
| Peak memory | 322568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073608959 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.4073608959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.365275221 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4265921800 ps |
| CPU time | 207.59 seconds |
| Started | Oct 03 07:39:07 AM UTC 24 |
| Finished | Oct 03 07:42:40 AM UTC 24 |
| Peak memory | 295948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=365275221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.flash_ctrl_rw_derr.365275221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2722865060 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 32166900 ps |
| CPU time | 47.25 seconds |
| Started | Oct 03 07:39:26 AM UTC 24 |
| Finished | Oct 03 07:40:15 AM UTC 24 |
| Peak memory | 287876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722865060 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.2722865060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.1790623598 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4203659500 ps |
| CPU time | 266.92 seconds |
| Started | Oct 03 07:38:59 AM UTC 24 |
| Finished | Oct 03 07:43:31 AM UTC 24 |
| Peak memory | 306364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1790623598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.1790623598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1736535771 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1783941400 ps |
| CPU time | 86.32 seconds |
| Started | Oct 03 07:39:39 AM UTC 24 |
| Finished | Oct 03 07:41:08 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736535771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1736535771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.372830027 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3466470400 ps |
| CPU time | 108.92 seconds |
| Started | Oct 03 07:39:02 AM UTC 24 |
| Finished | Oct 03 07:40:54 AM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372 830027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_serr _address.372830027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3171811199 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2294219100 ps |
| CPU time | 64.17 seconds |
| Started | Oct 03 07:39:01 AM UTC 24 |
| Finished | Oct 03 07:40:07 AM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31 71811199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se rr_counter.3171811199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.483248151 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 90702300 ps |
| CPU time | 339.81 seconds |
| Started | Oct 03 07:24:18 AM UTC 24 |
| Finished | Oct 03 07:30:04 AM UTC 24 |
| Peak memory | 291464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483248151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.483248151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.1619797413 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 39216400 ps |
| CPU time | 38.09 seconds |
| Started | Oct 03 07:24:25 AM UTC 24 |
| Finished | Oct 03 07:25:05 AM UTC 24 |
| Peak memory | 270920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619797413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.1619797413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.2423332870 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 493664700 ps |
| CPU time | 1697.97 seconds |
| Started | Oct 03 07:39:41 AM UTC 24 |
| Finished | Oct 03 08:08:19 AM UTC 24 |
| Peak memory | 295628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423332870 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.2423332870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3551353858 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 28081600 ps |
| CPU time | 40.56 seconds |
| Started | Oct 03 07:26:14 AM UTC 24 |
| Finished | Oct 03 07:26:56 AM UTC 24 |
| Peak memory | 272908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551353858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3551353858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.41020645 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2373990400 ps |
| CPU time | 182.31 seconds |
| Started | Oct 03 07:38:52 AM UTC 24 |
| Finished | Oct 03 07:41:58 AM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =41020645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.41020645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2468916285 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 581480800 ps |
| CPU time | 26.37 seconds |
| Started | Oct 03 07:39:48 AM UTC 24 |
| Finished | Oct 03 07:40:16 AM UTC 24 |
| Peak memory | 271440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468916285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_wr_intg.2468916285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.152841963 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 69836900 ps |
| CPU time | 26.92 seconds |
| Started | Oct 03 08:16:20 AM UTC 24 |
| Finished | Oct 03 08:16:49 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152841963 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.152841963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.3219871624 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 23029500 ps |
| CPU time | 31.57 seconds |
| Started | Oct 03 08:16:05 AM UTC 24 |
| Finished | Oct 03 08:16:38 AM UTC 24 |
| Peak memory | 284616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219871624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.3219871624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.1821691143 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 26086900 ps |
| CPU time | 44.18 seconds |
| Started | Oct 03 08:15:56 AM UTC 24 |
| Finished | Oct 03 08:16:42 AM UTC 24 |
| Peak memory | 275412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1821691143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ ctrl_disable.1821691143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.217038776 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 10071197000 ps |
| CPU time | 54.45 seconds |
| Started | Oct 03 08:16:14 AM UTC 24 |
| Finished | Oct 03 08:17:10 AM UTC 24 |
| Peak memory | 279388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=217038776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.217038776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.3516592184 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 46658400 ps |
| CPU time | 23.63 seconds |
| Started | Oct 03 08:16:10 AM UTC 24 |
| Finished | Oct 03 08:16:35 AM UTC 24 |
| Peak memory | 271436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3516592184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.3516592184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.1454503089 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 90144400600 ps |
| CPU time | 1007.22 seconds |
| Started | Oct 03 08:14:14 AM UTC 24 |
| Finished | Oct 03 08:31:14 AM UTC 24 |
| Peak memory | 275044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454503089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_res et.1454503089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.1321818435 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 12325091300 ps |
| CPU time | 124.36 seconds |
| Started | Oct 03 08:14:13 AM UTC 24 |
| Finished | Oct 03 08:16:20 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321818435 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.1321818435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.3190410796 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3946317200 ps |
| CPU time | 118.34 seconds |
| Started | Oct 03 08:14:49 AM UTC 24 |
| Finished | Oct 03 08:16:49 AM UTC 24 |
| Peak memory | 306288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190410796 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.3190410796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1102853373 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 24907740500 ps |
| CPU time | 246.18 seconds |
| Started | Oct 03 08:14:55 AM UTC 24 |
| Finished | Oct 03 08:19:05 AM UTC 24 |
| Peak memory | 304040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1102853373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_intr_rd_slow_flash.1102853373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.2254755843 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 898283500 ps |
| CPU time | 97.79 seconds |
| Started | Oct 03 08:14:22 AM UTC 24 |
| Finished | Oct 03 08:16:02 AM UTC 24 |
| Peak memory | 275012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254755843 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.2254755843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3578064823 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 26228200 ps |
| CPU time | 19.78 seconds |
| Started | Oct 03 08:16:09 AM UTC 24 |
| Finished | Oct 03 08:16:30 AM UTC 24 |
| Peak memory | 271372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3578064823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_lcmgr_intg.3578064823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2014268659 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 102400584000 ps |
| CPU time | 815.68 seconds |
| Started | Oct 03 08:14:15 AM UTC 24 |
| Finished | Oct 03 08:28:00 AM UTC 24 |
| Peak memory | 283324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2014268659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.2014268659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2633585090 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 43309500 ps |
| CPU time | 168.04 seconds |
| Started | Oct 03 08:14:14 AM UTC 24 |
| Finished | Oct 03 08:17:05 AM UTC 24 |
| Peak memory | 271192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633585090 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.2633585090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3302278676 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 204775500 ps |
| CPU time | 195.38 seconds |
| Started | Oct 03 08:14:10 AM UTC 24 |
| Finished | Oct 03 08:17:28 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302278676 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3302278676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.3886215017 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 5312118100 ps |
| CPU time | 156.4 seconds |
| Started | Oct 03 08:14:58 AM UTC 24 |
| Finished | Oct 03 08:17:37 AM UTC 24 |
| Peak memory | 271180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886215017 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.3886215017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.2990000945 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 412730200 ps |
| CPU time | 476.34 seconds |
| Started | Oct 03 08:14:09 AM UTC 24 |
| Finished | Oct 03 08:22:11 AM UTC 24 |
| Peak memory | 287500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990000945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2990000945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.195679548 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1096228400 ps |
| CPU time | 91.82 seconds |
| Started | Oct 03 08:14:34 AM UTC 24 |
| Finished | Oct 03 08:16:08 AM UTC 24 |
| Peak memory | 292064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=195679548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.195679548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.216433114 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3356442400 ps |
| CPU time | 528.13 seconds |
| Started | Oct 03 08:14:37 AM UTC 24 |
| Finished | Oct 03 08:23:31 AM UTC 24 |
| Peak memory | 330952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216433114 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.216433114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.580309633 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 29630100 ps |
| CPU time | 51.11 seconds |
| Started | Oct 03 08:15:20 AM UTC 24 |
| Finished | Oct 03 08:16:13 AM UTC 24 |
| Peak memory | 287700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=580309633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ct rl_rw_evict_all_en.580309633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.332068533 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 37159800 ps |
| CPU time | 225.9 seconds |
| Started | Oct 03 08:14:07 AM UTC 24 |
| Finished | Oct 03 08:17:57 AM UTC 24 |
| Peak memory | 289416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332068533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.332068533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.1588531669 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 7010055900 ps |
| CPU time | 143.86 seconds |
| Started | Oct 03 08:14:34 AM UTC 24 |
| Finished | Oct 03 08:17:01 AM UTC 24 |
| Peak memory | 271164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1588531669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.1588531669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.1683227266 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 78101800 ps |
| CPU time | 21.56 seconds |
| Started | Oct 03 08:18:14 AM UTC 24 |
| Finished | Oct 03 08:18:37 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683227266 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.1683227266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.3220982277 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 26746300 ps |
| CPU time | 31.83 seconds |
| Started | Oct 03 08:17:58 AM UTC 24 |
| Finished | Oct 03 08:18:31 AM UTC 24 |
| Peak memory | 284596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220982277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.3220982277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.2838330037 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 30347600 ps |
| CPU time | 26.48 seconds |
| Started | Oct 03 08:17:53 AM UTC 24 |
| Finished | Oct 03 08:18:20 AM UTC 24 |
| Peak memory | 285432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2838330037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ ctrl_disable.2838330037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2315581005 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 10034283700 ps |
| CPU time | 124.78 seconds |
| Started | Oct 03 08:18:13 AM UTC 24 |
| Finished | Oct 03 08:20:21 AM UTC 24 |
| Peak memory | 283404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2315581005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2315581005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.4084705601 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 40145500 ps |
| CPU time | 22.55 seconds |
| Started | Oct 03 08:18:05 AM UTC 24 |
| Finished | Oct 03 08:18:29 AM UTC 24 |
| Peak memory | 271296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4084705601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.4084705601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.1122510385 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 180172544600 ps |
| CPU time | 872.58 seconds |
| Started | Oct 03 08:16:43 AM UTC 24 |
| Finished | Oct 03 08:31:26 AM UTC 24 |
| Peak memory | 275040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122510385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res et.1122510385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.2430495098 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 25620420000 ps |
| CPU time | 60.31 seconds |
| Started | Oct 03 08:16:39 AM UTC 24 |
| Finished | Oct 03 08:17:41 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430495098 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.2430495098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.3568829342 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2995672200 ps |
| CPU time | 170.63 seconds |
| Started | Oct 03 08:17:06 AM UTC 24 |
| Finished | Oct 03 08:19:59 AM UTC 24 |
| Peak memory | 306124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568829342 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.3568829342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1628141705 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 23902830000 ps |
| CPU time | 298.23 seconds |
| Started | Oct 03 08:17:11 AM UTC 24 |
| Finished | Oct 03 08:22:13 AM UTC 24 |
| Peak memory | 301800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1628141705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_intr_rd_slow_flash.1628141705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.826917013 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 891841900 ps |
| CPU time | 92.46 seconds |
| Started | Oct 03 08:16:50 AM UTC 24 |
| Finished | Oct 03 08:18:25 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826917013 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.826917013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.449268749 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 41829200 ps |
| CPU time | 24.39 seconds |
| Started | Oct 03 08:17:58 AM UTC 24 |
| Finished | Oct 03 08:18:24 AM UTC 24 |
| Peak memory | 271052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=449268749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas h_ctrl_lcmgr_intg.449268749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3570830571 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 29105116600 ps |
| CPU time | 365.93 seconds |
| Started | Oct 03 08:16:50 AM UTC 24 |
| Finished | Oct 03 08:23:01 AM UTC 24 |
| Peak memory | 283332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3570830571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.3570830571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.188434615 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 88707100 ps |
| CPU time | 196.84 seconds |
| Started | Oct 03 08:16:50 AM UTC 24 |
| Finished | Oct 03 08:20:10 AM UTC 24 |
| Peak memory | 270944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188434615 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.188434615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.411128624 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 80935800 ps |
| CPU time | 96.01 seconds |
| Started | Oct 03 08:16:36 AM UTC 24 |
| Finished | Oct 03 08:18:14 AM UTC 24 |
| Peak memory | 275400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411128624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.411128624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.503482784 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 639012600 ps |
| CPU time | 35.47 seconds |
| Started | Oct 03 08:17:28 AM UTC 24 |
| Finished | Oct 03 08:18:05 AM UTC 24 |
| Peak memory | 271184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503482784 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.503482784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.1872885583 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 6395431100 ps |
| CPU time | 1194.81 seconds |
| Started | Oct 03 08:16:31 AM UTC 24 |
| Finished | Oct 03 08:36:42 AM UTC 24 |
| Peak memory | 293708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872885583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1872885583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.363209742 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1178757900 ps |
| CPU time | 60.97 seconds |
| Started | Oct 03 08:17:41 AM UTC 24 |
| Finished | Oct 03 08:18:44 AM UTC 24 |
| Peak memory | 287812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363209742 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.363209742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.3437929098 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2181976800 ps |
| CPU time | 141.95 seconds |
| Started | Oct 03 08:17:02 AM UTC 24 |
| Finished | Oct 03 08:19:27 AM UTC 24 |
| Peak memory | 308424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3437929098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.3437929098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.929399054 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 31516200 ps |
| CPU time | 42.21 seconds |
| Started | Oct 03 08:17:29 AM UTC 24 |
| Finished | Oct 03 08:18:13 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929399054 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.929399054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.4212875777 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 4002373400 ps |
| CPU time | 70.35 seconds |
| Started | Oct 03 08:17:55 AM UTC 24 |
| Finished | Oct 03 08:19:07 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212875777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.4212875777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.4004539299 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 57627000 ps |
| CPU time | 136.02 seconds |
| Started | Oct 03 08:16:31 AM UTC 24 |
| Finished | Oct 03 08:18:49 AM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004539299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.4004539299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.2895981894 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4671746100 ps |
| CPU time | 167.39 seconds |
| Started | Oct 03 08:17:02 AM UTC 24 |
| Finished | Oct 03 08:19:53 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2895981894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.2895981894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.2584318572 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 29777500 ps |
| CPU time | 26.23 seconds |
| Started | Oct 03 08:20:22 AM UTC 24 |
| Finished | Oct 03 08:20:49 AM UTC 24 |
| Peak memory | 275200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584318572 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.2584318572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.553038136 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 13985000 ps |
| CPU time | 20.75 seconds |
| Started | Oct 03 08:20:11 AM UTC 24 |
| Finished | Oct 03 08:20:33 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553038136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.553038136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.3330553091 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 12909900 ps |
| CPU time | 43.98 seconds |
| Started | Oct 03 08:20:00 AM UTC 24 |
| Finished | Oct 03 08:20:46 AM UTC 24 |
| Peak memory | 285584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3330553091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ ctrl_disable.3330553091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2826581590 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 10042521000 ps |
| CPU time | 50.26 seconds |
| Started | Oct 03 08:20:22 AM UTC 24 |
| Finished | Oct 03 08:21:14 AM UTC 24 |
| Peak memory | 283484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2826581590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2826581590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.4153827680 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 15119600 ps |
| CPU time | 28.5 seconds |
| Started | Oct 03 08:20:21 AM UTC 24 |
| Finished | Oct 03 08:20:51 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4153827680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.4153827680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.884950857 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 90154429200 ps |
| CPU time | 874.04 seconds |
| Started | Oct 03 08:18:30 AM UTC 24 |
| Finished | Oct 03 08:33:15 AM UTC 24 |
| Peak memory | 274984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884950857 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_reset.884950857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.2901060732 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 4496828600 ps |
| CPU time | 159.34 seconds |
| Started | Oct 03 08:18:26 AM UTC 24 |
| Finished | Oct 03 08:21:08 AM UTC 24 |
| Peak memory | 273032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901060732 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.2901060732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3470411870 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 15077637400 ps |
| CPU time | 246.93 seconds |
| Started | Oct 03 08:19:37 AM UTC 24 |
| Finished | Oct 03 08:23:47 AM UTC 24 |
| Peak memory | 305988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3470411870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_intr_rd_slow_flash.3470411870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.1761274078 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 3247217400 ps |
| CPU time | 84.67 seconds |
| Started | Oct 03 08:18:45 AM UTC 24 |
| Finished | Oct 03 08:20:11 AM UTC 24 |
| Peak memory | 275016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761274078 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1761274078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.1149093892 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 32324984900 ps |
| CPU time | 292.82 seconds |
| Started | Oct 03 08:18:38 AM UTC 24 |
| Finished | Oct 03 08:23:36 AM UTC 24 |
| Peak memory | 283324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1149093892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.1149093892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.2219264154 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 39904100 ps |
| CPU time | 184.17 seconds |
| Started | Oct 03 08:18:32 AM UTC 24 |
| Finished | Oct 03 08:21:40 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219264154 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.2219264154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.1761164692 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 129399800 ps |
| CPU time | 224.9 seconds |
| Started | Oct 03 08:18:25 AM UTC 24 |
| Finished | Oct 03 08:22:13 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761164692 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1761164692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.3812832740 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 21016300 ps |
| CPU time | 26.34 seconds |
| Started | Oct 03 08:19:37 AM UTC 24 |
| Finished | Oct 03 08:20:04 AM UTC 24 |
| Peak memory | 271160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812832740 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.3812832740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.2039067751 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 425516100 ps |
| CPU time | 515.02 seconds |
| Started | Oct 03 08:18:23 AM UTC 24 |
| Finished | Oct 03 08:27:04 AM UTC 24 |
| Peak memory | 291468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039067751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2039067751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.500527566 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 269696200 ps |
| CPU time | 62.05 seconds |
| Started | Oct 03 08:19:53 AM UTC 24 |
| Finished | Oct 03 08:20:57 AM UTC 24 |
| Peak memory | 289732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500527566 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.500527566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.3344139067 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 550858300 ps |
| CPU time | 112.28 seconds |
| Started | Oct 03 08:19:06 AM UTC 24 |
| Finished | Oct 03 08:21:00 AM UTC 24 |
| Peak memory | 302216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3344139067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.3344139067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.896984145 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 15573787500 ps |
| CPU time | 472.93 seconds |
| Started | Oct 03 08:19:08 AM UTC 24 |
| Finished | Oct 03 08:27:07 AM UTC 24 |
| Peak memory | 330756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896984145 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.896984145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.1362268252 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 315991500 ps |
| CPU time | 46.34 seconds |
| Started | Oct 03 08:19:38 AM UTC 24 |
| Finished | Oct 03 08:20:26 AM UTC 24 |
| Peak memory | 285656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362268252 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.1362268252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.1768181081 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 65395500 ps |
| CPU time | 52.51 seconds |
| Started | Oct 03 08:19:48 AM UTC 24 |
| Finished | Oct 03 08:20:42 AM UTC 24 |
| Peak memory | 287708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1768181081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c trl_rw_evict_all_en.1768181081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.286286426 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2515285300 ps |
| CPU time | 89.93 seconds |
| Started | Oct 03 08:20:05 AM UTC 24 |
| Finished | Oct 03 08:21:37 AM UTC 24 |
| Peak memory | 275156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286286426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.286286426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.2639840347 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 34432500 ps |
| CPU time | 83.44 seconds |
| Started | Oct 03 08:18:22 AM UTC 24 |
| Finished | Oct 03 08:19:47 AM UTC 24 |
| Peak memory | 285320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639840347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2639840347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.3704105278 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 12051149700 ps |
| CPU time | 205.36 seconds |
| Started | Oct 03 08:18:50 AM UTC 24 |
| Finished | Oct 03 08:22:18 AM UTC 24 |
| Peak memory | 275252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3704105278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.3704105278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.3233391007 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 76738000 ps |
| CPU time | 23.89 seconds |
| Started | Oct 03 08:22:52 AM UTC 24 |
| Finished | Oct 03 08:23:17 AM UTC 24 |
| Peak memory | 269240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233391007 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.3233391007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.87302152 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 51391800 ps |
| CPU time | 19.66 seconds |
| Started | Oct 03 08:22:19 AM UTC 24 |
| Finished | Oct 03 08:22:40 AM UTC 24 |
| Peak memory | 284616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87302152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.87302152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.3049678435 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 17691500 ps |
| CPU time | 34.69 seconds |
| Started | Oct 03 08:22:15 AM UTC 24 |
| Finished | Oct 03 08:22:51 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3049678435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ ctrl_disable.3049678435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2837332589 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 10012048800 ps |
| CPU time | 121.59 seconds |
| Started | Oct 03 08:22:51 AM UTC 24 |
| Finished | Oct 03 08:24:54 AM UTC 24 |
| Peak memory | 330712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2837332589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2837332589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.2650651100 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 108978600 ps |
| CPU time | 20.11 seconds |
| Started | Oct 03 08:22:42 AM UTC 24 |
| Finished | Oct 03 08:23:04 AM UTC 24 |
| Peak memory | 275400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2650651100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.2650651100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.3981769480 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 180184873500 ps |
| CPU time | 992.69 seconds |
| Started | Oct 03 08:20:47 AM UTC 24 |
| Finished | Oct 03 08:37:31 AM UTC 24 |
| Peak memory | 274972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981769480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_res et.3981769480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.2294040498 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 11306662100 ps |
| CPU time | 233.55 seconds |
| Started | Oct 03 08:20:44 AM UTC 24 |
| Finished | Oct 03 08:24:41 AM UTC 24 |
| Peak memory | 273036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294040498 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.2294040498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3646593401 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 12237738600 ps |
| CPU time | 320.71 seconds |
| Started | Oct 03 08:21:38 AM UTC 24 |
| Finished | Oct 03 08:27:03 AM UTC 24 |
| Peak memory | 304108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3646593401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_intr_rd_slow_flash.3646593401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3612656717 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 7931741400 ps |
| CPU time | 78.22 seconds |
| Started | Oct 03 08:20:58 AM UTC 24 |
| Finished | Oct 03 08:22:18 AM UTC 24 |
| Peak memory | 270912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612656717 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3612656717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.3701718066 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 15868900 ps |
| CPU time | 19.26 seconds |
| Started | Oct 03 08:22:41 AM UTC 24 |
| Finished | Oct 03 08:23:02 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3701718066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_lcmgr_intg.3701718066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.9775175 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2702869500 ps |
| CPU time | 122.47 seconds |
| Started | Oct 03 08:20:52 AM UTC 24 |
| Finished | Oct 03 08:22:57 AM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=9775175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 13.flash_ctrl_mp_regions.9775175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.1408063997 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 130711100 ps |
| CPU time | 246.22 seconds |
| Started | Oct 03 08:20:50 AM UTC 24 |
| Finished | Oct 03 08:25:00 AM UTC 24 |
| Peak memory | 270944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408063997 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.1408063997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.3480054847 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 113032700 ps |
| CPU time | 158.8 seconds |
| Started | Oct 03 08:20:43 AM UTC 24 |
| Finished | Oct 03 08:23:24 AM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480054847 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3480054847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.869990714 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 639261200 ps |
| CPU time | 31.98 seconds |
| Started | Oct 03 08:21:40 AM UTC 24 |
| Finished | Oct 03 08:22:14 AM UTC 24 |
| Peak memory | 275200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869990714 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.869990714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.3446529763 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 43950100 ps |
| CPU time | 194.42 seconds |
| Started | Oct 03 08:20:34 AM UTC 24 |
| Finished | Oct 03 08:23:52 AM UTC 24 |
| Peak memory | 291660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446529763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3446529763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.3104019324 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 477815000 ps |
| CPU time | 105.76 seconds |
| Started | Oct 03 08:21:10 AM UTC 24 |
| Finished | Oct 03 08:22:58 AM UTC 24 |
| Peak memory | 302108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3104019324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.3104019324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.2607388844 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 15022607300 ps |
| CPU time | 444.64 seconds |
| Started | Oct 03 08:21:14 AM UTC 24 |
| Finished | Oct 03 08:28:44 AM UTC 24 |
| Peak memory | 320548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607388844 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.2607388844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.487969953 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 74302500 ps |
| CPU time | 37.01 seconds |
| Started | Oct 03 08:22:11 AM UTC 24 |
| Finished | Oct 03 08:22:50 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487969953 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.487969953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.2726854750 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 60110000 ps |
| CPU time | 47.47 seconds |
| Started | Oct 03 08:22:15 AM UTC 24 |
| Finished | Oct 03 08:23:04 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2726854750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c trl_rw_evict_all_en.2726854750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2320323021 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 7593186500 ps |
| CPU time | 95.77 seconds |
| Started | Oct 03 08:22:19 AM UTC 24 |
| Finished | Oct 03 08:23:57 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320323021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2320323021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.2277176809 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 66060300 ps |
| CPU time | 151.38 seconds |
| Started | Oct 03 08:20:26 AM UTC 24 |
| Finished | Oct 03 08:23:00 AM UTC 24 |
| Peak memory | 287372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277176809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2277176809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.2209382027 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1832345400 ps |
| CPU time | 167.91 seconds |
| Started | Oct 03 08:21:01 AM UTC 24 |
| Finished | Oct 03 08:23:52 AM UTC 24 |
| Peak memory | 275252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2209382027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.2209382027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.1193508633 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 377143100 ps |
| CPU time | 22.25 seconds |
| Started | Oct 03 08:24:48 AM UTC 24 |
| Finished | Oct 03 08:25:11 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193508633 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.1193508633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.2774150560 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 25774000 ps |
| CPU time | 27.06 seconds |
| Started | Oct 03 08:24:33 AM UTC 24 |
| Finished | Oct 03 08:25:01 AM UTC 24 |
| Peak memory | 284616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774150560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.2774150560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.2992854943 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 104306200 ps |
| CPU time | 37.95 seconds |
| Started | Oct 03 08:24:01 AM UTC 24 |
| Finished | Oct 03 08:24:41 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2992854943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ ctrl_disable.2992854943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.449370738 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 10012330500 ps |
| CPU time | 375.11 seconds |
| Started | Oct 03 08:24:41 AM UTC 24 |
| Finished | Oct 03 08:31:02 AM UTC 24 |
| Peak memory | 312004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=449370738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.449370738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.173381783 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 19578900 ps |
| CPU time | 28.18 seconds |
| Started | Oct 03 08:24:41 AM UTC 24 |
| Finished | Oct 03 08:25:11 AM UTC 24 |
| Peak memory | 275444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=173381783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.flash_ctrl_hw_read_seed_err.173381783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.4211268005 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 40127001400 ps |
| CPU time | 867.79 seconds |
| Started | Oct 03 08:23:03 AM UTC 24 |
| Finished | Oct 03 08:37:42 AM UTC 24 |
| Peak memory | 275044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211268005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_res et.4211268005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.3182890641 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1750446000 ps |
| CPU time | 132.74 seconds |
| Started | Oct 03 08:23:03 AM UTC 24 |
| Finished | Oct 03 08:25:18 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182890641 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.3182890641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.4080279204 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 574809900 ps |
| CPU time | 131.64 seconds |
| Started | Oct 03 08:23:38 AM UTC 24 |
| Finished | Oct 03 08:25:52 AM UTC 24 |
| Peak memory | 306096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080279204 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.4080279204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1972022702 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 48271730200 ps |
| CPU time | 271.43 seconds |
| Started | Oct 03 08:23:46 AM UTC 24 |
| Finished | Oct 03 08:28:21 AM UTC 24 |
| Peak memory | 303848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1972022702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_intr_rd_slow_flash.1972022702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.1701068261 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 6166113500 ps |
| CPU time | 89.62 seconds |
| Started | Oct 03 08:23:04 AM UTC 24 |
| Finished | Oct 03 08:24:36 AM UTC 24 |
| Peak memory | 275008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701068261 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1701068261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.3309601216 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 15559800 ps |
| CPU time | 23.06 seconds |
| Started | Oct 03 08:24:37 AM UTC 24 |
| Finished | Oct 03 08:25:01 AM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3309601216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla sh_ctrl_lcmgr_intg.3309601216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.2873727702 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 10026434200 ps |
| CPU time | 300.21 seconds |
| Started | Oct 03 08:23:04 AM UTC 24 |
| Finished | Oct 03 08:28:09 AM UTC 24 |
| Peak memory | 283328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2873727702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.2873727702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.2614402192 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 43441200 ps |
| CPU time | 168.07 seconds |
| Started | Oct 03 08:23:04 AM UTC 24 |
| Finished | Oct 03 08:25:55 AM UTC 24 |
| Peak memory | 275296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614402192 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.2614402192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.1687910561 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 90607400 ps |
| CPU time | 611.85 seconds |
| Started | Oct 03 08:23:00 AM UTC 24 |
| Finished | Oct 03 08:33:20 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687910561 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1687910561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.4067686922 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 66586200 ps |
| CPU time | 22.03 seconds |
| Started | Oct 03 08:23:48 AM UTC 24 |
| Finished | Oct 03 08:24:11 AM UTC 24 |
| Peak memory | 271288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067686922 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.4067686922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.2601199018 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 36274400 ps |
| CPU time | 339.08 seconds |
| Started | Oct 03 08:22:58 AM UTC 24 |
| Finished | Oct 03 08:28:42 AM UTC 24 |
| Peak memory | 291468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601199018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.2601199018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.1060289606 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 109642800 ps |
| CPU time | 56.15 seconds |
| Started | Oct 03 08:23:57 AM UTC 24 |
| Finished | Oct 03 08:24:55 AM UTC 24 |
| Peak memory | 283580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060289606 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.1060289606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.2725037535 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1882312700 ps |
| CPU time | 107.55 seconds |
| Started | Oct 03 08:23:25 AM UTC 24 |
| Finished | Oct 03 08:25:15 AM UTC 24 |
| Peak memory | 291740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2725037535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.2725037535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.3858439896 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4923393000 ps |
| CPU time | 464 seconds |
| Started | Oct 03 08:23:32 AM UTC 24 |
| Finished | Oct 03 08:31:21 AM UTC 24 |
| Peak memory | 332816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858439896 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.3858439896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.1242561814 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 74774500 ps |
| CPU time | 52.09 seconds |
| Started | Oct 03 08:23:53 AM UTC 24 |
| Finished | Oct 03 08:24:47 AM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242561814 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.1242561814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.1370691476 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 184487600 ps |
| CPU time | 36.92 seconds |
| Started | Oct 03 08:23:53 AM UTC 24 |
| Finished | Oct 03 08:24:31 AM UTC 24 |
| Peak memory | 287604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1370691476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c trl_rw_evict_all_en.1370691476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.614267419 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 50476100 ps |
| CPU time | 118.41 seconds |
| Started | Oct 03 08:22:58 AM UTC 24 |
| Finished | Oct 03 08:24:59 AM UTC 24 |
| Peak memory | 287500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614267419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.614267419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.1715177615 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 12027948300 ps |
| CPU time | 243 seconds |
| Started | Oct 03 08:23:18 AM UTC 24 |
| Finished | Oct 03 08:27:25 AM UTC 24 |
| Peak memory | 275256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1715177615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.1715177615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.2761090716 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 21621400 ps |
| CPU time | 26.01 seconds |
| Started | Oct 03 08:27:04 AM UTC 24 |
| Finished | Oct 03 08:27:31 AM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761090716 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.2761090716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.3392636770 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 13750500 ps |
| CPU time | 18.31 seconds |
| Started | Oct 03 08:26:43 AM UTC 24 |
| Finished | Oct 03 08:27:03 AM UTC 24 |
| Peak memory | 284616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392636770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3392636770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.2261211371 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 18280300 ps |
| CPU time | 36.82 seconds |
| Started | Oct 03 08:26:28 AM UTC 24 |
| Finished | Oct 03 08:27:06 AM UTC 24 |
| Peak memory | 285652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2261211371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ ctrl_disable.2261211371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1281808527 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 10012513600 ps |
| CPU time | 313.66 seconds |
| Started | Oct 03 08:27:00 AM UTC 24 |
| Finished | Oct 03 08:32:18 AM UTC 24 |
| Peak memory | 334600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1281808527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.1281808527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.1694257240 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 18070500 ps |
| CPU time | 18.09 seconds |
| Started | Oct 03 08:26:49 AM UTC 24 |
| Finished | Oct 03 08:27:09 AM UTC 24 |
| Peak memory | 269252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1694257240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1694257240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.3249264885 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 140169020700 ps |
| CPU time | 878.34 seconds |
| Started | Oct 03 08:25:02 AM UTC 24 |
| Finished | Oct 03 08:39:51 AM UTC 24 |
| Peak memory | 275164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249264885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_res et.3249264885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.476061424 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2381879100 ps |
| CPU time | 229.39 seconds |
| Started | Oct 03 08:25:01 AM UTC 24 |
| Finished | Oct 03 08:28:54 AM UTC 24 |
| Peak memory | 273036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476061424 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.476061424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3503705922 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 11581315800 ps |
| CPU time | 213.99 seconds |
| Started | Oct 03 08:25:40 AM UTC 24 |
| Finished | Oct 03 08:29:17 AM UTC 24 |
| Peak memory | 303852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3503705922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_intr_rd_slow_flash.3503705922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.748976439 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 9225467500 ps |
| CPU time | 70.83 seconds |
| Started | Oct 03 08:25:12 AM UTC 24 |
| Finished | Oct 03 08:26:25 AM UTC 24 |
| Peak memory | 275012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748976439 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.748976439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.301378415 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 15526000 ps |
| CPU time | 20.35 seconds |
| Started | Oct 03 08:26:48 AM UTC 24 |
| Finished | Oct 03 08:27:10 AM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=301378415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flas h_ctrl_lcmgr_intg.301378415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.1043032694 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 7755154000 ps |
| CPU time | 493.27 seconds |
| Started | Oct 03 08:25:11 AM UTC 24 |
| Finished | Oct 03 08:33:31 AM UTC 24 |
| Peak memory | 283524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1043032694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.1043032694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.1182269110 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 147109300 ps |
| CPU time | 194.14 seconds |
| Started | Oct 03 08:25:02 AM UTC 24 |
| Finished | Oct 03 08:28:19 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182269110 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.1182269110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.2518952766 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 28500600 ps |
| CPU time | 84.99 seconds |
| Started | Oct 03 08:25:00 AM UTC 24 |
| Finished | Oct 03 08:26:27 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518952766 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2518952766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.2316468451 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 59118600 ps |
| CPU time | 18.52 seconds |
| Started | Oct 03 08:25:52 AM UTC 24 |
| Finished | Oct 03 08:26:12 AM UTC 24 |
| Peak memory | 271372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316468451 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.2316468451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.4138542462 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 44079300 ps |
| CPU time | 544.44 seconds |
| Started | Oct 03 08:24:56 AM UTC 24 |
| Finished | Oct 03 08:34:07 AM UTC 24 |
| Peak memory | 291660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138542462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.4138542462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.1745327710 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 121563700 ps |
| CPU time | 39.88 seconds |
| Started | Oct 03 08:26:26 AM UTC 24 |
| Finished | Oct 03 08:27:07 AM UTC 24 |
| Peak memory | 287872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745327710 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.1745327710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.1293521646 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2433172400 ps |
| CPU time | 97.02 seconds |
| Started | Oct 03 08:25:20 AM UTC 24 |
| Finished | Oct 03 08:26:59 AM UTC 24 |
| Peak memory | 291916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1293521646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.1293521646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.634500483 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4837935700 ps |
| CPU time | 471.42 seconds |
| Started | Oct 03 08:25:20 AM UTC 24 |
| Finished | Oct 03 08:33:17 AM UTC 24 |
| Peak memory | 330764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634500483 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.634500483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.4057531409 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 37687800 ps |
| CPU time | 44.32 seconds |
| Started | Oct 03 08:25:56 AM UTC 24 |
| Finished | Oct 03 08:26:42 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057531409 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.4057531409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.2474180846 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 28813400 ps |
| CPU time | 33.51 seconds |
| Started | Oct 03 08:26:13 AM UTC 24 |
| Finished | Oct 03 08:26:47 AM UTC 24 |
| Peak memory | 285820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2474180846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c trl_rw_evict_all_en.2474180846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.4160341173 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 89769000 ps |
| CPU time | 295.97 seconds |
| Started | Oct 03 08:24:56 AM UTC 24 |
| Finished | Oct 03 08:29:56 AM UTC 24 |
| Peak memory | 281420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160341173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.4160341173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.4035085547 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 9727946000 ps |
| CPU time | 247.18 seconds |
| Started | Oct 03 08:25:16 AM UTC 24 |
| Finished | Oct 03 08:29:26 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4035085547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.4035085547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.3866131284 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 38062800 ps |
| CPU time | 20.8 seconds |
| Started | Oct 03 08:29:16 AM UTC 24 |
| Finished | Oct 03 08:29:38 AM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866131284 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.3866131284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.1845791370 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 16471400 ps |
| CPU time | 21.92 seconds |
| Started | Oct 03 08:28:55 AM UTC 24 |
| Finished | Oct 03 08:29:18 AM UTC 24 |
| Peak memory | 284612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845791370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1845791370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.1320221491 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 28135900 ps |
| CPU time | 28.18 seconds |
| Started | Oct 03 08:28:45 AM UTC 24 |
| Finished | Oct 03 08:29:15 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1320221491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ ctrl_disable.1320221491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3357672051 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 10019440800 ps |
| CPU time | 92.68 seconds |
| Started | Oct 03 08:29:00 AM UTC 24 |
| Finished | Oct 03 08:30:35 AM UTC 24 |
| Peak memory | 285556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3357672051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3357672051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.4276568786 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 15436900 ps |
| CPU time | 24.72 seconds |
| Started | Oct 03 08:28:59 AM UTC 24 |
| Finished | Oct 03 08:29:25 AM UTC 24 |
| Peak memory | 275252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4276568786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.4276568786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.1630935817 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 160171763000 ps |
| CPU time | 821.57 seconds |
| Started | Oct 03 08:27:08 AM UTC 24 |
| Finished | Oct 03 08:41:00 AM UTC 24 |
| Peak memory | 274972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630935817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res et.1630935817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.3916269663 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3373121600 ps |
| CPU time | 149.04 seconds |
| Started | Oct 03 08:27:08 AM UTC 24 |
| Finished | Oct 03 08:29:40 AM UTC 24 |
| Peak memory | 271180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916269663 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.3916269663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.4097211258 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 7365188500 ps |
| CPU time | 136.2 seconds |
| Started | Oct 03 08:28:03 AM UTC 24 |
| Finished | Oct 03 08:30:22 AM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097211258 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.4097211258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.742652538 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 11850155400 ps |
| CPU time | 124.29 seconds |
| Started | Oct 03 08:28:10 AM UTC 24 |
| Finished | Oct 03 08:30:17 AM UTC 24 |
| Peak memory | 303852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=742652538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 16.flash_ctrl_intr_rd_slow_flash.742652538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.2962286218 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3145949800 ps |
| CPU time | 86.18 seconds |
| Started | Oct 03 08:27:26 AM UTC 24 |
| Finished | Oct 03 08:28:54 AM UTC 24 |
| Peak memory | 275012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962286218 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2962286218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.2390801899 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 15158700 ps |
| CPU time | 26.5 seconds |
| Started | Oct 03 08:28:55 AM UTC 24 |
| Finished | Oct 03 08:29:23 AM UTC 24 |
| Peak memory | 273160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2390801899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_lcmgr_intg.2390801899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.1924934204 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 12169832600 ps |
| CPU time | 950.49 seconds |
| Started | Oct 03 08:27:11 AM UTC 24 |
| Finished | Oct 03 08:43:13 AM UTC 24 |
| Peak memory | 283540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1924934204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.1924934204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.3852493703 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 74632400 ps |
| CPU time | 176.27 seconds |
| Started | Oct 03 08:27:10 AM UTC 24 |
| Finished | Oct 03 08:30:09 AM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852493703 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.3852493703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.732803424 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 103668800 ps |
| CPU time | 255.35 seconds |
| Started | Oct 03 08:27:07 AM UTC 24 |
| Finished | Oct 03 08:31:27 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732803424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.732803424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.3820678149 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 20885600 ps |
| CPU time | 23.23 seconds |
| Started | Oct 03 08:28:21 AM UTC 24 |
| Finished | Oct 03 08:28:45 AM UTC 24 |
| Peak memory | 271096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820678149 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.3820678149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.4232008347 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 82233700 ps |
| CPU time | 613.1 seconds |
| Started | Oct 03 08:27:05 AM UTC 24 |
| Finished | Oct 03 08:37:26 AM UTC 24 |
| Peak memory | 293516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232008347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.4232008347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.1651953688 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1260442400 ps |
| CPU time | 38.45 seconds |
| Started | Oct 03 08:28:43 AM UTC 24 |
| Finished | Oct 03 08:29:23 AM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651953688 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.1651953688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.3991429702 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 560556900 ps |
| CPU time | 110.4 seconds |
| Started | Oct 03 08:27:45 AM UTC 24 |
| Finished | Oct 03 08:29:38 AM UTC 24 |
| Peak memory | 292108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3991429702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.3991429702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.850954928 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 13137472200 ps |
| CPU time | 545.24 seconds |
| Started | Oct 03 08:27:50 AM UTC 24 |
| Finished | Oct 03 08:37:03 AM UTC 24 |
| Peak memory | 331052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850954928 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.850954928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.3450509475 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 29080000 ps |
| CPU time | 34.26 seconds |
| Started | Oct 03 08:28:22 AM UTC 24 |
| Finished | Oct 03 08:28:58 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450509475 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.3450509475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.2190922296 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 71669100 ps |
| CPU time | 47.75 seconds |
| Started | Oct 03 08:28:28 AM UTC 24 |
| Finished | Oct 03 08:29:17 AM UTC 24 |
| Peak memory | 287604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2190922296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c trl_rw_evict_all_en.2190922296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.103678959 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 4179469500 ps |
| CPU time | 89.16 seconds |
| Started | Oct 03 08:28:46 AM UTC 24 |
| Finished | Oct 03 08:30:17 AM UTC 24 |
| Peak memory | 275348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103678959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.103678959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.2767495104 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 18885100 ps |
| CPU time | 131.9 seconds |
| Started | Oct 03 08:27:05 AM UTC 24 |
| Finished | Oct 03 08:29:19 AM UTC 24 |
| Peak memory | 287372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767495104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2767495104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.2567371415 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 19220314600 ps |
| CPU time | 175.94 seconds |
| Started | Oct 03 08:27:32 AM UTC 24 |
| Finished | Oct 03 08:30:31 AM UTC 24 |
| Peak memory | 271164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2567371415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.2567371415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.2008358654 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 139251900 ps |
| CPU time | 20.02 seconds |
| Started | Oct 03 08:31:12 AM UTC 24 |
| Finished | Oct 03 08:31:34 AM UTC 24 |
| Peak memory | 275448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008358654 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.2008358654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.1479295796 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 24671300 ps |
| CPU time | 26.26 seconds |
| Started | Oct 03 08:30:36 AM UTC 24 |
| Finished | Oct 03 08:31:03 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479295796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1479295796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3705869248 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 10012366900 ps |
| CPU time | 112.11 seconds |
| Started | Oct 03 08:31:04 AM UTC 24 |
| Finished | Oct 03 08:32:59 AM UTC 24 |
| Peak memory | 330780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3705869248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3705869248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.4073894695 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 15061400 ps |
| CPU time | 23.72 seconds |
| Started | Oct 03 08:31:03 AM UTC 24 |
| Finished | Oct 03 08:31:28 AM UTC 24 |
| Peak memory | 275328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4073894695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.4073894695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.2814457251 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 160202474100 ps |
| CPU time | 1083.64 seconds |
| Started | Oct 03 08:29:24 AM UTC 24 |
| Finished | Oct 03 08:47:42 AM UTC 24 |
| Peak memory | 274716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814457251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_res et.2814457251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.322415276 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 12200401600 ps |
| CPU time | 141.36 seconds |
| Started | Oct 03 08:29:21 AM UTC 24 |
| Finished | Oct 03 08:31:44 AM UTC 24 |
| Peak memory | 270988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322415276 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.322415276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.2594178483 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1301829600 ps |
| CPU time | 153.71 seconds |
| Started | Oct 03 08:29:57 AM UTC 24 |
| Finished | Oct 03 08:32:33 AM UTC 24 |
| Peak memory | 306096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594178483 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.2594178483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2322551784 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 61724976600 ps |
| CPU time | 234.06 seconds |
| Started | Oct 03 08:30:10 AM UTC 24 |
| Finished | Oct 03 08:34:08 AM UTC 24 |
| Peak memory | 303852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2322551784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_intr_rd_slow_flash.2322551784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.2630916704 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 921770100 ps |
| CPU time | 112.15 seconds |
| Started | Oct 03 08:29:27 AM UTC 24 |
| Finished | Oct 03 08:31:22 AM UTC 24 |
| Peak memory | 275012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630916704 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2630916704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.3102027332 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 45886100 ps |
| CPU time | 28.44 seconds |
| Started | Oct 03 08:31:00 AM UTC 24 |
| Finished | Oct 03 08:31:30 AM UTC 24 |
| Peak memory | 271180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3102027332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_lcmgr_intg.3102027332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.2723594178 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 16186424700 ps |
| CPU time | 341.34 seconds |
| Started | Oct 03 08:29:26 AM UTC 24 |
| Finished | Oct 03 08:35:12 AM UTC 24 |
| Peak memory | 283344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2723594178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.2723594178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.1329252271 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 73491100 ps |
| CPU time | 166.51 seconds |
| Started | Oct 03 08:29:24 AM UTC 24 |
| Finished | Oct 03 08:32:13 AM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329252271 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.1329252271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.301686098 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 155461600 ps |
| CPU time | 470.75 seconds |
| Started | Oct 03 08:29:19 AM UTC 24 |
| Finished | Oct 03 08:37:16 AM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301686098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.301686098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.3346921027 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 20469700 ps |
| CPU time | 16.06 seconds |
| Started | Oct 03 08:30:18 AM UTC 24 |
| Finished | Oct 03 08:30:35 AM UTC 24 |
| Peak memory | 275128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346921027 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.3346921027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.1811187715 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 3051505000 ps |
| CPU time | 659.43 seconds |
| Started | Oct 03 08:29:18 AM UTC 24 |
| Finished | Oct 03 08:40:25 AM UTC 24 |
| Peak memory | 291468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811187715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1811187715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.3327370236 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 80147500 ps |
| CPU time | 49.85 seconds |
| Started | Oct 03 08:30:23 AM UTC 24 |
| Finished | Oct 03 08:31:15 AM UTC 24 |
| Peak memory | 287936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327370236 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.3327370236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.3510145006 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 572140800 ps |
| CPU time | 104.46 seconds |
| Started | Oct 03 08:29:39 AM UTC 24 |
| Finished | Oct 03 08:31:26 AM UTC 24 |
| Peak memory | 291872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3510145006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.3510145006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.1530404930 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3635135800 ps |
| CPU time | 472.94 seconds |
| Started | Oct 03 08:29:40 AM UTC 24 |
| Finished | Oct 03 08:37:39 AM UTC 24 |
| Peak memory | 330760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530404930 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.1530404930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.1185668272 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 112388100 ps |
| CPU time | 39.14 seconds |
| Started | Oct 03 08:30:18 AM UTC 24 |
| Finished | Oct 03 08:30:59 AM UTC 24 |
| Peak memory | 283584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185668272 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.1185668272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.3710349379 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 98508000 ps |
| CPU time | 52.02 seconds |
| Started | Oct 03 08:30:22 AM UTC 24 |
| Finished | Oct 03 08:31:16 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3710349379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c trl_rw_evict_all_en.3710349379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.500857288 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 10838851700 ps |
| CPU time | 109.06 seconds |
| Started | Oct 03 08:30:36 AM UTC 24 |
| Finished | Oct 03 08:32:27 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500857288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.500857288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.2278867044 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 23472200 ps |
| CPU time | 209.18 seconds |
| Started | Oct 03 08:29:18 AM UTC 24 |
| Finished | Oct 03 08:32:51 AM UTC 24 |
| Peak memory | 287372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278867044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.2278867044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.974573731 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3364062800 ps |
| CPU time | 140.34 seconds |
| Started | Oct 03 08:29:38 AM UTC 24 |
| Finished | Oct 03 08:32:01 AM UTC 24 |
| Peak memory | 271168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =974573731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.974573731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.3081115348 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 31434500 ps |
| CPU time | 20.21 seconds |
| Started | Oct 03 08:33:09 AM UTC 24 |
| Finished | Oct 03 08:33:30 AM UTC 24 |
| Peak memory | 275384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081115348 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.3081115348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.397143911 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 56257900 ps |
| CPU time | 24.44 seconds |
| Started | Oct 03 08:32:59 AM UTC 24 |
| Finished | Oct 03 08:33:25 AM UTC 24 |
| Peak memory | 294920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397143911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.397143911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.2163384893 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 30987200 ps |
| CPU time | 32.49 seconds |
| Started | Oct 03 08:32:34 AM UTC 24 |
| Finished | Oct 03 08:33:08 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2163384893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ ctrl_disable.2163384893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1396522685 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 10014970000 ps |
| CPU time | 158.1 seconds |
| Started | Oct 03 08:33:06 AM UTC 24 |
| Finished | Oct 03 08:35:47 AM UTC 24 |
| Peak memory | 314324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1396522685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1396522685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.2657682887 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 15310100 ps |
| CPU time | 27.07 seconds |
| Started | Oct 03 08:33:00 AM UTC 24 |
| Finished | Oct 03 08:33:29 AM UTC 24 |
| Peak memory | 275116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2657682887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.2657682887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.3779863287 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 210210586800 ps |
| CPU time | 945.71 seconds |
| Started | Oct 03 08:31:22 AM UTC 24 |
| Finished | Oct 03 08:47:19 AM UTC 24 |
| Peak memory | 274976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779863287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_res et.3779863287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.3682242705 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 4602017700 ps |
| CPU time | 94.79 seconds |
| Started | Oct 03 08:31:22 AM UTC 24 |
| Finished | Oct 03 08:32:59 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682242705 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.3682242705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.1213127097 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 7098618900 ps |
| CPU time | 200.2 seconds |
| Started | Oct 03 08:31:45 AM UTC 24 |
| Finished | Oct 03 08:35:09 AM UTC 24 |
| Peak memory | 302128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213127097 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.1213127097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3511339132 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 19434899900 ps |
| CPU time | 141.03 seconds |
| Started | Oct 03 08:32:02 AM UTC 24 |
| Finished | Oct 03 08:34:26 AM UTC 24 |
| Peak memory | 303852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3511339132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_intr_rd_slow_flash.3511339132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.4116027103 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 10632094200 ps |
| CPU time | 95.09 seconds |
| Started | Oct 03 08:31:28 AM UTC 24 |
| Finished | Oct 03 08:33:05 AM UTC 24 |
| Peak memory | 275016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116027103 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.4116027103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.984371085 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 26863900 ps |
| CPU time | 20.76 seconds |
| Started | Oct 03 08:33:00 AM UTC 24 |
| Finished | Oct 03 08:33:22 AM UTC 24 |
| Peak memory | 273480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=984371085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flas h_ctrl_lcmgr_intg.984371085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.1935241005 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1816381700 ps |
| CPU time | 193.01 seconds |
| Started | Oct 03 08:31:28 AM UTC 24 |
| Finished | Oct 03 08:34:44 AM UTC 24 |
| Peak memory | 275132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1935241005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.1935241005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.994086013 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 379083900 ps |
| CPU time | 181.73 seconds |
| Started | Oct 03 08:31:26 AM UTC 24 |
| Finished | Oct 03 08:34:31 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994086013 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.994086013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.1390824949 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 717329400 ps |
| CPU time | 254.69 seconds |
| Started | Oct 03 08:31:17 AM UTC 24 |
| Finished | Oct 03 08:35:35 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390824949 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1390824949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.558152440 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3808657800 ps |
| CPU time | 167.24 seconds |
| Started | Oct 03 08:32:13 AM UTC 24 |
| Finished | Oct 03 08:35:03 AM UTC 24 |
| Peak memory | 275256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558152440 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.558152440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.3687771812 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 229814900 ps |
| CPU time | 773.49 seconds |
| Started | Oct 03 08:31:16 AM UTC 24 |
| Finished | Oct 03 08:44:18 AM UTC 24 |
| Peak memory | 295564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687771812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3687771812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.180153543 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 277183000 ps |
| CPU time | 49.25 seconds |
| Started | Oct 03 08:32:33 AM UTC 24 |
| Finished | Oct 03 08:33:24 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180153543 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.180153543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.28513424 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3876521500 ps |
| CPU time | 95.65 seconds |
| Started | Oct 03 08:31:31 AM UTC 24 |
| Finished | Oct 03 08:33:08 AM UTC 24 |
| Peak memory | 291920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=28513424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.28513424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.1316908473 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 6172505300 ps |
| CPU time | 375.73 seconds |
| Started | Oct 03 08:31:35 AM UTC 24 |
| Finished | Oct 03 08:37:55 AM UTC 24 |
| Peak memory | 324688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316908473 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.1316908473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.467971943 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 153378300 ps |
| CPU time | 39.6 seconds |
| Started | Oct 03 08:32:19 AM UTC 24 |
| Finished | Oct 03 08:33:00 AM UTC 24 |
| Peak memory | 283580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467971943 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.467971943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.2880741749 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 29923900 ps |
| CPU time | 50.98 seconds |
| Started | Oct 03 08:32:28 AM UTC 24 |
| Finished | Oct 03 08:33:20 AM UTC 24 |
| Peak memory | 287604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2880741749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c trl_rw_evict_all_en.2880741749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.2825748951 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 28105800 ps |
| CPU time | 162.32 seconds |
| Started | Oct 03 08:31:15 AM UTC 24 |
| Finished | Oct 03 08:34:00 AM UTC 24 |
| Peak memory | 287376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825748951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2825748951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.2855982826 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1525924600 ps |
| CPU time | 162.98 seconds |
| Started | Oct 03 08:31:29 AM UTC 24 |
| Finished | Oct 03 08:34:15 AM UTC 24 |
| Peak memory | 275388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2855982826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.2855982826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.3175307780 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 134175800 ps |
| CPU time | 22.55 seconds |
| Started | Oct 03 08:34:51 AM UTC 24 |
| Finished | Oct 03 08:35:15 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175307780 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.3175307780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.39429619 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 13464000 ps |
| CPU time | 18.76 seconds |
| Started | Oct 03 08:34:29 AM UTC 24 |
| Finished | Oct 03 08:34:49 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39429619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.39429619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1977030701 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 10068501200 ps |
| CPU time | 73.62 seconds |
| Started | Oct 03 08:34:50 AM UTC 24 |
| Finished | Oct 03 08:36:05 AM UTC 24 |
| Peak memory | 283508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1977030701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1977030701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.3358717111 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 16318600 ps |
| CPU time | 25.49 seconds |
| Started | Oct 03 08:34:45 AM UTC 24 |
| Finished | Oct 03 08:35:11 AM UTC 24 |
| Peak memory | 275268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3358717111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3358717111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.2357206263 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 40127783200 ps |
| CPU time | 836.47 seconds |
| Started | Oct 03 08:33:23 AM UTC 24 |
| Finished | Oct 03 08:47:29 AM UTC 24 |
| Peak memory | 275236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357206263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_res et.2357206263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.1380682564 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 12022863100 ps |
| CPU time | 257.15 seconds |
| Started | Oct 03 08:33:22 AM UTC 24 |
| Finished | Oct 03 08:37:43 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380682564 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.1380682564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.2982109815 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4750793000 ps |
| CPU time | 204.25 seconds |
| Started | Oct 03 08:33:32 AM UTC 24 |
| Finished | Oct 03 08:36:59 AM UTC 24 |
| Peak memory | 293772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982109815 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.2982109815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2629834752 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 5952954900 ps |
| CPU time | 192.65 seconds |
| Started | Oct 03 08:34:01 AM UTC 24 |
| Finished | Oct 03 08:37:17 AM UTC 24 |
| Peak memory | 301860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2629834752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 19.flash_ctrl_intr_rd_slow_flash.2629834752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.1269072798 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 5494347400 ps |
| CPU time | 86.89 seconds |
| Started | Oct 03 08:33:25 AM UTC 24 |
| Finished | Oct 03 08:34:54 AM UTC 24 |
| Peak memory | 270916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269072798 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1269072798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.3853968384 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 20662000 ps |
| CPU time | 21.63 seconds |
| Started | Oct 03 08:34:32 AM UTC 24 |
| Finished | Oct 03 08:34:55 AM UTC 24 |
| Peak memory | 275468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3853968384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_lcmgr_intg.3853968384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.262217286 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 191272420500 ps |
| CPU time | 952.15 seconds |
| Started | Oct 03 08:33:24 AM UTC 24 |
| Finished | Oct 03 08:49:27 AM UTC 24 |
| Peak memory | 283348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=262217286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 19.flash_ctrl_mp_regions.262217286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.4024267748 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 153530500 ps |
| CPU time | 177.53 seconds |
| Started | Oct 03 08:33:23 AM UTC 24 |
| Finished | Oct 03 08:36:23 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024267748 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.4024267748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.1356670975 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1371608900 ps |
| CPU time | 489.12 seconds |
| Started | Oct 03 08:33:22 AM UTC 24 |
| Finished | Oct 03 08:41:38 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356670975 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1356670975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.2728891665 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 27429300 ps |
| CPU time | 18.2 seconds |
| Started | Oct 03 08:34:08 AM UTC 24 |
| Finished | Oct 03 08:34:28 AM UTC 24 |
| Peak memory | 271096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728891665 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.2728891665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.1402149316 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 172510700 ps |
| CPU time | 1095.71 seconds |
| Started | Oct 03 08:33:22 AM UTC 24 |
| Finished | Oct 03 08:51:50 AM UTC 24 |
| Peak memory | 295756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402149316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1402149316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.1367462776 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 440902500 ps |
| CPU time | 51.24 seconds |
| Started | Oct 03 08:34:24 AM UTC 24 |
| Finished | Oct 03 08:35:17 AM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367462776 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.1367462776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.2905032637 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 876501000 ps |
| CPU time | 95.44 seconds |
| Started | Oct 03 08:33:30 AM UTC 24 |
| Finished | Oct 03 08:35:07 AM UTC 24 |
| Peak memory | 308444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2905032637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.2905032637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.888216328 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 13812774800 ps |
| CPU time | 490.69 seconds |
| Started | Oct 03 08:33:32 AM UTC 24 |
| Finished | Oct 03 08:41:49 AM UTC 24 |
| Peak memory | 331040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888216328 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.888216328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.4052091458 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 44270700 ps |
| CPU time | 49.6 seconds |
| Started | Oct 03 08:34:15 AM UTC 24 |
| Finished | Oct 03 08:35:06 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4052091458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c trl_rw_evict_all_en.4052091458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.3935703399 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 16726507900 ps |
| CPU time | 123.96 seconds |
| Started | Oct 03 08:34:28 AM UTC 24 |
| Finished | Oct 03 08:36:34 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935703399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3935703399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.2454234116 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 87694500 ps |
| CPU time | 225.24 seconds |
| Started | Oct 03 08:33:09 AM UTC 24 |
| Finished | Oct 03 08:36:58 AM UTC 24 |
| Peak memory | 289420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454234116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.2454234116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.2377735314 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4748132700 ps |
| CPU time | 205.23 seconds |
| Started | Oct 03 08:33:26 AM UTC 24 |
| Finished | Oct 03 08:36:55 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2377735314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.2377735314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.786225700 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 76649200 ps |
| CPU time | 20.41 seconds |
| Started | Oct 03 07:43:28 AM UTC 24 |
| Finished | Oct 03 07:43:50 AM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786225700 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.786225700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.665302011 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 38816900 ps |
| CPU time | 26.21 seconds |
| Started | Oct 03 07:43:09 AM UTC 24 |
| Finished | Oct 03 07:43:37 AM UTC 24 |
| Peak memory | 273048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665302011 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.665302011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.915976422 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 43559400 ps |
| CPU time | 26.85 seconds |
| Started | Oct 03 07:42:40 AM UTC 24 |
| Finished | Oct 03 07:43:08 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915976422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.915976422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.1947917389 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 57655900 ps |
| CPU time | 32.45 seconds |
| Started | Oct 03 07:42:16 AM UTC 24 |
| Finished | Oct 03 07:42:49 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1947917389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c trl_disable.1947917389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.1532184532 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 8874149000 ps |
| CPU time | 571.06 seconds |
| Started | Oct 03 07:40:39 AM UTC 24 |
| Finished | Oct 03 07:50:17 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532184532 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1532184532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.2529893675 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1467566500 ps |
| CPU time | 1341.1 seconds |
| Started | Oct 03 07:40:54 AM UTC 24 |
| Finished | Oct 03 08:03:31 AM UTC 24 |
| Peak memory | 283604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529893675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2529893675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.1122742893 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1703219100 ps |
| CPU time | 67.53 seconds |
| Started | Oct 03 07:43:02 AM UTC 24 |
| Finished | Oct 03 07:44:11 AM UTC 24 |
| Peak memory | 275236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122742 893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_f s_sup.1122742893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.2814893515 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 99777602800 ps |
| CPU time | 4143.46 seconds |
| Started | Oct 03 07:40:51 AM UTC 24 |
| Finished | Oct 03 08:50:44 AM UTC 24 |
| Peak memory | 277820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814893515 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.2814893515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.3624431974 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 98248900 ps |
| CPU time | 55.74 seconds |
| Started | Oct 03 07:43:28 AM UTC 24 |
| Finished | Oct 03 07:44:26 AM UTC 24 |
| Peak memory | 277368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362443197 4 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ho st_addr_infection.3624431974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.2051408716 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 903392809300 ps |
| CPU time | 2736.78 seconds |
| Started | Oct 03 07:40:42 AM UTC 24 |
| Finished | Oct 03 08:26:49 AM UTC 24 |
| Peak memory | 277996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051408716 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.2051408716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.3247765472 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 62921000 ps |
| CPU time | 122.46 seconds |
| Started | Oct 03 07:40:32 AM UTC 24 |
| Finished | Oct 03 07:42:37 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247765472 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3247765472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.1885883548 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 10011587900 ps |
| CPU time | 339.45 seconds |
| Started | Oct 03 07:43:23 AM UTC 24 |
| Finished | Oct 03 07:49:08 AM UTC 24 |
| Peak memory | 344828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1885883548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.1885883548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.651437044 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 15011200 ps |
| CPU time | 22.08 seconds |
| Started | Oct 03 07:43:23 AM UTC 24 |
| Finished | Oct 03 07:43:47 AM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=651437044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .flash_ctrl_hw_read_seed_err.651437044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.603920444 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 501973227800 ps |
| CPU time | 1865.24 seconds |
| Started | Oct 03 07:40:39 AM UTC 24 |
| Finished | Oct 03 08:12:05 AM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603920444 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.603920444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.3536548330 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 80138748300 ps |
| CPU time | 848.03 seconds |
| Started | Oct 03 07:40:39 AM UTC 24 |
| Finished | Oct 03 07:54:57 AM UTC 24 |
| Peak memory | 274972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536548330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.3536548330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.381119245 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3294577900 ps |
| CPU time | 257.51 seconds |
| Started | Oct 03 07:40:39 AM UTC 24 |
| Finished | Oct 03 07:45:00 AM UTC 24 |
| Peak memory | 275080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381119245 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.381119245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3292823753 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2975607900 ps |
| CPU time | 562.81 seconds |
| Started | Oct 03 07:41:47 AM UTC 24 |
| Finished | Oct 03 07:51:17 AM UTC 24 |
| Peak memory | 330808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3292823753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integr ity.3292823753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.4150344138 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 579287800 ps |
| CPU time | 149.16 seconds |
| Started | Oct 03 07:41:53 AM UTC 24 |
| Finished | Oct 03 07:44:25 AM UTC 24 |
| Peak memory | 306100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150344138 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.4150344138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2891404420 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 15763296200 ps |
| CPU time | 177.29 seconds |
| Started | Oct 03 07:41:55 AM UTC 24 |
| Finished | Oct 03 07:44:55 AM UTC 24 |
| Peak memory | 304040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2891404420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_intr_rd_slow_flash.2891404420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.673581278 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7841810400 ps |
| CPU time | 90.69 seconds |
| Started | Oct 03 07:41:55 AM UTC 24 |
| Finished | Oct 03 07:43:28 AM UTC 24 |
| Peak memory | 271152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673581278 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.673581278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3234115482 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 305046229400 ps |
| CPU time | 530.97 seconds |
| Started | Oct 03 07:41:57 AM UTC 24 |
| Finished | Oct 03 07:50:55 AM UTC 24 |
| Peak memory | 271560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234115482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.3234115482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.1650831211 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3429730700 ps |
| CPU time | 113.54 seconds |
| Started | Oct 03 07:40:57 AM UTC 24 |
| Finished | Oct 03 07:42:53 AM UTC 24 |
| Peak memory | 270920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650831211 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.1650831211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.2169033730 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 30018100 ps |
| CPU time | 24.92 seconds |
| Started | Oct 03 07:43:22 AM UTC 24 |
| Finished | Oct 03 07:43:48 AM UTC 24 |
| Peak memory | 273220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2169033730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_lcmgr_intg.2169033730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.314243706 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 45563931400 ps |
| CPU time | 438.88 seconds |
| Started | Oct 03 07:40:42 AM UTC 24 |
| Finished | Oct 03 07:48:07 AM UTC 24 |
| Peak memory | 283328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=314243706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_mp_regions.314243706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.218051685 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1916535600 ps |
| CPU time | 205.22 seconds |
| Started | Oct 03 07:41:44 AM UTC 24 |
| Finished | Oct 03 07:45:13 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=218051685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_oversize_error.218051685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.708682792 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 122656400 ps |
| CPU time | 213.72 seconds |
| Started | Oct 03 07:40:37 AM UTC 24 |
| Finished | Oct 03 07:44:15 AM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708682792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.708682792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.4012198552 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 666709300 ps |
| CPU time | 29.71 seconds |
| Started | Oct 03 07:43:02 AM UTC 24 |
| Finished | Oct 03 07:43:33 AM UTC 24 |
| Peak memory | 273604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=4012198552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.4012198552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.2591128605 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4078087700 ps |
| CPU time | 185.1 seconds |
| Started | Oct 03 07:41:58 AM UTC 24 |
| Finished | Oct 03 07:45:06 AM UTC 24 |
| Peak memory | 271356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591128605 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.2591128605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.2140013096 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 76968400 ps |
| CPU time | 1316.49 seconds |
| Started | Oct 03 07:40:26 AM UTC 24 |
| Finished | Oct 03 08:02:39 AM UTC 24 |
| Peak memory | 293644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140013096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2140013096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1894054805 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 702203200 ps |
| CPU time | 221.74 seconds |
| Started | Oct 03 07:40:35 AM UTC 24 |
| Finished | Oct 03 07:44:21 AM UTC 24 |
| Peak memory | 273092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894054805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1894054805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3906596672 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 137681100 ps |
| CPU time | 48.15 seconds |
| Started | Oct 03 07:42:40 AM UTC 24 |
| Finished | Oct 03 07:43:30 AM UTC 24 |
| Peak memory | 287552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390659667 2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.3906596672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.4048062275 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 118213000 ps |
| CPU time | 47.53 seconds |
| Started | Oct 03 07:42:14 AM UTC 24 |
| Finished | Oct 03 07:43:03 AM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048062275 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.4048062275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.3453386618 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 23368300 ps |
| CPU time | 32.6 seconds |
| Started | Oct 03 07:41:22 AM UTC 24 |
| Finished | Oct 03 07:41:56 AM UTC 24 |
| Peak memory | 275508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3453386618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_read_word_sweep_derr.3453386618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3254721386 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 59818500 ps |
| CPU time | 33.52 seconds |
| Started | Oct 03 07:41:17 AM UTC 24 |
| Finished | Oct 03 07:41:52 AM UTC 24 |
| Peak memory | 275316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254721386 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.3254721386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2432231496 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 159306048600 ps |
| CPU time | 1088.28 seconds |
| Started | Oct 03 07:43:14 AM UTC 24 |
| Finished | Oct 03 08:01:35 AM UTC 24 |
| Peak memory | 273228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30 0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2432231496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. flash_ctrl_rma_err.2432231496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2666289360 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 639718800 ps |
| CPU time | 122.34 seconds |
| Started | Oct 03 07:41:09 AM UTC 24 |
| Finished | Oct 03 07:43:13 AM UTC 24 |
| Peak memory | 291868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2666289360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.2666289360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.1852556755 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 7354467800 ps |
| CPU time | 180.53 seconds |
| Started | Oct 03 07:41:23 AM UTC 24 |
| Finished | Oct 03 07:44:27 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852556755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1852556755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.3017780108 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2867004700 ps |
| CPU time | 147.24 seconds |
| Started | Oct 03 07:41:17 AM UTC 24 |
| Finished | Oct 03 07:43:47 AM UTC 24 |
| Peak memory | 306172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3017780108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash _ctrl_ro_serr.3017780108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.3046749289 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 5064937300 ps |
| CPU time | 305.9 seconds |
| Started | Oct 03 07:41:31 AM UTC 24 |
| Finished | Oct 03 07:46:42 AM UTC 24 |
| Peak memory | 297976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3046749289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 2.flash_ctrl_rw_derr.3046749289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.237813024 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 28615700 ps |
| CPU time | 59.11 seconds |
| Started | Oct 03 07:42:00 AM UTC 24 |
| Finished | Oct 03 07:43:01 AM UTC 24 |
| Peak memory | 287668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237813024 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict.237813024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.1837281938 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 37338200 ps |
| CPU time | 45.25 seconds |
| Started | Oct 03 07:42:14 AM UTC 24 |
| Finished | Oct 03 07:43:01 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1837281938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_rw_evict_all_en.1837281938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.888374974 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 7588412400 ps |
| CPU time | 228.69 seconds |
| Started | Oct 03 07:41:18 AM UTC 24 |
| Finished | Oct 03 07:45:11 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=888374974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.888374974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.4148653335 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3941309500 ps |
| CPU time | 7410.04 seconds |
| Started | Oct 03 07:42:21 AM UTC 24 |
| Finished | Oct 03 09:47:20 AM UTC 24 |
| Peak memory | 312164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148653335 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.4148653335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.676097989 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2392129100 ps |
| CPU time | 98.38 seconds |
| Started | Oct 03 07:42:39 AM UTC 24 |
| Finished | Oct 03 07:44:19 AM UTC 24 |
| Peak memory | 275160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676097989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.676097989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.2595006985 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3038210500 ps |
| CPU time | 74.15 seconds |
| Started | Oct 03 07:41:21 AM UTC 24 |
| Finished | Oct 03 07:42:37 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259 5006985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ser r_address.2595006985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.4098746368 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 424955400 ps |
| CPU time | 77.99 seconds |
| Started | Oct 03 07:41:19 AM UTC 24 |
| Finished | Oct 03 07:42:39 AM UTC 24 |
| Peak memory | 285964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40 98746368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se rr_counter.4098746368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.1365869459 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 69612100 ps |
| CPU time | 259.32 seconds |
| Started | Oct 03 07:40:23 AM UTC 24 |
| Finished | Oct 03 07:44:46 AM UTC 24 |
| Peak memory | 287560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365869459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.1365869459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.366907065 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 16453200 ps |
| CPU time | 46.62 seconds |
| Started | Oct 03 07:40:24 AM UTC 24 |
| Finished | Oct 03 07:41:12 AM UTC 24 |
| Peak memory | 270924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366907065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.366907065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.884663860 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 581206300 ps |
| CPU time | 1478.36 seconds |
| Started | Oct 03 07:42:39 AM UTC 24 |
| Finished | Oct 03 08:07:34 AM UTC 24 |
| Peak memory | 301772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884663860 -assert nopostproc +UVM_TESTNA ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.884663860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.2835422147 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 37027300 ps |
| CPU time | 44.37 seconds |
| Started | Oct 03 07:40:31 AM UTC 24 |
| Finished | Oct 03 07:41:17 AM UTC 24 |
| Peak memory | 272900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835422147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.2835422147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1018686846 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 25528113600 ps |
| CPU time | 355.65 seconds |
| Started | Oct 03 07:41:05 AM UTC 24 |
| Finished | Oct 03 07:47:06 AM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1018686846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.1018686846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.1087127684 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 30960700 ps |
| CPU time | 24.77 seconds |
| Started | Oct 03 08:35:21 AM UTC 24 |
| Finished | Oct 03 08:35:47 AM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087127684 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.1087127684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.3924041656 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 57069800 ps |
| CPU time | 27.1 seconds |
| Started | Oct 03 08:35:18 AM UTC 24 |
| Finished | Oct 03 08:35:47 AM UTC 24 |
| Peak memory | 284616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924041656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.3924041656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.4269387009 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 13074000 ps |
| CPU time | 36.18 seconds |
| Started | Oct 03 08:35:14 AM UTC 24 |
| Finished | Oct 03 08:35:52 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4269387009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ ctrl_disable.4269387009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.95201129 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 7921098000 ps |
| CPU time | 162.79 seconds |
| Started | Oct 03 08:34:55 AM UTC 24 |
| Finished | Oct 03 08:37:41 AM UTC 24 |
| Peak memory | 273036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95201129 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.95201129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.1787533155 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 2114165300 ps |
| CPU time | 236.64 seconds |
| Started | Oct 03 08:35:05 AM UTC 24 |
| Finished | Oct 03 08:39:05 AM UTC 24 |
| Peak memory | 293996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787533155 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.1787533155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3961393710 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 6065626200 ps |
| CPU time | 146.65 seconds |
| Started | Oct 03 08:35:07 AM UTC 24 |
| Finished | Oct 03 08:37:36 AM UTC 24 |
| Peak memory | 293636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3961393710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.flash_ctrl_intr_rd_slow_flash.3961393710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.400525440 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 420050900 ps |
| CPU time | 154.32 seconds |
| Started | Oct 03 08:35:05 AM UTC 24 |
| Finished | Oct 03 08:37:41 AM UTC 24 |
| Peak memory | 275252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400525440 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.400525440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.1600143710 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 7378983700 ps |
| CPU time | 164.96 seconds |
| Started | Oct 03 08:35:08 AM UTC 24 |
| Finished | Oct 03 08:37:56 AM UTC 24 |
| Peak memory | 271160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600143710 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.1600143710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.2171663436 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 81347200 ps |
| CPU time | 61.2 seconds |
| Started | Oct 03 08:35:10 AM UTC 24 |
| Finished | Oct 03 08:36:13 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171663436 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.2171663436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.3181155865 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 42993700 ps |
| CPU time | 34.32 seconds |
| Started | Oct 03 08:35:12 AM UTC 24 |
| Finished | Oct 03 08:35:48 AM UTC 24 |
| Peak memory | 287804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3181155865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_c trl_rw_evict_all_en.3181155865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.3253718228 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1634285800 ps |
| CPU time | 69.88 seconds |
| Started | Oct 03 08:35:16 AM UTC 24 |
| Finished | Oct 03 08:36:28 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253718228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3253718228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.411758642 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 26925000 ps |
| CPU time | 161.52 seconds |
| Started | Oct 03 08:34:55 AM UTC 24 |
| Finished | Oct 03 08:37:39 AM UTC 24 |
| Peak memory | 287372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411758642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.411758642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.1078995710 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 37446200 ps |
| CPU time | 23.94 seconds |
| Started | Oct 03 08:36:35 AM UTC 24 |
| Finished | Oct 03 08:37:01 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078995710 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.1078995710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.2468499277 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 14788600 ps |
| CPU time | 25.03 seconds |
| Started | Oct 03 08:36:29 AM UTC 24 |
| Finished | Oct 03 08:36:55 AM UTC 24 |
| Peak memory | 294920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468499277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.2468499277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.741449913 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 2807017800 ps |
| CPU time | 134.47 seconds |
| Started | Oct 03 08:35:48 AM UTC 24 |
| Finished | Oct 03 08:38:05 AM UTC 24 |
| Peak memory | 273032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741449913 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.741449913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.1520303155 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3920830300 ps |
| CPU time | 137.02 seconds |
| Started | Oct 03 08:35:48 AM UTC 24 |
| Finished | Oct 03 08:38:07 AM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520303155 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.1520303155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3469493672 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 5921095600 ps |
| CPU time | 162.73 seconds |
| Started | Oct 03 08:35:49 AM UTC 24 |
| Finished | Oct 03 08:38:34 AM UTC 24 |
| Peak memory | 305964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3469493672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.flash_ctrl_intr_rd_slow_flash.3469493672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.4014401268 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 93167200 ps |
| CPU time | 182.89 seconds |
| Started | Oct 03 08:35:48 AM UTC 24 |
| Finished | Oct 03 08:38:53 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014401268 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.4014401268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.1391831069 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 19799700 ps |
| CPU time | 23.2 seconds |
| Started | Oct 03 08:35:53 AM UTC 24 |
| Finished | Oct 03 08:36:17 AM UTC 24 |
| Peak memory | 275388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391831069 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.1391831069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.610011980 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 284540100 ps |
| CPU time | 54.62 seconds |
| Started | Oct 03 08:36:06 AM UTC 24 |
| Finished | Oct 03 08:37:02 AM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610011980 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.610011980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.797502535 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 42780800 ps |
| CPU time | 63.25 seconds |
| Started | Oct 03 08:36:14 AM UTC 24 |
| Finished | Oct 03 08:37:19 AM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=797502535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ct rl_rw_evict_all_en.797502535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.3102350914 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 1330206600 ps |
| CPU time | 95.64 seconds |
| Started | Oct 03 08:36:23 AM UTC 24 |
| Finished | Oct 03 08:38:01 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102350914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3102350914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.2468034988 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 45552200 ps |
| CPU time | 173.53 seconds |
| Started | Oct 03 08:35:36 AM UTC 24 |
| Finished | Oct 03 08:38:33 AM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468034988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2468034988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.778400113 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 149116300 ps |
| CPU time | 15.96 seconds |
| Started | Oct 03 08:37:25 AM UTC 24 |
| Finished | Oct 03 08:37:42 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778400113 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.778400113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.1915062781 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 29601800 ps |
| CPU time | 26.84 seconds |
| Started | Oct 03 08:37:16 AM UTC 24 |
| Finished | Oct 03 08:37:44 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915062781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.1915062781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.1508474052 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 12305100 ps |
| CPU time | 34.75 seconds |
| Started | Oct 03 08:37:04 AM UTC 24 |
| Finished | Oct 03 08:37:40 AM UTC 24 |
| Peak memory | 285460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1508474052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ ctrl_disable.1508474052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.2403333991 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 13561786200 ps |
| CPU time | 128.03 seconds |
| Started | Oct 03 08:36:55 AM UTC 24 |
| Finished | Oct 03 08:39:06 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403333991 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.2403333991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.1060942838 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 1266557700 ps |
| CPU time | 139.06 seconds |
| Started | Oct 03 08:36:57 AM UTC 24 |
| Finished | Oct 03 08:39:19 AM UTC 24 |
| Peak memory | 306096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060942838 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.1060942838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.4131736464 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 23294001600 ps |
| CPU time | 284.88 seconds |
| Started | Oct 03 08:36:58 AM UTC 24 |
| Finished | Oct 03 08:41:48 AM UTC 24 |
| Peak memory | 301800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4131736464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 22.flash_ctrl_intr_rd_slow_flash.4131736464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.4098614348 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 135763200 ps |
| CPU time | 171.63 seconds |
| Started | Oct 03 08:36:56 AM UTC 24 |
| Finished | Oct 03 08:39:51 AM UTC 24 |
| Peak memory | 274976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098614348 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.4098614348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.350909227 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1306046100 ps |
| CPU time | 81.92 seconds |
| Started | Oct 03 08:37:01 AM UTC 24 |
| Finished | Oct 03 08:38:24 AM UTC 24 |
| Peak memory | 271360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350909227 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.350909227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.1203136694 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 53139200 ps |
| CPU time | 41.94 seconds |
| Started | Oct 03 08:37:02 AM UTC 24 |
| Finished | Oct 03 08:37:45 AM UTC 24 |
| Peak memory | 287872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203136694 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.1203136694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.1498337396 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 51555000 ps |
| CPU time | 43.38 seconds |
| Started | Oct 03 08:37:03 AM UTC 24 |
| Finished | Oct 03 08:37:48 AM UTC 24 |
| Peak memory | 287604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1498337396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_c trl_rw_evict_all_en.1498337396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.910155678 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3910061200 ps |
| CPU time | 100.09 seconds |
| Started | Oct 03 08:37:08 AM UTC 24 |
| Finished | Oct 03 08:38:50 AM UTC 24 |
| Peak memory | 275156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910155678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.910155678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.190347346 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 34807200 ps |
| CPU time | 141.31 seconds |
| Started | Oct 03 08:36:43 AM UTC 24 |
| Finished | Oct 03 08:39:07 AM UTC 24 |
| Peak memory | 287360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190347346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.190347346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.1386486074 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 333192600 ps |
| CPU time | 16.54 seconds |
| Started | Oct 03 08:37:44 AM UTC 24 |
| Finished | Oct 03 08:38:02 AM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386486074 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.1386486074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.3685721172 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 14441700 ps |
| CPU time | 29.02 seconds |
| Started | Oct 03 08:37:43 AM UTC 24 |
| Finished | Oct 03 08:38:13 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685721172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3685721172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.4270616633 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 4321723700 ps |
| CPU time | 144.72 seconds |
| Started | Oct 03 08:37:25 AM UTC 24 |
| Finished | Oct 03 08:39:53 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270616633 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.4270616633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.276872600 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 13191619600 ps |
| CPU time | 219.34 seconds |
| Started | Oct 03 08:37:37 AM UTC 24 |
| Finished | Oct 03 08:41:20 AM UTC 24 |
| Peak memory | 305960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=276872600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 23.flash_ctrl_intr_rd_slow_flash.276872600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.2629649151 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 41832900 ps |
| CPU time | 199.45 seconds |
| Started | Oct 03 08:37:27 AM UTC 24 |
| Finished | Oct 03 08:40:49 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629649151 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.2629649151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.324522523 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 7581143900 ps |
| CPU time | 192.87 seconds |
| Started | Oct 03 08:37:40 AM UTC 24 |
| Finished | Oct 03 08:40:56 AM UTC 24 |
| Peak memory | 275264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324522523 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.324522523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.2639039183 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 46586000 ps |
| CPU time | 32.91 seconds |
| Started | Oct 03 08:37:40 AM UTC 24 |
| Finished | Oct 03 08:38:14 AM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639039183 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.2639039183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.3452063901 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 43750700 ps |
| CPU time | 33.28 seconds |
| Started | Oct 03 08:37:41 AM UTC 24 |
| Finished | Oct 03 08:38:16 AM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3452063901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c trl_rw_evict_all_en.3452063901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.2182094831 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1128233600 ps |
| CPU time | 96.74 seconds |
| Started | Oct 03 08:37:43 AM UTC 24 |
| Finished | Oct 03 08:39:21 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182094831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2182094831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.2523319661 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 51216500 ps |
| CPU time | 235.4 seconds |
| Started | Oct 03 08:37:25 AM UTC 24 |
| Finished | Oct 03 08:41:25 AM UTC 24 |
| Peak memory | 287376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523319661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2523319661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.1698439104 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 55206500 ps |
| CPU time | 22.76 seconds |
| Started | Oct 03 08:38:14 AM UTC 24 |
| Finished | Oct 03 08:38:38 AM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698439104 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.1698439104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.3648848611 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 13783500 ps |
| CPU time | 17.86 seconds |
| Started | Oct 03 08:38:13 AM UTC 24 |
| Finished | Oct 03 08:38:32 AM UTC 24 |
| Peak memory | 294924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648848611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3648848611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.248233029 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 31708800 ps |
| CPU time | 30.71 seconds |
| Started | Oct 03 08:38:06 AM UTC 24 |
| Finished | Oct 03 08:38:38 AM UTC 24 |
| Peak memory | 285580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=248233029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_disable.248233029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.2756731127 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2911303000 ps |
| CPU time | 244.79 seconds |
| Started | Oct 03 08:37:45 AM UTC 24 |
| Finished | Oct 03 08:41:54 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756731127 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.2756731127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.3228295755 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 6895041700 ps |
| CPU time | 225.22 seconds |
| Started | Oct 03 08:37:48 AM UTC 24 |
| Finished | Oct 03 08:41:37 AM UTC 24 |
| Peak memory | 302192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228295755 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.3228295755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3908569461 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 24795550100 ps |
| CPU time | 263.25 seconds |
| Started | Oct 03 08:37:57 AM UTC 24 |
| Finished | Oct 03 08:42:23 AM UTC 24 |
| Peak memory | 303852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3908569461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 24.flash_ctrl_intr_rd_slow_flash.3908569461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.2175609562 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 135001600 ps |
| CPU time | 242.72 seconds |
| Started | Oct 03 08:37:46 AM UTC 24 |
| Finished | Oct 03 08:41:53 AM UTC 24 |
| Peak memory | 271264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175609562 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.2175609562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.3338195812 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 11425069800 ps |
| CPU time | 204.65 seconds |
| Started | Oct 03 08:37:57 AM UTC 24 |
| Finished | Oct 03 08:41:25 AM UTC 24 |
| Peak memory | 271164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338195812 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.3338195812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.899135638 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 32958600 ps |
| CPU time | 37.62 seconds |
| Started | Oct 03 08:38:02 AM UTC 24 |
| Finished | Oct 03 08:38:41 AM UTC 24 |
| Peak memory | 287684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899135638 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.899135638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.3088660198 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 74235700 ps |
| CPU time | 39.26 seconds |
| Started | Oct 03 08:38:03 AM UTC 24 |
| Finished | Oct 03 08:38:44 AM UTC 24 |
| Peak memory | 287712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3088660198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c trl_rw_evict_all_en.3088660198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.1465769348 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1544219800 ps |
| CPU time | 74.03 seconds |
| Started | Oct 03 08:38:08 AM UTC 24 |
| Finished | Oct 03 08:39:24 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465769348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.1465769348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.3770869054 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 69392100 ps |
| CPU time | 150.28 seconds |
| Started | Oct 03 08:37:45 AM UTC 24 |
| Finished | Oct 03 08:40:18 AM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770869054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3770869054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.2389890078 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 103841800 ps |
| CPU time | 20.18 seconds |
| Started | Oct 03 08:38:54 AM UTC 24 |
| Finished | Oct 03 08:39:15 AM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389890078 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.2389890078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.3556058004 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 23232800 ps |
| CPU time | 24.66 seconds |
| Started | Oct 03 08:38:52 AM UTC 24 |
| Finished | Oct 03 08:39:18 AM UTC 24 |
| Peak memory | 284616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556058004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.3556058004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.2201210154 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 17141600 ps |
| CPU time | 25.47 seconds |
| Started | Oct 03 08:38:41 AM UTC 24 |
| Finished | Oct 03 08:39:08 AM UTC 24 |
| Peak memory | 285436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2201210154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ ctrl_disable.2201210154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.3356290728 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2688812600 ps |
| CPU time | 113.43 seconds |
| Started | Oct 03 08:38:17 AM UTC 24 |
| Finished | Oct 03 08:40:12 AM UTC 24 |
| Peak memory | 270988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356290728 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.3356290728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.1218586296 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1901440900 ps |
| CPU time | 127.93 seconds |
| Started | Oct 03 08:38:33 AM UTC 24 |
| Finished | Oct 03 08:40:43 AM UTC 24 |
| Peak memory | 306092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218586296 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.1218586296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1170606192 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 23581918100 ps |
| CPU time | 226.48 seconds |
| Started | Oct 03 08:38:34 AM UTC 24 |
| Finished | Oct 03 08:42:24 AM UTC 24 |
| Peak memory | 303876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1170606192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.flash_ctrl_intr_rd_slow_flash.1170606192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.2193810607 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 63680200 ps |
| CPU time | 179.34 seconds |
| Started | Oct 03 08:38:26 AM UTC 24 |
| Finished | Oct 03 08:41:28 AM UTC 24 |
| Peak memory | 271604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193810607 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.2193810607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.553161757 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 83251500 ps |
| CPU time | 29.66 seconds |
| Started | Oct 03 08:38:35 AM UTC 24 |
| Finished | Oct 03 08:39:06 AM UTC 24 |
| Peak memory | 271360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553161757 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.553161757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.2183269824 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 73697200 ps |
| CPU time | 44.57 seconds |
| Started | Oct 03 08:38:39 AM UTC 24 |
| Finished | Oct 03 08:39:25 AM UTC 24 |
| Peak memory | 281528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183269824 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.2183269824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.3997272778 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 59043800 ps |
| CPU time | 40.07 seconds |
| Started | Oct 03 08:38:39 AM UTC 24 |
| Finished | Oct 03 08:39:21 AM UTC 24 |
| Peak memory | 287704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3997272778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c trl_rw_evict_all_en.3997272778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.2882017108 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 385707100 ps |
| CPU time | 58.27 seconds |
| Started | Oct 03 08:38:45 AM UTC 24 |
| Finished | Oct 03 08:39:45 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882017108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.2882017108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.2031581879 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 117638700 ps |
| CPU time | 309.6 seconds |
| Started | Oct 03 08:38:16 AM UTC 24 |
| Finished | Oct 03 08:43:30 AM UTC 24 |
| Peak memory | 289608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031581879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2031581879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.1040539656 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 66637400 ps |
| CPU time | 24.49 seconds |
| Started | Oct 03 08:39:27 AM UTC 24 |
| Finished | Oct 03 08:39:52 AM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040539656 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.1040539656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.3898765743 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 23249200 ps |
| CPU time | 27.74 seconds |
| Started | Oct 03 08:39:25 AM UTC 24 |
| Finished | Oct 03 08:39:54 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898765743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.3898765743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.1718087731 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 35896400 ps |
| CPU time | 42.7 seconds |
| Started | Oct 03 08:39:21 AM UTC 24 |
| Finished | Oct 03 08:40:05 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1718087731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ ctrl_disable.1718087731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.407337418 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 54602331200 ps |
| CPU time | 124.18 seconds |
| Started | Oct 03 08:39:07 AM UTC 24 |
| Finished | Oct 03 08:41:14 AM UTC 24 |
| Peak memory | 273032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407337418 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.407337418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.1677908648 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 14271014200 ps |
| CPU time | 199.23 seconds |
| Started | Oct 03 08:39:08 AM UTC 24 |
| Finished | Oct 03 08:42:31 AM UTC 24 |
| Peak memory | 293780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677908648 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.1677908648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.3105799483 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 12580512600 ps |
| CPU time | 275.73 seconds |
| Started | Oct 03 08:39:10 AM UTC 24 |
| Finished | Oct 03 08:43:49 AM UTC 24 |
| Peak memory | 303912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3105799483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.flash_ctrl_intr_rd_slow_flash.3105799483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.2558431941 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 39015200 ps |
| CPU time | 157.29 seconds |
| Started | Oct 03 08:39:07 AM UTC 24 |
| Finished | Oct 03 08:41:47 AM UTC 24 |
| Peak memory | 275488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558431941 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.2558431941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.2886526371 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 40646900 ps |
| CPU time | 18.63 seconds |
| Started | Oct 03 08:39:16 AM UTC 24 |
| Finished | Oct 03 08:39:36 AM UTC 24 |
| Peak memory | 271228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886526371 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.2886526371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.3089314656 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 70334100 ps |
| CPU time | 56.7 seconds |
| Started | Oct 03 08:39:19 AM UTC 24 |
| Finished | Oct 03 08:40:17 AM UTC 24 |
| Peak memory | 283776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089314656 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.3089314656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.4239107861 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 79910400 ps |
| CPU time | 39.8 seconds |
| Started | Oct 03 08:39:20 AM UTC 24 |
| Finished | Oct 03 08:40:01 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4239107861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_c trl_rw_evict_all_en.4239107861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.1581599080 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1179708600 ps |
| CPU time | 85.33 seconds |
| Started | Oct 03 08:39:22 AM UTC 24 |
| Finished | Oct 03 08:40:50 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581599080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.1581599080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.30813672 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 29486600 ps |
| CPU time | 222.97 seconds |
| Started | Oct 03 08:39:06 AM UTC 24 |
| Finished | Oct 03 08:42:53 AM UTC 24 |
| Peak memory | 287364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30813672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.30813672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.435744686 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 93468100 ps |
| CPU time | 17.24 seconds |
| Started | Oct 03 08:40:19 AM UTC 24 |
| Finished | Oct 03 08:40:38 AM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435744686 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.435744686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.972426112 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 16022100 ps |
| CPU time | 26.64 seconds |
| Started | Oct 03 08:40:18 AM UTC 24 |
| Finished | Oct 03 08:40:46 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972426112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.972426112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.2729890039 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 12792000 ps |
| CPU time | 30.88 seconds |
| Started | Oct 03 08:40:07 AM UTC 24 |
| Finished | Oct 03 08:40:39 AM UTC 24 |
| Peak memory | 285432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2729890039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ ctrl_disable.2729890039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.3045395630 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3444880000 ps |
| CPU time | 154.54 seconds |
| Started | Oct 03 08:39:46 AM UTC 24 |
| Finished | Oct 03 08:42:23 AM UTC 24 |
| Peak memory | 273032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045395630 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.3045395630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.2910906472 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 7882040400 ps |
| CPU time | 255.46 seconds |
| Started | Oct 03 08:39:52 AM UTC 24 |
| Finished | Oct 03 08:44:12 AM UTC 24 |
| Peak memory | 301904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910906472 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.2910906472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3772736857 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 6018282000 ps |
| CPU time | 165.58 seconds |
| Started | Oct 03 08:39:53 AM UTC 24 |
| Finished | Oct 03 08:42:42 AM UTC 24 |
| Peak memory | 303848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3772736857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.flash_ctrl_intr_rd_slow_flash.3772736857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.108008489 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 76135200 ps |
| CPU time | 171.13 seconds |
| Started | Oct 03 08:39:52 AM UTC 24 |
| Finished | Oct 03 08:42:46 AM UTC 24 |
| Peak memory | 271072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108008489 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.108008489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.3504315696 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2356356500 ps |
| CPU time | 200.48 seconds |
| Started | Oct 03 08:39:54 AM UTC 24 |
| Finished | Oct 03 08:43:18 AM UTC 24 |
| Peak memory | 271164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504315696 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.3504315696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.2581345973 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 28097500 ps |
| CPU time | 42.35 seconds |
| Started | Oct 03 08:39:56 AM UTC 24 |
| Finished | Oct 03 08:40:39 AM UTC 24 |
| Peak memory | 287672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581345973 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.2581345973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.2403871337 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 28057400 ps |
| CPU time | 37.05 seconds |
| Started | Oct 03 08:40:02 AM UTC 24 |
| Finished | Oct 03 08:40:40 AM UTC 24 |
| Peak memory | 285660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2403871337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_c trl_rw_evict_all_en.2403871337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.3474618802 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 9456132800 ps |
| CPU time | 105.22 seconds |
| Started | Oct 03 08:40:13 AM UTC 24 |
| Finished | Oct 03 08:42:01 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474618802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.3474618802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.1844872809 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 26001800 ps |
| CPU time | 213.15 seconds |
| Started | Oct 03 08:39:37 AM UTC 24 |
| Finished | Oct 03 08:43:13 AM UTC 24 |
| Peak memory | 289420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844872809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1844872809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.1441470802 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 316324100 ps |
| CPU time | 28.26 seconds |
| Started | Oct 03 08:40:57 AM UTC 24 |
| Finished | Oct 03 08:41:27 AM UTC 24 |
| Peak memory | 275188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441470802 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.1441470802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.4219543541 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 24891300 ps |
| CPU time | 25.82 seconds |
| Started | Oct 03 08:40:55 AM UTC 24 |
| Finished | Oct 03 08:41:22 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219543541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.4219543541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.2869587608 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 11988500 ps |
| CPU time | 31.19 seconds |
| Started | Oct 03 08:40:51 AM UTC 24 |
| Finished | Oct 03 08:41:23 AM UTC 24 |
| Peak memory | 285460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2869587608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ ctrl_disable.2869587608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.1484191605 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 16252773100 ps |
| CPU time | 144.92 seconds |
| Started | Oct 03 08:40:25 AM UTC 24 |
| Finished | Oct 03 08:42:53 AM UTC 24 |
| Peak memory | 273036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484191605 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.1484191605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.92839270 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 8943758800 ps |
| CPU time | 246.06 seconds |
| Started | Oct 03 08:40:40 AM UTC 24 |
| Finished | Oct 03 08:44:50 AM UTC 24 |
| Peak memory | 293740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92839270 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.92839270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3462005236 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 5816138800 ps |
| CPU time | 144.75 seconds |
| Started | Oct 03 08:40:41 AM UTC 24 |
| Finished | Oct 03 08:43:08 AM UTC 24 |
| Peak memory | 303808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3462005236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.flash_ctrl_intr_rd_slow_flash.3462005236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.3804924229 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 74942100 ps |
| CPU time | 160.92 seconds |
| Started | Oct 03 08:40:39 AM UTC 24 |
| Finished | Oct 03 08:43:22 AM UTC 24 |
| Peak memory | 275300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804924229 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.3804924229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.2331733021 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 19049674200 ps |
| CPU time | 166.71 seconds |
| Started | Oct 03 08:40:41 AM UTC 24 |
| Finished | Oct 03 08:43:31 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331733021 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.2331733021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.1744793775 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 30217800 ps |
| CPU time | 39.39 seconds |
| Started | Oct 03 08:40:44 AM UTC 24 |
| Finished | Oct 03 08:41:25 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744793775 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict.1744793775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.1895213842 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2898538400 ps |
| CPU time | 79.11 seconds |
| Started | Oct 03 08:40:51 AM UTC 24 |
| Finished | Oct 03 08:42:12 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895213842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.1895213842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.929335770 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 59733900 ps |
| CPU time | 131.51 seconds |
| Started | Oct 03 08:40:25 AM UTC 24 |
| Finished | Oct 03 08:42:39 AM UTC 24 |
| Peak memory | 287376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929335770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.929335770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.1460685478 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 130700800 ps |
| CPU time | 19.01 seconds |
| Started | Oct 03 08:41:38 AM UTC 24 |
| Finished | Oct 03 08:41:59 AM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460685478 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.1460685478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.3098516298 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 38852900 ps |
| CPU time | 27.67 seconds |
| Started | Oct 03 08:41:38 AM UTC 24 |
| Finished | Oct 03 08:42:08 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098516298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3098516298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.2944454002 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 84617200 ps |
| CPU time | 33.45 seconds |
| Started | Oct 03 08:41:27 AM UTC 24 |
| Finished | Oct 03 08:42:02 AM UTC 24 |
| Peak memory | 285564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2944454002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ ctrl_disable.2944454002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.1652465246 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2987928000 ps |
| CPU time | 260.91 seconds |
| Started | Oct 03 08:41:14 AM UTC 24 |
| Finished | Oct 03 08:45:39 AM UTC 24 |
| Peak memory | 275080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652465246 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.1652465246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.2693107307 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 9691217200 ps |
| CPU time | 238.21 seconds |
| Started | Oct 03 08:41:23 AM UTC 24 |
| Finished | Oct 03 08:45:25 AM UTC 24 |
| Peak memory | 301972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693107307 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.2693107307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2133399208 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 12321371400 ps |
| CPU time | 268.42 seconds |
| Started | Oct 03 08:41:24 AM UTC 24 |
| Finished | Oct 03 08:45:56 AM UTC 24 |
| Peak memory | 301804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2133399208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.flash_ctrl_intr_rd_slow_flash.2133399208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.400758428 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 350814400 ps |
| CPU time | 173.02 seconds |
| Started | Oct 03 08:41:20 AM UTC 24 |
| Finished | Oct 03 08:44:16 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400758428 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.400758428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.2040135856 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 30414200 ps |
| CPU time | 21.08 seconds |
| Started | Oct 03 08:41:26 AM UTC 24 |
| Finished | Oct 03 08:41:49 AM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040135856 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.2040135856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.3360080899 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 38944800 ps |
| CPU time | 31.98 seconds |
| Started | Oct 03 08:41:27 AM UTC 24 |
| Finished | Oct 03 08:42:00 AM UTC 24 |
| Peak memory | 287668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3360080899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c trl_rw_evict_all_en.3360080899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.65283752 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 4142207600 ps |
| CPU time | 107.52 seconds |
| Started | Oct 03 08:41:29 AM UTC 24 |
| Finished | Oct 03 08:43:19 AM UTC 24 |
| Peak memory | 275160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65283752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.65283752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.2447725963 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 142018300 ps |
| CPU time | 141.33 seconds |
| Started | Oct 03 08:41:00 AM UTC 24 |
| Finished | Oct 03 08:43:24 AM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447725963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2447725963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.4003712586 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 44637100 ps |
| CPU time | 26.18 seconds |
| Started | Oct 03 07:48:25 AM UTC 24 |
| Finished | Oct 03 07:48:52 AM UTC 24 |
| Peak memory | 275380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003712586 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.4003712586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2660963814 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 21533900 ps |
| CPU time | 17.45 seconds |
| Started | Oct 03 07:48:13 AM UTC 24 |
| Finished | Oct 03 07:48:32 AM UTC 24 |
| Peak memory | 273060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660963814 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.2660963814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.552349761 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 38582300 ps |
| CPU time | 22.82 seconds |
| Started | Oct 03 07:47:48 AM UTC 24 |
| Finished | Oct 03 07:48:12 AM UTC 24 |
| Peak memory | 294920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552349761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.552349761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.701320827 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 12861000 ps |
| CPU time | 29.02 seconds |
| Started | Oct 03 07:47:24 AM UTC 24 |
| Finished | Oct 03 07:47:54 AM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=701320827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct rl_disable.701320827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.781046236 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 4166668400 ps |
| CPU time | 699.85 seconds |
| Started | Oct 03 07:43:49 AM UTC 24 |
| Finished | Oct 03 07:55:38 AM UTC 24 |
| Peak memory | 275280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781046236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.781046236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.2784103119 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 4708790100 ps |
| CPU time | 2729.88 seconds |
| Started | Oct 03 07:44:25 AM UTC 24 |
| Finished | Oct 03 08:30:22 AM UTC 24 |
| Peak memory | 275136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784103119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.2784103119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.3712638355 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1599564900 ps |
| CPU time | 1067.46 seconds |
| Started | Oct 03 07:44:22 AM UTC 24 |
| Finished | Oct 03 08:02:21 AM UTC 24 |
| Peak memory | 285388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712638355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3712638355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.2159050870 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 132959600 ps |
| CPU time | 35.09 seconds |
| Started | Oct 03 07:44:17 AM UTC 24 |
| Finished | Oct 03 07:44:53 AM UTC 24 |
| Peak memory | 275140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 59050870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetc h_code.2159050870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.2254284713 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 901628600 ps |
| CPU time | 48.96 seconds |
| Started | Oct 03 07:47:55 AM UTC 24 |
| Finished | Oct 03 07:48:45 AM UTC 24 |
| Peak memory | 275112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254284 713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f s_sup.2254284713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.2972019289 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 324267243600 ps |
| CPU time | 2901.31 seconds |
| Started | Oct 03 07:44:20 AM UTC 24 |
| Finished | Oct 03 08:33:14 AM UTC 24 |
| Peak memory | 286372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972019289 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.2972019289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.3034788427 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 267916743700 ps |
| CPU time | 3449.12 seconds |
| Started | Oct 03 07:44:12 AM UTC 24 |
| Finished | Oct 03 08:42:18 AM UTC 24 |
| Peak memory | 277988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034788427 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.3034788427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.1139921162 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 171362600 ps |
| CPU time | 130.27 seconds |
| Started | Oct 03 07:43:34 AM UTC 24 |
| Finished | Oct 03 07:45:47 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139921162 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1139921162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3804132221 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 13704603700 ps |
| CPU time | 235.03 seconds |
| Started | Oct 03 07:43:48 AM UTC 24 |
| Finished | Oct 03 07:47:47 AM UTC 24 |
| Peak memory | 275088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804132221 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.3804132221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.705705934 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3734884400 ps |
| CPU time | 591.62 seconds |
| Started | Oct 03 07:46:30 AM UTC 24 |
| Finished | Oct 03 07:56:29 AM UTC 24 |
| Peak memory | 328736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=705705934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integrity.705705934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.1005397958 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1754995500 ps |
| CPU time | 212.32 seconds |
| Started | Oct 03 07:46:34 AM UTC 24 |
| Finished | Oct 03 07:50:10 AM UTC 24 |
| Peak memory | 301940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005397958 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.1005397958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4277687055 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 5867397500 ps |
| CPU time | 201.57 seconds |
| Started | Oct 03 07:46:43 AM UTC 24 |
| Finished | Oct 03 07:50:08 AM UTC 24 |
| Peak memory | 303776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4277687055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_intr_rd_slow_flash.4277687055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.1507633518 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 37236584400 ps |
| CPU time | 87.66 seconds |
| Started | Oct 03 07:46:41 AM UTC 24 |
| Finished | Oct 03 07:48:11 AM UTC 24 |
| Peak memory | 271152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507633518 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.1507633518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.531721309 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 20276704700 ps |
| CPU time | 293.91 seconds |
| Started | Oct 03 07:46:43 AM UTC 24 |
| Finished | Oct 03 07:51:41 AM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531721309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.531721309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.3222691646 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6213050300 ps |
| CPU time | 106.06 seconds |
| Started | Oct 03 07:44:26 AM UTC 24 |
| Finished | Oct 03 07:46:15 AM UTC 24 |
| Peak memory | 275016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222691646 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.3222691646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.1010370575 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 69154500 ps |
| CPU time | 19.82 seconds |
| Started | Oct 03 07:48:13 AM UTC 24 |
| Finished | Oct 03 07:48:34 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1010370575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_lcmgr_intg.1010370575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.3069247656 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 645964600 ps |
| CPU time | 122.61 seconds |
| Started | Oct 03 07:44:28 AM UTC 24 |
| Finished | Oct 03 07:46:33 AM UTC 24 |
| Peak memory | 270872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069247656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3069247656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.3908081345 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 23993616700 ps |
| CPU time | 363.32 seconds |
| Started | Oct 03 07:44:16 AM UTC 24 |
| Finished | Oct 03 07:50:24 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3908081345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.3908081345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.3650377572 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 4828717000 ps |
| CPU time | 170.36 seconds |
| Started | Oct 03 07:46:15 AM UTC 24 |
| Finished | Oct 03 07:49:08 AM UTC 24 |
| Peak memory | 302276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3650377572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.3650377572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.2349594250 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 39996400 ps |
| CPU time | 210.38 seconds |
| Started | Oct 03 07:43:47 AM UTC 24 |
| Finished | Oct 03 07:47:21 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349594250 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.2349594250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.155775627 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 14084800 ps |
| CPU time | 18.21 seconds |
| Started | Oct 03 07:48:09 AM UTC 24 |
| Finished | Oct 03 07:48:28 AM UTC 24 |
| Peak memory | 273480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=155775627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.155775627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.2143794207 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 80096500 ps |
| CPU time | 15.51 seconds |
| Started | Oct 03 07:46:49 AM UTC 24 |
| Finished | Oct 03 07:47:05 AM UTC 24 |
| Peak memory | 271116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143794207 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.2143794207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.3007511436 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1684709200 ps |
| CPU time | 1223.72 seconds |
| Started | Oct 03 07:43:32 AM UTC 24 |
| Finished | Oct 03 08:04:09 AM UTC 24 |
| Peak memory | 293708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007511436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.3007511436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.246661382 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 97487400 ps |
| CPU time | 180.24 seconds |
| Started | Oct 03 07:43:37 AM UTC 24 |
| Finished | Oct 03 07:46:40 AM UTC 24 |
| Peak memory | 273096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246661382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.246661382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.2077333574 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 562469600 ps |
| CPU time | 53.69 seconds |
| Started | Oct 03 07:47:22 AM UTC 24 |
| Finished | Oct 03 07:48:18 AM UTC 24 |
| Peak memory | 285856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077333574 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.2077333574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.2293775137 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 150768800 ps |
| CPU time | 33.15 seconds |
| Started | Oct 03 07:45:13 AM UTC 24 |
| Finished | Oct 03 07:45:48 AM UTC 24 |
| Peak memory | 275464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2293775137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_read_word_sweep_derr.2293775137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.2367200269 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 114921200 ps |
| CPU time | 33.34 seconds |
| Started | Oct 03 07:44:54 AM UTC 24 |
| Finished | Oct 03 07:45:29 AM UTC 24 |
| Peak memory | 275516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367200269 -assert nopostproc + UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.2367200269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.3228677342 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 672598900 ps |
| CPU time | 153.07 seconds |
| Started | Oct 03 07:44:48 AM UTC 24 |
| Finished | Oct 03 07:47:23 AM UTC 24 |
| Peak memory | 301948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3228677342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.3228677342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.1496357862 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1314230400 ps |
| CPU time | 169.89 seconds |
| Started | Oct 03 07:45:30 AM UTC 24 |
| Finished | Oct 03 07:48:23 AM UTC 24 |
| Peak memory | 291828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496357862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.1496357862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.3532347593 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 725128800 ps |
| CPU time | 151.57 seconds |
| Started | Oct 03 07:44:56 AM UTC 24 |
| Finished | Oct 03 07:47:30 AM UTC 24 |
| Peak memory | 306432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=3532347593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash _ctrl_ro_serr.3532347593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.1221819813 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 18468318900 ps |
| CPU time | 556.88 seconds |
| Started | Oct 03 07:44:52 AM UTC 24 |
| Finished | Oct 03 07:54:16 AM UTC 24 |
| Peak memory | 330740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221819813 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.1221819813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.4003544015 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1856950400 ps |
| CPU time | 256.4 seconds |
| Started | Oct 03 07:45:48 AM UTC 24 |
| Finished | Oct 03 07:50:08 AM UTC 24 |
| Peak memory | 300044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=4003544015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 3.flash_ctrl_rw_derr.4003544015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.201119089 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 39253600 ps |
| CPU time | 46.78 seconds |
| Started | Oct 03 07:47:06 AM UTC 24 |
| Finished | Oct 03 07:47:54 AM UTC 24 |
| Peak memory | 287604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201119089 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.201119089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.572270066 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 35772600 ps |
| CPU time | 38.83 seconds |
| Started | Oct 03 07:47:07 AM UTC 24 |
| Finished | Oct 03 07:47:47 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=572270066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctr l_rw_evict_all_en.572270066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.3856933705 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 5194965900 ps |
| CPU time | 228.93 seconds |
| Started | Oct 03 07:45:01 AM UTC 24 |
| Finished | Oct 03 07:48:53 AM UTC 24 |
| Peak memory | 306164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3856933705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.3856933705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.4248896077 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2735171700 ps |
| CPU time | 7020.86 seconds |
| Started | Oct 03 07:47:31 AM UTC 24 |
| Finished | Oct 03 09:45:59 AM UTC 24 |
| Peak memory | 316244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248896077 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.4248896077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.1130560540 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 13453656400 ps |
| CPU time | 108.52 seconds |
| Started | Oct 03 07:47:42 AM UTC 24 |
| Finished | Oct 03 07:49:33 AM UTC 24 |
| Peak memory | 275344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130560540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1130560540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1507198804 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 428773200 ps |
| CPU time | 75.94 seconds |
| Started | Oct 03 07:45:11 AM UTC 24 |
| Finished | Oct 03 07:46:29 AM UTC 24 |
| Peak memory | 275660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150 7198804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser r_address.1507198804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.389931919 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 6533934600 ps |
| CPU time | 92.08 seconds |
| Started | Oct 03 07:45:07 AM UTC 24 |
| Finished | Oct 03 07:46:41 AM UTC 24 |
| Peak memory | 285688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38 9931919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser r_counter.389931919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.3323889219 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 38186200 ps |
| CPU time | 78.64 seconds |
| Started | Oct 03 07:43:30 AM UTC 24 |
| Finished | Oct 03 07:44:51 AM UTC 24 |
| Peak memory | 285328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323889219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3323889219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1901587325 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 13130000 ps |
| CPU time | 43.06 seconds |
| Started | Oct 03 07:43:32 AM UTC 24 |
| Finished | Oct 03 07:44:16 AM UTC 24 |
| Peak memory | 270924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901587325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1901587325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1130025110 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 199059200 ps |
| CPU time | 189.25 seconds |
| Started | Oct 03 07:47:48 AM UTC 24 |
| Finished | Oct 03 07:51:00 AM UTC 24 |
| Peak memory | 279248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130025110 -assert nopostproc +UVM_TESTN AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.1130025110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.2353573758 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 82491000 ps |
| CPU time | 46.36 seconds |
| Started | Oct 03 07:43:32 AM UTC 24 |
| Finished | Oct 03 07:44:20 AM UTC 24 |
| Peak memory | 270860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353573758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2353573758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.1029450400 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 4385146600 ps |
| CPU time | 227.71 seconds |
| Started | Oct 03 07:44:42 AM UTC 24 |
| Finished | Oct 03 07:48:34 AM UTC 24 |
| Peak memory | 275256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1029450400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.1029450400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.4220587563 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 69855900 ps |
| CPU time | 26.44 seconds |
| Started | Oct 03 08:42:03 AM UTC 24 |
| Finished | Oct 03 08:42:31 AM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220587563 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.4220587563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.988796623 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 48395500 ps |
| CPU time | 24.15 seconds |
| Started | Oct 03 08:42:02 AM UTC 24 |
| Finished | Oct 03 08:42:27 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988796623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.988796623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.1263414036 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 13663200 ps |
| CPU time | 39.82 seconds |
| Started | Oct 03 08:42:00 AM UTC 24 |
| Finished | Oct 03 08:42:41 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1263414036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ ctrl_disable.1263414036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.3872509275 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2125981900 ps |
| CPU time | 101.79 seconds |
| Started | Oct 03 08:41:48 AM UTC 24 |
| Finished | Oct 03 08:43:32 AM UTC 24 |
| Peak memory | 273032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872509275 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.3872509275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.2199571842 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 1686927200 ps |
| CPU time | 179.16 seconds |
| Started | Oct 03 08:41:50 AM UTC 24 |
| Finished | Oct 03 08:44:52 AM UTC 24 |
| Peak memory | 302192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199571842 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.2199571842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.1609870985 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 32093659900 ps |
| CPU time | 175.34 seconds |
| Started | Oct 03 08:41:50 AM UTC 24 |
| Finished | Oct 03 08:44:48 AM UTC 24 |
| Peak memory | 303848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1609870985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.flash_ctrl_intr_rd_slow_flash.1609870985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.32857666 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 269750100 ps |
| CPU time | 225.98 seconds |
| Started | Oct 03 08:41:49 AM UTC 24 |
| Finished | Oct 03 08:45:39 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32857666 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.32857666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.2894937006 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 88930000 ps |
| CPU time | 42.2 seconds |
| Started | Oct 03 08:41:53 AM UTC 24 |
| Finished | Oct 03 08:42:37 AM UTC 24 |
| Peak memory | 283576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894937006 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.2894937006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.2932353000 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 65454400 ps |
| CPU time | 44.3 seconds |
| Started | Oct 03 08:41:54 AM UTC 24 |
| Finished | Oct 03 08:42:41 AM UTC 24 |
| Peak memory | 285592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2932353000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c trl_rw_evict_all_en.2932353000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.1784328940 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 397283500 ps |
| CPU time | 79.2 seconds |
| Started | Oct 03 08:42:02 AM UTC 24 |
| Finished | Oct 03 08:43:23 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784328940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1784328940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.3525262001 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 20722600 ps |
| CPU time | 111.88 seconds |
| Started | Oct 03 08:41:44 AM UTC 24 |
| Finished | Oct 03 08:43:38 AM UTC 24 |
| Peak memory | 289408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525262001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3525262001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.1577603583 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 90742500 ps |
| CPU time | 23.16 seconds |
| Started | Oct 03 08:42:38 AM UTC 24 |
| Finished | Oct 03 08:43:03 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577603583 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.1577603583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.3072158129 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 47414200 ps |
| CPU time | 26.22 seconds |
| Started | Oct 03 08:42:32 AM UTC 24 |
| Finished | Oct 03 08:43:00 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072158129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3072158129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.3076298662 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 10833800 ps |
| CPU time | 37 seconds |
| Started | Oct 03 08:42:28 AM UTC 24 |
| Finished | Oct 03 08:43:06 AM UTC 24 |
| Peak memory | 285648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3076298662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ ctrl_disable.3076298662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.4113952398 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 12430559800 ps |
| CPU time | 256.51 seconds |
| Started | Oct 03 08:42:12 AM UTC 24 |
| Finished | Oct 03 08:46:32 AM UTC 24 |
| Peak memory | 273032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113952398 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.4113952398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.655402784 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 1275469300 ps |
| CPU time | 126.93 seconds |
| Started | Oct 03 08:42:25 AM UTC 24 |
| Finished | Oct 03 08:44:34 AM UTC 24 |
| Peak memory | 296028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655402784 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.655402784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.200924542 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 71548183800 ps |
| CPU time | 260.93 seconds |
| Started | Oct 03 08:42:25 AM UTC 24 |
| Finished | Oct 03 08:46:50 AM UTC 24 |
| Peak memory | 304048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=200924542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 31.flash_ctrl_intr_rd_slow_flash.200924542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.1364885531 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 49833200 ps |
| CPU time | 193.15 seconds |
| Started | Oct 03 08:42:19 AM UTC 24 |
| Finished | Oct 03 08:45:36 AM UTC 24 |
| Peak memory | 273248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364885531 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.1364885531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.2315620924 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 156836300 ps |
| CPU time | 34.9 seconds |
| Started | Oct 03 08:42:25 AM UTC 24 |
| Finished | Oct 03 08:43:01 AM UTC 24 |
| Peak memory | 287588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315620924 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.2315620924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.3930846770 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 36349700 ps |
| CPU time | 48.11 seconds |
| Started | Oct 03 08:42:26 AM UTC 24 |
| Finished | Oct 03 08:43:16 AM UTC 24 |
| Peak memory | 287668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3930846770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c trl_rw_evict_all_en.3930846770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.480152661 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 776419000 ps |
| CPU time | 65.62 seconds |
| Started | Oct 03 08:42:31 AM UTC 24 |
| Finished | Oct 03 08:43:39 AM UTC 24 |
| Peak memory | 275156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480152661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.480152661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.846450526 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 18850600 ps |
| CPU time | 69.03 seconds |
| Started | Oct 03 08:42:09 AM UTC 24 |
| Finished | Oct 03 08:43:20 AM UTC 24 |
| Peak memory | 285512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846450526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.846450526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.2862938029 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 83088400 ps |
| CPU time | 18.35 seconds |
| Started | Oct 03 08:43:08 AM UTC 24 |
| Finished | Oct 03 08:43:27 AM UTC 24 |
| Peak memory | 269304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862938029 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.2862938029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.2116244700 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 13852000 ps |
| CPU time | 24.59 seconds |
| Started | Oct 03 08:43:04 AM UTC 24 |
| Finished | Oct 03 08:43:30 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116244700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2116244700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.2597225631 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 13014200 ps |
| CPU time | 29.57 seconds |
| Started | Oct 03 08:43:00 AM UTC 24 |
| Finished | Oct 03 08:43:31 AM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2597225631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ ctrl_disable.2597225631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.149449162 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 10830205300 ps |
| CPU time | 213.8 seconds |
| Started | Oct 03 08:42:42 AM UTC 24 |
| Finished | Oct 03 08:46:19 AM UTC 24 |
| Peak memory | 273036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149449162 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.149449162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.801195280 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 3495765300 ps |
| CPU time | 143.43 seconds |
| Started | Oct 03 08:42:43 AM UTC 24 |
| Finished | Oct 03 08:45:09 AM UTC 24 |
| Peak memory | 306220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801195280 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.801195280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1155846745 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 47732859000 ps |
| CPU time | 155.84 seconds |
| Started | Oct 03 08:42:47 AM UTC 24 |
| Finished | Oct 03 08:45:25 AM UTC 24 |
| Peak memory | 303852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=1155846745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.flash_ctrl_intr_rd_slow_flash.1155846745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.2897335719 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 120696200 ps |
| CPU time | 216.98 seconds |
| Started | Oct 03 08:42:42 AM UTC 24 |
| Finished | Oct 03 08:46:22 AM UTC 24 |
| Peak memory | 271152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897335719 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.2897335719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.3571572617 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 39596000 ps |
| CPU time | 52.95 seconds |
| Started | Oct 03 08:42:53 AM UTC 24 |
| Finished | Oct 03 08:43:48 AM UTC 24 |
| Peak memory | 287904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571572617 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.3571572617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.751983832 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 88593100 ps |
| CPU time | 42.52 seconds |
| Started | Oct 03 08:42:54 AM UTC 24 |
| Finished | Oct 03 08:43:38 AM UTC 24 |
| Peak memory | 285884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=751983832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ct rl_rw_evict_all_en.751983832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.2031217165 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2125522600 ps |
| CPU time | 82.44 seconds |
| Started | Oct 03 08:43:02 AM UTC 24 |
| Finished | Oct 03 08:44:26 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031217165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.2031217165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.1693310935 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 61916400 ps |
| CPU time | 90.05 seconds |
| Started | Oct 03 08:42:40 AM UTC 24 |
| Finished | Oct 03 08:44:13 AM UTC 24 |
| Peak memory | 287560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693310935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.1693310935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.2944261311 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 30071500 ps |
| CPU time | 23.05 seconds |
| Started | Oct 03 08:43:25 AM UTC 24 |
| Finished | Oct 03 08:43:49 AM UTC 24 |
| Peak memory | 269240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944261311 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.2944261311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.2957541006 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 43188100 ps |
| CPU time | 20.57 seconds |
| Started | Oct 03 08:43:23 AM UTC 24 |
| Finished | Oct 03 08:43:45 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957541006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2957541006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.4055371227 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 10274700 ps |
| CPU time | 44.12 seconds |
| Started | Oct 03 08:43:20 AM UTC 24 |
| Finished | Oct 03 08:44:06 AM UTC 24 |
| Peak memory | 285524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4055371227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ ctrl_disable.4055371227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.725703320 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 991936100 ps |
| CPU time | 49.95 seconds |
| Started | Oct 03 08:43:15 AM UTC 24 |
| Finished | Oct 03 08:44:06 AM UTC 24 |
| Peak memory | 274504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725703320 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.725703320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.1857748369 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3087696000 ps |
| CPU time | 225.5 seconds |
| Started | Oct 03 08:43:17 AM UTC 24 |
| Finished | Oct 03 08:47:06 AM UTC 24 |
| Peak memory | 302128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857748369 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.1857748369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3371741540 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 5933288900 ps |
| CPU time | 137.26 seconds |
| Started | Oct 03 08:43:17 AM UTC 24 |
| Finished | Oct 03 08:45:37 AM UTC 24 |
| Peak memory | 304068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3371741540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.flash_ctrl_intr_rd_slow_flash.3371741540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.793914689 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 159835900 ps |
| CPU time | 171.12 seconds |
| Started | Oct 03 08:43:15 AM UTC 24 |
| Finished | Oct 03 08:46:09 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793914689 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.793914689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.1506920912 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 54202600 ps |
| CPU time | 35.59 seconds |
| Started | Oct 03 08:43:19 AM UTC 24 |
| Finished | Oct 03 08:43:56 AM UTC 24 |
| Peak memory | 287872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506920912 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.1506920912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.2057941504 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 55779300 ps |
| CPU time | 53.77 seconds |
| Started | Oct 03 08:43:20 AM UTC 24 |
| Finished | Oct 03 08:44:16 AM UTC 24 |
| Peak memory | 287904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2057941504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c trl_rw_evict_all_en.2057941504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.771173811 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 4949489500 ps |
| CPU time | 69.39 seconds |
| Started | Oct 03 08:43:23 AM UTC 24 |
| Finished | Oct 03 08:44:35 AM UTC 24 |
| Peak memory | 275156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771173811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.771173811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.1049690184 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 27994200 ps |
| CPU time | 147.24 seconds |
| Started | Oct 03 08:43:09 AM UTC 24 |
| Finished | Oct 03 08:45:39 AM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049690184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.1049690184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.3161755807 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 29568400 ps |
| CPU time | 16.57 seconds |
| Started | Oct 03 08:43:46 AM UTC 24 |
| Finished | Oct 03 08:44:04 AM UTC 24 |
| Peak memory | 275188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161755807 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.3161755807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.1569684037 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 22767400 ps |
| CPU time | 26.59 seconds |
| Started | Oct 03 08:43:40 AM UTC 24 |
| Finished | Oct 03 08:44:08 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569684037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1569684037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.2764102768 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 11953700 ps |
| CPU time | 32 seconds |
| Started | Oct 03 08:43:39 AM UTC 24 |
| Finished | Oct 03 08:44:12 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2764102768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ ctrl_disable.2764102768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.1838611969 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 1697404100 ps |
| CPU time | 144.37 seconds |
| Started | Oct 03 08:43:31 AM UTC 24 |
| Finished | Oct 03 08:45:58 AM UTC 24 |
| Peak memory | 273032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838611969 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.1838611969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.2439268527 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 4444430300 ps |
| CPU time | 140.91 seconds |
| Started | Oct 03 08:43:32 AM UTC 24 |
| Finished | Oct 03 08:45:56 AM UTC 24 |
| Peak memory | 306096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439268527 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.2439268527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.4170608895 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 86579355300 ps |
| CPU time | 465.44 seconds |
| Started | Oct 03 08:43:32 AM UTC 24 |
| Finished | Oct 03 08:51:24 AM UTC 24 |
| Peak memory | 301796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=4170608895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.flash_ctrl_intr_rd_slow_flash.4170608895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.4029570887 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 125328700 ps |
| CPU time | 188.66 seconds |
| Started | Oct 03 08:43:31 AM UTC 24 |
| Finished | Oct 03 08:46:43 AM UTC 24 |
| Peak memory | 271196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029570887 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.4029570887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.3462028851 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 43522700 ps |
| CPU time | 33.95 seconds |
| Started | Oct 03 08:43:32 AM UTC 24 |
| Finished | Oct 03 08:44:08 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462028851 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.3462028851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.3129515583 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 174050400 ps |
| CPU time | 53.48 seconds |
| Started | Oct 03 08:43:35 AM UTC 24 |
| Finished | Oct 03 08:44:30 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3129515583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c trl_rw_evict_all_en.3129515583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.1230687022 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2883402700 ps |
| CPU time | 91.37 seconds |
| Started | Oct 03 08:43:40 AM UTC 24 |
| Finished | Oct 03 08:45:13 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230687022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1230687022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.2398354722 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 52214700 ps |
| CPU time | 92.17 seconds |
| Started | Oct 03 08:43:28 AM UTC 24 |
| Finished | Oct 03 08:45:02 AM UTC 24 |
| Peak memory | 287376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398354722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.2398354722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.94503355 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 255690900 ps |
| CPU time | 27.28 seconds |
| Started | Oct 03 08:44:13 AM UTC 24 |
| Finished | Oct 03 08:44:42 AM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94503355 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.94503355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.2471884023 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 49451100 ps |
| CPU time | 32.49 seconds |
| Started | Oct 03 08:44:12 AM UTC 24 |
| Finished | Oct 03 08:44:46 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471884023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2471884023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.2716941729 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 30523300 ps |
| CPU time | 35.56 seconds |
| Started | Oct 03 08:44:09 AM UTC 24 |
| Finished | Oct 03 08:44:46 AM UTC 24 |
| Peak memory | 285716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2716941729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ ctrl_disable.2716941729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.889450533 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 6208077600 ps |
| CPU time | 134.81 seconds |
| Started | Oct 03 08:43:50 AM UTC 24 |
| Finished | Oct 03 08:46:08 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889450533 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.889450533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.2741698312 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 17006003000 ps |
| CPU time | 276.62 seconds |
| Started | Oct 03 08:43:57 AM UTC 24 |
| Finished | Oct 03 08:48:38 AM UTC 24 |
| Peak memory | 293772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741698312 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.2741698312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.548310746 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 23307965600 ps |
| CPU time | 162.05 seconds |
| Started | Oct 03 08:44:04 AM UTC 24 |
| Finished | Oct 03 08:46:49 AM UTC 24 |
| Peak memory | 303844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=548310746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 35.flash_ctrl_intr_rd_slow_flash.548310746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.4272426498 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 140712900 ps |
| CPU time | 177.34 seconds |
| Started | Oct 03 08:43:50 AM UTC 24 |
| Finished | Oct 03 08:46:50 AM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272426498 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.4272426498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.3328636892 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 27884700 ps |
| CPU time | 40.09 seconds |
| Started | Oct 03 08:44:07 AM UTC 24 |
| Finished | Oct 03 08:44:48 AM UTC 24 |
| Peak memory | 287608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328636892 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.3328636892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.2322415961 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 29601600 ps |
| CPU time | 51.58 seconds |
| Started | Oct 03 08:44:08 AM UTC 24 |
| Finished | Oct 03 08:45:01 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2322415961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c trl_rw_evict_all_en.2322415961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.3171115352 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2137716700 ps |
| CPU time | 88.38 seconds |
| Started | Oct 03 08:44:09 AM UTC 24 |
| Finished | Oct 03 08:45:39 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171115352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3171115352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.4010850398 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 69397500 ps |
| CPU time | 150.8 seconds |
| Started | Oct 03 08:43:48 AM UTC 24 |
| Finished | Oct 03 08:46:21 AM UTC 24 |
| Peak memory | 289420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010850398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.4010850398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.3668973371 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 149951800 ps |
| CPU time | 18.14 seconds |
| Started | Oct 03 08:44:43 AM UTC 24 |
| Finished | Oct 03 08:45:02 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668973371 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.3668973371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.1633136233 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 20413500 ps |
| CPU time | 18.16 seconds |
| Started | Oct 03 08:44:40 AM UTC 24 |
| Finished | Oct 03 08:44:59 AM UTC 24 |
| Peak memory | 284808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633136233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.1633136233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.3246162328 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 15925200 ps |
| CPU time | 35.17 seconds |
| Started | Oct 03 08:44:35 AM UTC 24 |
| Finished | Oct 03 08:45:12 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3246162328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ ctrl_disable.3246162328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.2828535526 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 9863633600 ps |
| CPU time | 101.1 seconds |
| Started | Oct 03 08:44:16 AM UTC 24 |
| Finished | Oct 03 08:46:00 AM UTC 24 |
| Peak memory | 273228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828535526 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.2828535526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.3269521680 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2890730400 ps |
| CPU time | 149.94 seconds |
| Started | Oct 03 08:44:19 AM UTC 24 |
| Finished | Oct 03 08:46:51 AM UTC 24 |
| Peak memory | 304084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269521680 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.3269521680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3155949707 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 6003663200 ps |
| CPU time | 186.84 seconds |
| Started | Oct 03 08:44:22 AM UTC 24 |
| Finished | Oct 03 08:47:32 AM UTC 24 |
| Peak memory | 305988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3155949707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.flash_ctrl_intr_rd_slow_flash.3155949707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.978121325 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 119470300 ps |
| CPU time | 181.69 seconds |
| Started | Oct 03 08:44:17 AM UTC 24 |
| Finished | Oct 03 08:47:22 AM UTC 24 |
| Peak memory | 275168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978121325 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.978121325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.3390272742 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 127508400 ps |
| CPU time | 61.74 seconds |
| Started | Oct 03 08:44:27 AM UTC 24 |
| Finished | Oct 03 08:45:31 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390272742 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.3390272742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.4283358172 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 30873200 ps |
| CPU time | 49.41 seconds |
| Started | Oct 03 08:44:30 AM UTC 24 |
| Finished | Oct 03 08:45:21 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4283358172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c trl_rw_evict_all_en.4283358172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.244446006 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 562362400 ps |
| CPU time | 83.16 seconds |
| Started | Oct 03 08:44:35 AM UTC 24 |
| Finished | Oct 03 08:46:01 AM UTC 24 |
| Peak memory | 275348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244446006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.244446006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.1377686193 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 59989500 ps |
| CPU time | 193.77 seconds |
| Started | Oct 03 08:44:13 AM UTC 24 |
| Finished | Oct 03 08:47:30 AM UTC 24 |
| Peak memory | 289676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377686193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.1377686193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.102946206 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 47537300 ps |
| CPU time | 25.02 seconds |
| Started | Oct 03 08:45:10 AM UTC 24 |
| Finished | Oct 03 08:45:36 AM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102946206 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.102946206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.1852095321 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 47135500 ps |
| CPU time | 19.64 seconds |
| Started | Oct 03 08:45:03 AM UTC 24 |
| Finished | Oct 03 08:45:24 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852095321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1852095321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.4070619544 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 31012200 ps |
| CPU time | 28.68 seconds |
| Started | Oct 03 08:45:02 AM UTC 24 |
| Finished | Oct 03 08:45:32 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4070619544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ ctrl_disable.4070619544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.1363852851 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 3700390900 ps |
| CPU time | 132.93 seconds |
| Started | Oct 03 08:44:47 AM UTC 24 |
| Finished | Oct 03 08:47:02 AM UTC 24 |
| Peak memory | 273228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363852851 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.1363852851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.3246337422 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 1694396700 ps |
| CPU time | 234.88 seconds |
| Started | Oct 03 08:44:49 AM UTC 24 |
| Finished | Oct 03 08:48:48 AM UTC 24 |
| Peak memory | 301968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246337422 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.3246337422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3093241387 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 12136379800 ps |
| CPU time | 193.11 seconds |
| Started | Oct 03 08:44:50 AM UTC 24 |
| Finished | Oct 03 08:48:07 AM UTC 24 |
| Peak memory | 303880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3093241387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.flash_ctrl_intr_rd_slow_flash.3093241387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.2929093840 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 71189600 ps |
| CPU time | 177.6 seconds |
| Started | Oct 03 08:44:49 AM UTC 24 |
| Finished | Oct 03 08:47:50 AM UTC 24 |
| Peak memory | 275184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929093840 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.2929093840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.2229125268 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 27142400 ps |
| CPU time | 59.02 seconds |
| Started | Oct 03 08:44:53 AM UTC 24 |
| Finished | Oct 03 08:45:54 AM UTC 24 |
| Peak memory | 285664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229125268 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.2229125268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.409197328 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 30541200 ps |
| CPU time | 59.98 seconds |
| Started | Oct 03 08:44:59 AM UTC 24 |
| Finished | Oct 03 08:46:01 AM UTC 24 |
| Peak memory | 287708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=409197328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ct rl_rw_evict_all_en.409197328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.3989244679 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 1713389500 ps |
| CPU time | 69.87 seconds |
| Started | Oct 03 08:45:03 AM UTC 24 |
| Finished | Oct 03 08:46:15 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989244679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3989244679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.2606689539 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 3574161400 ps |
| CPU time | 402.1 seconds |
| Started | Oct 03 08:44:47 AM UTC 24 |
| Finished | Oct 03 08:51:35 AM UTC 24 |
| Peak memory | 291472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606689539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.2606689539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.3158978523 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 80705500 ps |
| CPU time | 17.4 seconds |
| Started | Oct 03 08:45:38 AM UTC 24 |
| Finished | Oct 03 08:45:57 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158978523 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.3158978523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.1720930 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 27123500 ps |
| CPU time | 19 seconds |
| Started | Oct 03 08:45:37 AM UTC 24 |
| Finished | Oct 03 08:45:57 AM UTC 24 |
| Peak memory | 284816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.1720930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.2232803123 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 10503200 ps |
| CPU time | 33.95 seconds |
| Started | Oct 03 08:45:33 AM UTC 24 |
| Finished | Oct 03 08:46:08 AM UTC 24 |
| Peak memory | 285820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2232803123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ ctrl_disable.2232803123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.3526981823 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3248074000 ps |
| CPU time | 122.37 seconds |
| Started | Oct 03 08:45:14 AM UTC 24 |
| Finished | Oct 03 08:47:19 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526981823 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.3526981823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.790729646 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 3667578000 ps |
| CPU time | 190.33 seconds |
| Started | Oct 03 08:45:24 AM UTC 24 |
| Finished | Oct 03 08:48:38 AM UTC 24 |
| Peak memory | 302124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790729646 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.790729646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.677644210 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 23689938700 ps |
| CPU time | 147.79 seconds |
| Started | Oct 03 08:45:26 AM UTC 24 |
| Finished | Oct 03 08:47:56 AM UTC 24 |
| Peak memory | 303848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=677644210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 38.flash_ctrl_intr_rd_slow_flash.677644210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.3035228400 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 40257900 ps |
| CPU time | 182.29 seconds |
| Started | Oct 03 08:45:22 AM UTC 24 |
| Finished | Oct 03 08:48:28 AM UTC 24 |
| Peak memory | 274972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035228400 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.3035228400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.3321385745 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 72798400 ps |
| CPU time | 49.26 seconds |
| Started | Oct 03 08:45:27 AM UTC 24 |
| Finished | Oct 03 08:46:17 AM UTC 24 |
| Peak memory | 285656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321385745 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.3321385745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.2875706663 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 2548842200 ps |
| CPU time | 68.24 seconds |
| Started | Oct 03 08:45:37 AM UTC 24 |
| Finished | Oct 03 08:46:47 AM UTC 24 |
| Peak memory | 275408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875706663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2875706663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.353825221 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 56054500 ps |
| CPU time | 83.91 seconds |
| Started | Oct 03 08:45:13 AM UTC 24 |
| Finished | Oct 03 08:46:39 AM UTC 24 |
| Peak memory | 277136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353825221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.353825221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.2389485929 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 50838000 ps |
| CPU time | 25.58 seconds |
| Started | Oct 03 08:46:01 AM UTC 24 |
| Finished | Oct 03 08:46:28 AM UTC 24 |
| Peak memory | 269320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389485929 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.2389485929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.2476976683 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 46292700 ps |
| CPU time | 22.35 seconds |
| Started | Oct 03 08:45:59 AM UTC 24 |
| Finished | Oct 03 08:46:23 AM UTC 24 |
| Peak memory | 284812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476976683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2476976683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.1430972775 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 72039100 ps |
| CPU time | 42.98 seconds |
| Started | Oct 03 08:45:58 AM UTC 24 |
| Finished | Oct 03 08:46:43 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1430972775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ ctrl_disable.1430972775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.2412172014 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 4713193800 ps |
| CPU time | 202.01 seconds |
| Started | Oct 03 08:45:39 AM UTC 24 |
| Finished | Oct 03 08:49:05 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412172014 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.2412172014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.1779545796 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 3418584200 ps |
| CPU time | 185.89 seconds |
| Started | Oct 03 08:45:41 AM UTC 24 |
| Finished | Oct 03 08:48:50 AM UTC 24 |
| Peak memory | 304084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779545796 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.1779545796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3728915006 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 12483817900 ps |
| CPU time | 288.83 seconds |
| Started | Oct 03 08:45:55 AM UTC 24 |
| Finished | Oct 03 08:50:48 AM UTC 24 |
| Peak memory | 303912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3728915006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.flash_ctrl_intr_rd_slow_flash.3728915006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.116033083 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 48239800 ps |
| CPU time | 186.7 seconds |
| Started | Oct 03 08:45:41 AM UTC 24 |
| Finished | Oct 03 08:48:51 AM UTC 24 |
| Peak memory | 270972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116033083 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.116033083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.3122402568 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 122058600 ps |
| CPU time | 51.85 seconds |
| Started | Oct 03 08:45:57 AM UTC 24 |
| Finished | Oct 03 08:46:50 AM UTC 24 |
| Peak memory | 283584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122402568 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.3122402568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.3434907092 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 74464500 ps |
| CPU time | 59.54 seconds |
| Started | Oct 03 08:45:57 AM UTC 24 |
| Finished | Oct 03 08:46:58 AM UTC 24 |
| Peak memory | 287604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3434907092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c trl_rw_evict_all_en.3434907092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.235169170 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 1434065800 ps |
| CPU time | 90.33 seconds |
| Started | Oct 03 08:45:58 AM UTC 24 |
| Finished | Oct 03 08:47:31 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235169170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.235169170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.1570285500 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 56109500 ps |
| CPU time | 181.37 seconds |
| Started | Oct 03 08:45:39 AM UTC 24 |
| Finished | Oct 03 08:48:44 AM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570285500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1570285500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.371999775 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 53090700 ps |
| CPU time | 25.34 seconds |
| Started | Oct 03 07:54:26 AM UTC 24 |
| Finished | Oct 03 07:54:53 AM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371999775 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.371999775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1249149908 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 96972800 ps |
| CPU time | 28.79 seconds |
| Started | Oct 03 07:54:09 AM UTC 24 |
| Finished | Oct 03 07:54:39 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249149908 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.1249149908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.2587916837 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 49390100 ps |
| CPU time | 22.65 seconds |
| Started | Oct 03 07:53:32 AM UTC 24 |
| Finished | Oct 03 07:53:56 AM UTC 24 |
| Peak memory | 294924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587916837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.2587916837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.2412208806 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 11975100 ps |
| CPU time | 42.96 seconds |
| Started | Oct 03 07:52:56 AM UTC 24 |
| Finished | Oct 03 07:53:40 AM UTC 24 |
| Peak memory | 285820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2412208806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_disable.2412208806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.3704603280 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 12240751100 ps |
| CPU time | 672.4 seconds |
| Started | Oct 03 07:48:54 AM UTC 24 |
| Finished | Oct 03 08:00:15 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704603280 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3704603280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.43078482 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 4424765000 ps |
| CPU time | 3364.45 seconds |
| Started | Oct 03 07:50:08 AM UTC 24 |
| Finished | Oct 03 08:46:49 AM UTC 24 |
| Peak memory | 275876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43078482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.43078482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.1100480968 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1517056800 ps |
| CPU time | 3248.97 seconds |
| Started | Oct 03 07:49:56 AM UTC 24 |
| Finished | Oct 03 08:44:38 AM UTC 24 |
| Peak memory | 277936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11 00480968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _error_prog_type.1100480968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.3533565084 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 17311777500 ps |
| CPU time | 1390.84 seconds |
| Started | Oct 03 07:50:02 AM UTC 24 |
| Finished | Oct 03 08:13:29 AM UTC 24 |
| Peak memory | 285396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533565084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3533565084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.3651615931 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 198259600 ps |
| CPU time | 34.26 seconds |
| Started | Oct 03 07:49:20 AM UTC 24 |
| Finished | Oct 03 07:49:56 AM UTC 24 |
| Peak memory | 275340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36 51615931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc h_code.3651615931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1087770517 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 902799200 ps |
| CPU time | 58.08 seconds |
| Started | Oct 03 07:53:36 AM UTC 24 |
| Finished | Oct 03 07:54:36 AM UTC 24 |
| Peak memory | 275236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087770 517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_f s_sup.1087770517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.2958520567 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 847621816500 ps |
| CPU time | 2829.29 seconds |
| Started | Oct 03 07:49:34 AM UTC 24 |
| Finished | Oct 03 08:37:16 AM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958520567 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.2958520567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.185093084 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 288022767900 ps |
| CPU time | 3227.84 seconds |
| Started | Oct 03 07:49:12 AM UTC 24 |
| Finished | Oct 03 08:43:33 AM UTC 24 |
| Peak memory | 277988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185093084 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.185093084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.2060977329 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 110878600 ps |
| CPU time | 146.19 seconds |
| Started | Oct 03 07:48:35 AM UTC 24 |
| Finished | Oct 03 07:51:04 AM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060977329 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2060977329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1121096895 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 10012509500 ps |
| CPU time | 142.69 seconds |
| Started | Oct 03 07:54:23 AM UTC 24 |
| Finished | Oct 03 07:56:48 AM UTC 24 |
| Peak memory | 394260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1121096895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1121096895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.219623377 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 15372400 ps |
| CPU time | 18.41 seconds |
| Started | Oct 03 07:54:17 AM UTC 24 |
| Finished | Oct 03 07:54:36 AM UTC 24 |
| Peak memory | 275248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=219623377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 .flash_ctrl_hw_read_seed_err.219623377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.80789108 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 760477782500 ps |
| CPU time | 1044.61 seconds |
| Started | Oct 03 07:49:09 AM UTC 24 |
| Finished | Oct 03 08:06:46 AM UTC 24 |
| Peak memory | 275172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80789108 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.80789108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.3882789593 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 4450986100 ps |
| CPU time | 654.63 seconds |
| Started | Oct 03 07:51:43 AM UTC 24 |
| Finished | Oct 03 08:02:46 AM UTC 24 |
| Peak memory | 332820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3882789593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integr ity.3882789593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.997417293 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2490205600 ps |
| CPU time | 150.29 seconds |
| Started | Oct 03 07:51:56 AM UTC 24 |
| Finished | Oct 03 07:54:29 AM UTC 24 |
| Peak memory | 304044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997417293 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.997417293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3690666186 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 49577673300 ps |
| CPU time | 314.83 seconds |
| Started | Oct 03 07:52:15 AM UTC 24 |
| Finished | Oct 03 07:57:34 AM UTC 24 |
| Peak memory | 301992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=3690666186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_intr_rd_slow_flash.3690666186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.985916554 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2080889600 ps |
| CPU time | 72.76 seconds |
| Started | Oct 03 07:52:14 AM UTC 24 |
| Finished | Oct 03 07:53:28 AM UTC 24 |
| Peak memory | 275252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985916554 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.985916554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3790657105 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 44141862800 ps |
| CPU time | 219.24 seconds |
| Started | Oct 03 07:52:16 AM UTC 24 |
| Finished | Oct 03 07:55:58 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790657105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3790657105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.3314295515 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 4148378700 ps |
| CPU time | 103.8 seconds |
| Started | Oct 03 07:50:08 AM UTC 24 |
| Finished | Oct 03 07:51:54 AM UTC 24 |
| Peak memory | 270912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314295515 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3314295515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3246737754 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 35636800 ps |
| CPU time | 23.6 seconds |
| Started | Oct 03 07:54:13 AM UTC 24 |
| Finished | Oct 03 07:54:38 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3246737754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_lcmgr_intg.3246737754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.2103948753 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1139570200 ps |
| CPU time | 89.47 seconds |
| Started | Oct 03 07:50:11 AM UTC 24 |
| Finished | Oct 03 07:51:42 AM UTC 24 |
| Peak memory | 270876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103948753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash _ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.2103948753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.3537855354 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1724345100 ps |
| CPU time | 174.63 seconds |
| Started | Oct 03 07:49:15 AM UTC 24 |
| Finished | Oct 03 07:52:13 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3537855354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.3537855354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.3189987264 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 45949700 ps |
| CPU time | 201.32 seconds |
| Started | Oct 03 07:49:10 AM UTC 24 |
| Finished | Oct 03 07:52:34 AM UTC 24 |
| Peak memory | 275636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189987264 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.3189987264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.2081061140 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1974240900 ps |
| CPU time | 179.67 seconds |
| Started | Oct 03 07:51:42 AM UTC 24 |
| Finished | Oct 03 07:54:44 AM UTC 24 |
| Peak memory | 291824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1 00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2081061140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.2081061140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1350042900 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 27440000 ps |
| CPU time | 109.75 seconds |
| Started | Oct 03 07:48:46 AM UTC 24 |
| Finished | Oct 03 07:50:38 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350042900 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1350042900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.3096997153 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 44518100 ps |
| CPU time | 25.83 seconds |
| Started | Oct 03 07:53:44 AM UTC 24 |
| Finished | Oct 03 07:54:12 AM UTC 24 |
| Peak memory | 273412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo /hw/dv/tools/sim.tcl +ntb_random_seed=3096997153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.3096997153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.3713271552 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4749015400 ps |
| CPU time | 151.38 seconds |
| Started | Oct 03 07:52:30 AM UTC 24 |
| Finished | Oct 03 07:55:04 AM UTC 24 |
| Peak memory | 271188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713271552 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.3713271552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.4294371737 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 164579500 ps |
| CPU time | 1039.35 seconds |
| Started | Oct 03 07:48:33 AM UTC 24 |
| Finished | Oct 03 08:06:05 AM UTC 24 |
| Peak memory | 293708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294371737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.4294371737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.1008521913 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 750933800 ps |
| CPU time | 211.36 seconds |
| Started | Oct 03 07:48:40 AM UTC 24 |
| Finished | Oct 03 07:52:15 AM UTC 24 |
| Peak memory | 273096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008521913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1008521913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.1046206574 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 128095300 ps |
| CPU time | 39.38 seconds |
| Started | Oct 03 07:52:54 AM UTC 24 |
| Finished | Oct 03 07:53:35 AM UTC 24 |
| Peak memory | 287712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046206574 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.1046206574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.638906743 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 18968700 ps |
| CPU time | 29.84 seconds |
| Started | Oct 03 07:51:05 AM UTC 24 |
| Finished | Oct 03 07:51:36 AM UTC 24 |
| Peak memory | 275312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=638906743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_read_word_sweep_derr.638906743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.52498103 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 27048600 ps |
| CPU time | 24.76 seconds |
| Started | Oct 03 07:50:39 AM UTC 24 |
| Finished | Oct 03 07:51:05 AM UTC 24 |
| Peak memory | 275324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52498103 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.52498103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.3013094038 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 644902900 ps |
| CPU time | 120.78 seconds |
| Started | Oct 03 07:50:26 AM UTC 24 |
| Finished | Oct 03 07:52:29 AM UTC 24 |
| Peak memory | 291784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3013094038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.3013094038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.3964413927 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2736124000 ps |
| CPU time | 126.98 seconds |
| Started | Oct 03 07:51:05 AM UTC 24 |
| Finished | Oct 03 07:53:14 AM UTC 24 |
| Peak memory | 291844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964413927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.3964413927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.1424485892 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 12237741500 ps |
| CPU time | 160.11 seconds |
| Started | Oct 03 07:50:44 AM UTC 24 |
| Finished | Oct 03 07:53:27 AM UTC 24 |
| Peak memory | 306168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1424485892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_ro_serr.1424485892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.1244397157 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 7424926900 ps |
| CPU time | 492.2 seconds |
| Started | Oct 03 07:50:35 AM UTC 24 |
| Finished | Oct 03 07:58:54 AM UTC 24 |
| Peak memory | 330836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244397157 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.1244397157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2983595819 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 29651341000 ps |
| CPU time | 249.65 seconds |
| Started | Oct 03 07:51:18 AM UTC 24 |
| Finished | Oct 03 07:55:32 AM UTC 24 |
| Peak memory | 300044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2983595819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 4.flash_ctrl_rw_derr.2983595819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.2576510558 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 28325900 ps |
| CPU time | 55.73 seconds |
| Started | Oct 03 07:52:46 AM UTC 24 |
| Finished | Oct 03 07:53:44 AM UTC 24 |
| Peak memory | 287872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2576510558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct rl_rw_evict_all_en.2576510558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.1272706781 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1197946800 ps |
| CPU time | 6767.23 seconds |
| Started | Oct 03 07:53:16 AM UTC 24 |
| Finished | Oct 03 09:47:25 AM UTC 24 |
| Peak memory | 314192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272706781 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.1272706781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.380095253 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 11712601300 ps |
| CPU time | 116.23 seconds |
| Started | Oct 03 07:53:28 AM UTC 24 |
| Finished | Oct 03 07:55:26 AM UTC 24 |
| Peak memory | 275164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380095253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.380095253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.1119231178 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3445371100 ps |
| CPU time | 111.56 seconds |
| Started | Oct 03 07:51:01 AM UTC 24 |
| Finished | Oct 03 07:52:55 AM UTC 24 |
| Peak memory | 275640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111 9231178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser r_address.1119231178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.4228986562 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 3060025600 ps |
| CPU time | 115.58 seconds |
| Started | Oct 03 07:50:56 AM UTC 24 |
| Finished | Oct 03 07:52:54 AM UTC 24 |
| Peak memory | 275444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42 28986562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_se rr_counter.4228986562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.241154031 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 39866200 ps |
| CPU time | 126.74 seconds |
| Started | Oct 03 07:48:25 AM UTC 24 |
| Finished | Oct 03 07:50:34 AM UTC 24 |
| Peak memory | 287364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241154031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.241154031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.1943935038 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 22550100 ps |
| CPU time | 43.53 seconds |
| Started | Oct 03 07:48:29 AM UTC 24 |
| Finished | Oct 03 07:49:14 AM UTC 24 |
| Peak memory | 270924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943935038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1943935038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.322571601 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 4365693700 ps |
| CPU time | 539.45 seconds |
| Started | Oct 03 07:53:29 AM UTC 24 |
| Finished | Oct 03 08:02:35 AM UTC 24 |
| Peak memory | 289488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322571601 -assert nopostproc +UVM_TESTNA ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.322571601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.558319654 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 34789900 ps |
| CPU time | 34.42 seconds |
| Started | Oct 03 07:48:35 AM UTC 24 |
| Finished | Oct 03 07:49:11 AM UTC 24 |
| Peak memory | 273164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558319654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.558319654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.1045418639 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2236402800 ps |
| CPU time | 240.58 seconds |
| Started | Oct 03 07:50:18 AM UTC 24 |
| Finished | Oct 03 07:54:22 AM UTC 24 |
| Peak memory | 275256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1045418639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.1045418639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.590552502 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 83709600 ps |
| CPU time | 19.24 seconds |
| Started | Oct 03 08:46:16 AM UTC 24 |
| Finished | Oct 03 08:46:36 AM UTC 24 |
| Peak memory | 275388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590552502 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.590552502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.1331093966 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 12851100 ps |
| CPU time | 21.77 seconds |
| Started | Oct 03 08:46:13 AM UTC 24 |
| Finished | Oct 03 08:46:36 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331093966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1331093966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.1645740269 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 10724200 ps |
| CPU time | 32.76 seconds |
| Started | Oct 03 08:46:09 AM UTC 24 |
| Finished | Oct 03 08:46:43 AM UTC 24 |
| Peak memory | 285400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1645740269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ ctrl_disable.1645740269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.4087021570 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 2950317800 ps |
| CPU time | 154.09 seconds |
| Started | Oct 03 08:46:02 AM UTC 24 |
| Finished | Oct 03 08:48:39 AM UTC 24 |
| Peak memory | 275080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087021570 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.4087021570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.2567531015 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 196001200 ps |
| CPU time | 178.18 seconds |
| Started | Oct 03 08:46:09 AM UTC 24 |
| Finished | Oct 03 08:49:10 AM UTC 24 |
| Peak memory | 270968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567531015 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.2567531015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.2792024310 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 346498800 ps |
| CPU time | 59.95 seconds |
| Started | Oct 03 08:46:10 AM UTC 24 |
| Finished | Oct 03 08:47:12 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792024310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2792024310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.1706673915 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 33358500 ps |
| CPU time | 174.28 seconds |
| Started | Oct 03 08:46:02 AM UTC 24 |
| Finished | Oct 03 08:48:59 AM UTC 24 |
| Peak memory | 289424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706673915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.1706673915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.295576784 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 82917500 ps |
| CPU time | 18.72 seconds |
| Started | Oct 03 08:46:34 AM UTC 24 |
| Finished | Oct 03 08:46:53 AM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295576784 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.295576784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.3497205677 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 16114800 ps |
| CPU time | 23.74 seconds |
| Started | Oct 03 08:46:28 AM UTC 24 |
| Finished | Oct 03 08:46:53 AM UTC 24 |
| Peak memory | 284812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497205677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.3497205677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.1370445478 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 10753800 ps |
| CPU time | 24.84 seconds |
| Started | Oct 03 08:46:23 AM UTC 24 |
| Finished | Oct 03 08:46:50 AM UTC 24 |
| Peak memory | 285368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1370445478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ ctrl_disable.1370445478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.1637799268 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 9283157700 ps |
| CPU time | 158.5 seconds |
| Started | Oct 03 08:46:20 AM UTC 24 |
| Finished | Oct 03 08:49:02 AM UTC 24 |
| Peak memory | 273228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637799268 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.1637799268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.1308408242 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 81141200 ps |
| CPU time | 172.68 seconds |
| Started | Oct 03 08:46:22 AM UTC 24 |
| Finished | Oct 03 08:49:18 AM UTC 24 |
| Peak memory | 270940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308408242 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.1308408242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.210671153 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 171755800 ps |
| CPU time | 280.63 seconds |
| Started | Oct 03 08:46:19 AM UTC 24 |
| Finished | Oct 03 08:51:04 AM UTC 24 |
| Peak memory | 289424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210671153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.210671153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.2080388159 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 121434900 ps |
| CPU time | 16.93 seconds |
| Started | Oct 03 08:46:48 AM UTC 24 |
| Finished | Oct 03 08:47:06 AM UTC 24 |
| Peak memory | 275188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080388159 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.2080388159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.3363078758 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 44089800 ps |
| CPU time | 26.48 seconds |
| Started | Oct 03 08:46:44 AM UTC 24 |
| Finished | Oct 03 08:47:12 AM UTC 24 |
| Peak memory | 284688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363078758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.3363078758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.3558257462 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 24731700 ps |
| CPU time | 39.14 seconds |
| Started | Oct 03 08:46:43 AM UTC 24 |
| Finished | Oct 03 08:47:24 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3558257462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ ctrl_disable.3558257462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.2507954962 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 11299148400 ps |
| CPU time | 105.48 seconds |
| Started | Oct 03 08:46:38 AM UTC 24 |
| Finished | Oct 03 08:48:25 AM UTC 24 |
| Peak memory | 273228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507954962 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.2507954962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.254432129 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 43587600 ps |
| CPU time | 166.24 seconds |
| Started | Oct 03 08:46:40 AM UTC 24 |
| Finished | Oct 03 08:49:29 AM UTC 24 |
| Peak memory | 273244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254432129 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.254432129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.765245584 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 2315381800 ps |
| CPU time | 66.86 seconds |
| Started | Oct 03 08:46:44 AM UTC 24 |
| Finished | Oct 03 08:47:53 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765245584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.765245584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.1299629745 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 33711700 ps |
| CPU time | 61.48 seconds |
| Started | Oct 03 08:46:37 AM UTC 24 |
| Finished | Oct 03 08:47:40 AM UTC 24 |
| Peak memory | 285324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299629745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.1299629745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.1455764928 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 38684900 ps |
| CPU time | 20.12 seconds |
| Started | Oct 03 08:46:52 AM UTC 24 |
| Finished | Oct 03 08:47:14 AM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455764928 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.1455764928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.244133525 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 70047600 ps |
| CPU time | 21.97 seconds |
| Started | Oct 03 08:46:51 AM UTC 24 |
| Finished | Oct 03 08:47:14 AM UTC 24 |
| Peak memory | 294924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244133525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.244133525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.1145899424 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 10607200 ps |
| CPU time | 30.81 seconds |
| Started | Oct 03 08:46:51 AM UTC 24 |
| Finished | Oct 03 08:47:23 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1145899424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ ctrl_disable.1145899424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.2834992343 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 974473100 ps |
| CPU time | 91.56 seconds |
| Started | Oct 03 08:46:50 AM UTC 24 |
| Finished | Oct 03 08:48:23 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834992343 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.2834992343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.1643705293 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 37570000 ps |
| CPU time | 177.76 seconds |
| Started | Oct 03 08:46:51 AM UTC 24 |
| Finished | Oct 03 08:49:52 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643705293 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.1643705293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.1269022240 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 1418649000 ps |
| CPU time | 64.22 seconds |
| Started | Oct 03 08:46:51 AM UTC 24 |
| Finished | Oct 03 08:47:57 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269022240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1269022240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.1451208060 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 105219500 ps |
| CPU time | 264.93 seconds |
| Started | Oct 03 08:46:50 AM UTC 24 |
| Finished | Oct 03 08:51:19 AM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451208060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1451208060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.1962796056 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 32185700 ps |
| CPU time | 16.91 seconds |
| Started | Oct 03 08:47:16 AM UTC 24 |
| Finished | Oct 03 08:47:34 AM UTC 24 |
| Peak memory | 269056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962796056 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.1962796056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.2940570857 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 25709400 ps |
| CPU time | 22.53 seconds |
| Started | Oct 03 08:47:07 AM UTC 24 |
| Finished | Oct 03 08:47:31 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940570857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2940570857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.2654093991 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 15654000 ps |
| CPU time | 34.5 seconds |
| Started | Oct 03 08:47:03 AM UTC 24 |
| Finished | Oct 03 08:47:39 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2654093991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ ctrl_disable.2654093991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.1618287374 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 2124061500 ps |
| CPU time | 45.47 seconds |
| Started | Oct 03 08:46:55 AM UTC 24 |
| Finished | Oct 03 08:47:41 AM UTC 24 |
| Peak memory | 270988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618287374 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.1618287374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.173874429 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 87309000 ps |
| CPU time | 133.02 seconds |
| Started | Oct 03 08:46:59 AM UTC 24 |
| Finished | Oct 03 08:49:14 AM UTC 24 |
| Peak memory | 271264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173874429 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.173874429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.2376462543 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 5183799400 ps |
| CPU time | 87.21 seconds |
| Started | Oct 03 08:47:06 AM UTC 24 |
| Finished | Oct 03 08:48:35 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376462543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2376462543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.2471545442 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 47749500 ps |
| CPU time | 119.5 seconds |
| Started | Oct 03 08:46:55 AM UTC 24 |
| Finished | Oct 03 08:48:56 AM UTC 24 |
| Peak memory | 287376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471545442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.2471545442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.3471504483 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 50500300 ps |
| CPU time | 22.33 seconds |
| Started | Oct 03 08:47:23 AM UTC 24 |
| Finished | Oct 03 08:47:46 AM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471504483 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.3471504483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.2914938076 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 15089500 ps |
| CPU time | 26.88 seconds |
| Started | Oct 03 08:47:21 AM UTC 24 |
| Finished | Oct 03 08:47:49 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914938076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2914938076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.265875875 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 30735900 ps |
| CPU time | 35.06 seconds |
| Started | Oct 03 08:47:17 AM UTC 24 |
| Finished | Oct 03 08:47:54 AM UTC 24 |
| Peak memory | 285632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=265875875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_c trl_disable.265875875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.729426855 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 19739819600 ps |
| CPU time | 142.1 seconds |
| Started | Oct 03 08:47:17 AM UTC 24 |
| Finished | Oct 03 08:49:42 AM UTC 24 |
| Peak memory | 275076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729426855 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.729426855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.3096675622 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 66444500 ps |
| CPU time | 148.41 seconds |
| Started | Oct 03 08:47:17 AM UTC 24 |
| Finished | Oct 03 08:49:48 AM UTC 24 |
| Peak memory | 275040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096675622 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.3096675622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.3052241446 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3779452600 ps |
| CPU time | 98.2 seconds |
| Started | Oct 03 08:47:20 AM UTC 24 |
| Finished | Oct 03 08:49:00 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052241446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3052241446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.4210143377 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 152677300 ps |
| CPU time | 207.19 seconds |
| Started | Oct 03 08:47:17 AM UTC 24 |
| Finished | Oct 03 08:50:48 AM UTC 24 |
| Peak memory | 291472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210143377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.4210143377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.3821937004 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 163534200 ps |
| CPU time | 17.11 seconds |
| Started | Oct 03 08:47:33 AM UTC 24 |
| Finished | Oct 03 08:47:51 AM UTC 24 |
| Peak memory | 269064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821937004 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.3821937004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.484117008 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 25805300 ps |
| CPU time | 26.36 seconds |
| Started | Oct 03 08:47:33 AM UTC 24 |
| Finished | Oct 03 08:48:01 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484117008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.484117008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.3711318503 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 21502100 ps |
| CPU time | 26.54 seconds |
| Started | Oct 03 08:47:31 AM UTC 24 |
| Finished | Oct 03 08:48:00 AM UTC 24 |
| Peak memory | 285584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3711318503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ ctrl_disable.3711318503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.2714301887 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 22052027800 ps |
| CPU time | 180.72 seconds |
| Started | Oct 03 08:47:25 AM UTC 24 |
| Finished | Oct 03 08:50:29 AM UTC 24 |
| Peak memory | 275080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714301887 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.2714301887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.1094209096 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 1239293500 ps |
| CPU time | 76.03 seconds |
| Started | Oct 03 08:47:32 AM UTC 24 |
| Finished | Oct 03 08:48:51 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094209096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1094209096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.1634156138 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 88733900 ps |
| CPU time | 207.73 seconds |
| Started | Oct 03 08:47:24 AM UTC 24 |
| Finished | Oct 03 08:50:55 AM UTC 24 |
| Peak memory | 291468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634156138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1634156138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.697632284 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 100639000 ps |
| CPU time | 28.64 seconds |
| Started | Oct 03 08:47:49 AM UTC 24 |
| Finished | Oct 03 08:48:20 AM UTC 24 |
| Peak memory | 275188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697632284 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.697632284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.4117920989 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 13898300 ps |
| CPU time | 27.23 seconds |
| Started | Oct 03 08:47:47 AM UTC 24 |
| Finished | Oct 03 08:48:16 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117920989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.4117920989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.3164095295 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 25640400 ps |
| CPU time | 26.11 seconds |
| Started | Oct 03 08:47:42 AM UTC 24 |
| Finished | Oct 03 08:48:10 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3164095295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ ctrl_disable.3164095295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.961559577 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 8350505900 ps |
| CPU time | 103.15 seconds |
| Started | Oct 03 08:47:40 AM UTC 24 |
| Finished | Oct 03 08:49:25 AM UTC 24 |
| Peak memory | 275084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961559577 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.961559577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.774557051 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 147254600 ps |
| CPU time | 173.84 seconds |
| Started | Oct 03 08:47:41 AM UTC 24 |
| Finished | Oct 03 08:50:38 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774557051 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.774557051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.2679618688 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 9831653600 ps |
| CPU time | 66.04 seconds |
| Started | Oct 03 08:47:42 AM UTC 24 |
| Finished | Oct 03 08:48:50 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679618688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2679618688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.38594506 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 48365900 ps |
| CPU time | 87.69 seconds |
| Started | Oct 03 08:47:35 AM UTC 24 |
| Finished | Oct 03 08:49:05 AM UTC 24 |
| Peak memory | 287364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38594506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.38594506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.2337156977 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 162594400 ps |
| CPU time | 28.17 seconds |
| Started | Oct 03 08:47:58 AM UTC 24 |
| Finished | Oct 03 08:48:28 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337156977 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.2337156977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.2764100067 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 25475200 ps |
| CPU time | 21.59 seconds |
| Started | Oct 03 08:47:57 AM UTC 24 |
| Finished | Oct 03 08:48:20 AM UTC 24 |
| Peak memory | 294924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764100067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2764100067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.1168459537 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 48945900 ps |
| CPU time | 26.07 seconds |
| Started | Oct 03 08:47:55 AM UTC 24 |
| Finished | Oct 03 08:48:22 AM UTC 24 |
| Peak memory | 285652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1168459537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ ctrl_disable.1168459537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.1162219159 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 1228374800 ps |
| CPU time | 127.34 seconds |
| Started | Oct 03 08:47:53 AM UTC 24 |
| Finished | Oct 03 08:50:03 AM UTC 24 |
| Peak memory | 273036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162219159 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.1162219159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.785650689 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 333080600 ps |
| CPU time | 173.41 seconds |
| Started | Oct 03 08:47:54 AM UTC 24 |
| Finished | Oct 03 08:50:50 AM UTC 24 |
| Peak memory | 271096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785650689 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.785650689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.654920737 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 3328516800 ps |
| CPU time | 71.76 seconds |
| Started | Oct 03 08:47:56 AM UTC 24 |
| Finished | Oct 03 08:49:09 AM UTC 24 |
| Peak memory | 275280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654920737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.654920737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.1360691694 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 714945300 ps |
| CPU time | 322.98 seconds |
| Started | Oct 03 08:47:51 AM UTC 24 |
| Finished | Oct 03 08:53:18 AM UTC 24 |
| Peak memory | 291472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360691694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.1360691694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.1348385257 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 29976300 ps |
| CPU time | 23.76 seconds |
| Started | Oct 03 08:48:21 AM UTC 24 |
| Finished | Oct 03 08:48:46 AM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348385257 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.1348385257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.1139780240 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 45955400 ps |
| CPU time | 25.82 seconds |
| Started | Oct 03 08:48:20 AM UTC 24 |
| Finished | Oct 03 08:48:47 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139780240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1139780240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.2339618140 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 32554700 ps |
| CPU time | 30.91 seconds |
| Started | Oct 03 08:48:11 AM UTC 24 |
| Finished | Oct 03 08:48:43 AM UTC 24 |
| Peak memory | 285368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2339618140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ ctrl_disable.2339618140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.3762652593 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 905002700 ps |
| CPU time | 50.08 seconds |
| Started | Oct 03 08:48:01 AM UTC 24 |
| Finished | Oct 03 08:48:53 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762652593 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.3762652593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.1020274360 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 40894900 ps |
| CPU time | 168.66 seconds |
| Started | Oct 03 08:48:08 AM UTC 24 |
| Finished | Oct 03 08:50:59 AM UTC 24 |
| Peak memory | 275636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020274360 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.1020274360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.2559698678 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 844768300 ps |
| CPU time | 57.07 seconds |
| Started | Oct 03 08:48:17 AM UTC 24 |
| Finished | Oct 03 08:49:15 AM UTC 24 |
| Peak memory | 275152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559698678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.2559698678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.2902770081 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 88104300 ps |
| CPU time | 147.04 seconds |
| Started | Oct 03 08:48:00 AM UTC 24 |
| Finished | Oct 03 08:50:30 AM UTC 24 |
| Peak memory | 287368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902770081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2902770081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.3984174362 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 176462700 ps |
| CPU time | 19.81 seconds |
| Started | Oct 03 07:58:59 AM UTC 24 |
| Finished | Oct 03 07:59:20 AM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984174362 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.3984174362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.1537805189 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 56041200 ps |
| CPU time | 28.01 seconds |
| Started | Oct 03 07:58:41 AM UTC 24 |
| Finished | Oct 03 07:59:11 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537805189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1537805189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1269143483 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 120540700 ps |
| CPU time | 27.09 seconds |
| Started | Oct 03 07:58:12 AM UTC 24 |
| Finished | Oct 03 07:58:40 AM UTC 24 |
| Peak memory | 285564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1269143483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_c trl_disable.1269143483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.2209990077 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 12906214600 ps |
| CPU time | 2860.34 seconds |
| Started | Oct 03 07:55:05 AM UTC 24 |
| Finished | Oct 03 08:43:16 AM UTC 24 |
| Peak memory | 275876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209990077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.2209990077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.1305237676 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1341440300 ps |
| CPU time | 1136.21 seconds |
| Started | Oct 03 07:54:58 AM UTC 24 |
| Finished | Oct 03 08:14:07 AM UTC 24 |
| Peak memory | 285388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305237676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1305237676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2168667783 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1770821700 ps |
| CPU time | 54.76 seconds |
| Started | Oct 03 07:54:54 AM UTC 24 |
| Finished | Oct 03 07:55:50 AM UTC 24 |
| Peak memory | 273100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21 68667783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetc h_code.2168667783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2956548448 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 10019490900 ps |
| CPU time | 93.71 seconds |
| Started | Oct 03 07:58:56 AM UTC 24 |
| Finished | Oct 03 08:00:31 AM UTC 24 |
| Peak memory | 316244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2956548448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2956548448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.1307175792 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 64868700 ps |
| CPU time | 20.69 seconds |
| Started | Oct 03 07:58:56 AM UTC 24 |
| Finished | Oct 03 07:59:17 AM UTC 24 |
| Peak memory | 269448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1307175792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1307175792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.2631365629 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 480366581000 ps |
| CPU time | 1151.69 seconds |
| Started | Oct 03 07:54:39 AM UTC 24 |
| Finished | Oct 03 08:14:07 AM UTC 24 |
| Peak memory | 275176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631365629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.2631365629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.673214461 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 8390717600 ps |
| CPU time | 115.91 seconds |
| Started | Oct 03 07:54:38 AM UTC 24 |
| Finished | Oct 03 07:56:36 AM UTC 24 |
| Peak memory | 273032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673214461 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.673214461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.288647933 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 32936947900 ps |
| CPU time | 223.63 seconds |
| Started | Oct 03 07:56:48 AM UTC 24 |
| Finished | Oct 03 08:00:36 AM UTC 24 |
| Peak memory | 305960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=288647933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 5.flash_ctrl_intr_rd_slow_flash.288647933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.2535203333 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 6780310100 ps |
| CPU time | 82.11 seconds |
| Started | Oct 03 07:56:44 AM UTC 24 |
| Finished | Oct 03 07:58:08 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535203333 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.2535203333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2218476469 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 162562160200 ps |
| CPU time | 264.83 seconds |
| Started | Oct 03 07:57:28 AM UTC 24 |
| Finished | Oct 03 08:01:57 AM UTC 24 |
| Peak memory | 275184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218476469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.2218476469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.3419041406 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 6436326600 ps |
| CPU time | 63.91 seconds |
| Started | Oct 03 07:55:27 AM UTC 24 |
| Finished | Oct 03 07:56:33 AM UTC 24 |
| Peak memory | 272972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419041406 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3419041406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.3286941234 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 47845800 ps |
| CPU time | 15.34 seconds |
| Started | Oct 03 07:58:54 AM UTC 24 |
| Finished | Oct 03 07:59:11 AM UTC 24 |
| Peak memory | 275296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3286941234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_lcmgr_intg.3286941234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.1782753171 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 24483988100 ps |
| CPU time | 403.57 seconds |
| Started | Oct 03 07:54:54 AM UTC 24 |
| Finished | Oct 03 08:01:44 AM UTC 24 |
| Peak memory | 283324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=1782753171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.1782753171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.999554439 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 39711200 ps |
| CPU time | 202.34 seconds |
| Started | Oct 03 07:54:45 AM UTC 24 |
| Finished | Oct 03 07:58:11 AM UTC 24 |
| Peak memory | 270880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999554439 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.999554439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.369969064 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1380781800 ps |
| CPU time | 582.56 seconds |
| Started | Oct 03 07:54:37 AM UTC 24 |
| Finished | Oct 03 08:04:26 AM UTC 24 |
| Peak memory | 275148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369969064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.369969064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.3536558611 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 150349500 ps |
| CPU time | 28.2 seconds |
| Started | Oct 03 07:57:35 AM UTC 24 |
| Finished | Oct 03 07:58:04 AM UTC 24 |
| Peak memory | 271164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536558611 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.3536558611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.3873597673 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 456242100 ps |
| CPU time | 1198.06 seconds |
| Started | Oct 03 07:54:37 AM UTC 24 |
| Finished | Oct 03 08:14:48 AM UTC 24 |
| Peak memory | 293516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873597673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.3873597673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.426043770 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 120987600 ps |
| CPU time | 50.17 seconds |
| Started | Oct 03 07:58:09 AM UTC 24 |
| Finished | Oct 03 07:59:01 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426043770 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.426043770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.2158618297 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 541916000 ps |
| CPU time | 139.57 seconds |
| Started | Oct 03 07:55:38 AM UTC 24 |
| Finished | Oct 03 07:58:00 AM UTC 24 |
| Peak memory | 302096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2158618297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.2158618297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.4032605565 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1315555200 ps |
| CPU time | 175.8 seconds |
| Started | Oct 03 07:56:00 AM UTC 24 |
| Finished | Oct 03 07:58:58 AM UTC 24 |
| Peak memory | 306304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=4032605565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash _ctrl_ro_serr.4032605565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.1868186733 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4781722900 ps |
| CPU time | 489.75 seconds |
| Started | Oct 03 07:55:50 AM UTC 24 |
| Finished | Oct 03 08:04:07 AM UTC 24 |
| Peak memory | 330812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868186733 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.1868186733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.809092025 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1196900100 ps |
| CPU time | 178.11 seconds |
| Started | Oct 03 07:56:34 AM UTC 24 |
| Finished | Oct 03 07:59:35 AM UTC 24 |
| Peak memory | 295936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=809092025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.flash_ctrl_rw_derr.809092025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.2943970048 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 31761800 ps |
| CPU time | 52.23 seconds |
| Started | Oct 03 07:58:01 AM UTC 24 |
| Finished | Oct 03 07:58:55 AM UTC 24 |
| Peak memory | 287876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943970048 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.2943970048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.12632130 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 43740400 ps |
| CPU time | 48.16 seconds |
| Started | Oct 03 07:58:05 AM UTC 24 |
| Finished | Oct 03 07:58:55 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=12632130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl _rw_evict_all_en.12632130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.4001495989 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 19500086700 ps |
| CPU time | 213.33 seconds |
| Started | Oct 03 07:56:04 AM UTC 24 |
| Finished | Oct 03 07:59:41 AM UTC 24 |
| Peak memory | 291916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4001495989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.4001495989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.1017569912 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 529422100 ps |
| CPU time | 90.4 seconds |
| Started | Oct 03 07:58:25 AM UTC 24 |
| Finished | Oct 03 07:59:58 AM UTC 24 |
| Peak memory | 275216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017569912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.1017569912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.2629886310 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 26474100 ps |
| CPU time | 272.39 seconds |
| Started | Oct 03 07:54:30 AM UTC 24 |
| Finished | Oct 03 07:59:06 AM UTC 24 |
| Peak memory | 291536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629886310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2629886310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.2442535528 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 26879400 ps |
| CPU time | 25.97 seconds |
| Started | Oct 03 08:48:24 AM UTC 24 |
| Finished | Oct 03 08:48:52 AM UTC 24 |
| Peak memory | 295116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442535528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.2442535528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.869449401 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 16459900 ps |
| CPU time | 24.18 seconds |
| Started | Oct 03 08:48:29 AM UTC 24 |
| Finished | Oct 03 08:48:54 AM UTC 24 |
| Peak memory | 284616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869449401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.869449401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.4223098658 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 147767300 ps |
| CPU time | 180.49 seconds |
| Started | Oct 03 08:48:27 AM UTC 24 |
| Finished | Oct 03 08:51:30 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223098658 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.4223098658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.1882033672 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 24113500 ps |
| CPU time | 26.14 seconds |
| Started | Oct 03 08:48:36 AM UTC 24 |
| Finished | Oct 03 08:49:03 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882033672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1882033672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.1328635848 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 305815200 ps |
| CPU time | 168.21 seconds |
| Started | Oct 03 08:48:29 AM UTC 24 |
| Finished | Oct 03 08:51:20 AM UTC 24 |
| Peak memory | 275704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328635848 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.1328635848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.2580786695 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 16622200 ps |
| CPU time | 25.19 seconds |
| Started | Oct 03 08:48:39 AM UTC 24 |
| Finished | Oct 03 08:49:06 AM UTC 24 |
| Peak memory | 294924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580786695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2580786695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.3257426481 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 78386700 ps |
| CPU time | 164.79 seconds |
| Started | Oct 03 08:48:39 AM UTC 24 |
| Finished | Oct 03 08:51:27 AM UTC 24 |
| Peak memory | 271196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257426481 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.3257426481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.851666572 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 16966500 ps |
| CPU time | 24.74 seconds |
| Started | Oct 03 08:48:43 AM UTC 24 |
| Finished | Oct 03 08:49:09 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851666572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.851666572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.795490606 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 91710900 ps |
| CPU time | 155.17 seconds |
| Started | Oct 03 08:48:40 AM UTC 24 |
| Finished | Oct 03 08:51:18 AM UTC 24 |
| Peak memory | 271136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795490606 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.795490606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.2380341035 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 47119500 ps |
| CPU time | 24.05 seconds |
| Started | Oct 03 08:48:47 AM UTC 24 |
| Finished | Oct 03 08:49:12 AM UTC 24 |
| Peak memory | 284612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380341035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2380341035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.3393916736 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 37733100 ps |
| CPU time | 166.17 seconds |
| Started | Oct 03 08:48:45 AM UTC 24 |
| Finished | Oct 03 08:51:34 AM UTC 24 |
| Peak memory | 275040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393916736 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.3393916736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.2770767569 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 22443300 ps |
| CPU time | 24.77 seconds |
| Started | Oct 03 08:48:49 AM UTC 24 |
| Finished | Oct 03 08:49:15 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770767569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2770767569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.672579052 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 609539400 ps |
| CPU time | 170.53 seconds |
| Started | Oct 03 08:48:48 AM UTC 24 |
| Finished | Oct 03 08:51:42 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672579052 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.672579052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.1086344925 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 13871000 ps |
| CPU time | 21.75 seconds |
| Started | Oct 03 08:48:51 AM UTC 24 |
| Finished | Oct 03 08:49:15 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086344925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1086344925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1655314632 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 52038900 ps |
| CPU time | 157.34 seconds |
| Started | Oct 03 08:48:51 AM UTC 24 |
| Finished | Oct 03 08:51:32 AM UTC 24 |
| Peak memory | 271264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655314632 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.1655314632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.603697715 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 16466200 ps |
| CPU time | 16.23 seconds |
| Started | Oct 03 08:48:52 AM UTC 24 |
| Finished | Oct 03 08:49:11 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603697715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.603697715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.1207191451 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 38785500 ps |
| CPU time | 161.87 seconds |
| Started | Oct 03 08:48:51 AM UTC 24 |
| Finished | Oct 03 08:51:36 AM UTC 24 |
| Peak memory | 271264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207191451 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.1207191451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.700114538 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 19998200 ps |
| CPU time | 24.88 seconds |
| Started | Oct 03 08:48:54 AM UTC 24 |
| Finished | Oct 03 08:49:20 AM UTC 24 |
| Peak memory | 294924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700114538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.700114538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3210584297 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 145709200 ps |
| CPU time | 129.15 seconds |
| Started | Oct 03 08:48:52 AM UTC 24 |
| Finished | Oct 03 08:51:05 AM UTC 24 |
| Peak memory | 270940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210584297 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.3210584297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3064167603 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 60566800 ps |
| CPU time | 26.47 seconds |
| Started | Oct 03 08:03:26 AM UTC 24 |
| Finished | Oct 03 08:03:54 AM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064167603 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3064167603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.255392183 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 27041800 ps |
| CPU time | 25.13 seconds |
| Started | Oct 03 08:02:59 AM UTC 24 |
| Finished | Oct 03 08:03:25 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255392183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.255392183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.3944771296 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 9288830800 ps |
| CPU time | 2990.47 seconds |
| Started | Oct 03 07:59:59 AM UTC 24 |
| Finished | Oct 03 08:50:23 AM UTC 24 |
| Peak memory | 273284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944771296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.3944771296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.999801560 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 311824300 ps |
| CPU time | 1180.41 seconds |
| Started | Oct 03 07:59:42 AM UTC 24 |
| Finished | Oct 03 08:19:35 AM UTC 24 |
| Peak memory | 283348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999801560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/fl ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.999801560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2486723726 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 561471600 ps |
| CPU time | 33.52 seconds |
| Started | Oct 03 07:59:36 AM UTC 24 |
| Finished | Oct 03 08:00:10 AM UTC 24 |
| Peak memory | 273100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24 86723726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetc h_code.2486723726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2093272178 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 10019090500 ps |
| CPU time | 103.65 seconds |
| Started | Oct 03 08:03:22 AM UTC 24 |
| Finished | Oct 03 08:05:08 AM UTC 24 |
| Peak memory | 322412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=2093272178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.2093272178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.2862789429 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 208831200 ps |
| CPU time | 15.89 seconds |
| Started | Oct 03 08:03:19 AM UTC 24 |
| Finished | Oct 03 08:03:36 AM UTC 24 |
| Peak memory | 269184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2862789429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.2862789429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.2289757042 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 200210712300 ps |
| CPU time | 910.02 seconds |
| Started | Oct 03 07:59:12 AM UTC 24 |
| Finished | Oct 03 08:14:33 AM UTC 24 |
| Peak memory | 275048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289757042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.2289757042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.369084007 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 16889807500 ps |
| CPU time | 86.29 seconds |
| Started | Oct 03 07:59:11 AM UTC 24 |
| Finished | Oct 03 08:00:39 AM UTC 24 |
| Peak memory | 271180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369084007 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.369084007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.2025116432 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1533411400 ps |
| CPU time | 190.38 seconds |
| Started | Oct 03 08:01:54 AM UTC 24 |
| Finished | Oct 03 08:05:07 AM UTC 24 |
| Peak memory | 306292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025116432 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.2025116432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.5348575 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 26436900700 ps |
| CPU time | 315.71 seconds |
| Started | Oct 03 08:01:58 AM UTC 24 |
| Finished | Oct 03 08:07:18 AM UTC 24 |
| Peak memory | 302016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=5348575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 6.flash_ctrl_intr_rd_slow_flash.5348575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.183126604 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 7919241400 ps |
| CPU time | 75.44 seconds |
| Started | Oct 03 08:01:57 AM UTC 24 |
| Finished | Oct 03 08:03:14 AM UTC 24 |
| Peak memory | 271368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183126604 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.183126604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1426868288 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 45408009100 ps |
| CPU time | 248.32 seconds |
| Started | Oct 03 08:02:22 AM UTC 24 |
| Finished | Oct 03 08:06:34 AM UTC 24 |
| Peak memory | 275188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426868288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.1426868288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.3751657488 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3109939400 ps |
| CPU time | 102.75 seconds |
| Started | Oct 03 08:00:11 AM UTC 24 |
| Finished | Oct 03 08:01:56 AM UTC 24 |
| Peak memory | 270916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751657488 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3751657488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.1302848891 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 42663000 ps |
| CPU time | 20.45 seconds |
| Started | Oct 03 08:03:15 AM UTC 24 |
| Finished | Oct 03 08:03:37 AM UTC 24 |
| Peak memory | 275404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1302848891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_lcmgr_intg.1302848891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.750733584 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 59470565100 ps |
| CPU time | 1102.72 seconds |
| Started | Oct 03 07:59:20 AM UTC 24 |
| Finished | Oct 03 08:17:57 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=750733584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_mp_regions.750733584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2050607132 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 77126900 ps |
| CPU time | 215.56 seconds |
| Started | Oct 03 07:59:18 AM UTC 24 |
| Finished | Oct 03 08:02:58 AM UTC 24 |
| Peak memory | 270944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050607132 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.2050607132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.2414520871 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1523571600 ps |
| CPU time | 589.36 seconds |
| Started | Oct 03 07:59:07 AM UTC 24 |
| Finished | Oct 03 08:09:03 AM UTC 24 |
| Peak memory | 275144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414520871 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2414520871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.4138974253 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 8254519000 ps |
| CPU time | 173.64 seconds |
| Started | Oct 03 08:02:34 AM UTC 24 |
| Finished | Oct 03 08:05:31 AM UTC 24 |
| Peak memory | 271164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138974253 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.4138974253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.2536669001 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 164890900 ps |
| CPU time | 359.62 seconds |
| Started | Oct 03 07:59:06 AM UTC 24 |
| Finished | Oct 03 08:05:11 AM UTC 24 |
| Peak memory | 291468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536669001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.2536669001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2961967315 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 943977300 ps |
| CPU time | 61.24 seconds |
| Started | Oct 03 08:02:40 AM UTC 24 |
| Finished | Oct 03 08:03:43 AM UTC 24 |
| Peak memory | 287684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961967315 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.2961967315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.302293741 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2216347500 ps |
| CPU time | 157.65 seconds |
| Started | Oct 03 08:00:16 AM UTC 24 |
| Finished | Oct 03 08:02:57 AM UTC 24 |
| Peak memory | 291936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=302293741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.302293741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.2541533430 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3657614500 ps |
| CPU time | 167.86 seconds |
| Started | Oct 03 08:01:36 AM UTC 24 |
| Finished | Oct 03 08:04:27 AM UTC 24 |
| Peak memory | 291848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541533430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2541533430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1373773201 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1314538100 ps |
| CPU time | 112.68 seconds |
| Started | Oct 03 08:00:36 AM UTC 24 |
| Finished | Oct 03 08:02:33 AM UTC 24 |
| Peak memory | 291856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=1373773201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash _ctrl_ro_serr.1373773201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.557381183 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 83303604900 ps |
| CPU time | 533.89 seconds |
| Started | Oct 03 08:00:36 AM UTC 24 |
| Finished | Oct 03 08:09:40 AM UTC 24 |
| Peak memory | 322548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557381183 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.557381183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.134767456 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1381309300 ps |
| CPU time | 179.45 seconds |
| Started | Oct 03 08:01:45 AM UTC 24 |
| Finished | Oct 03 08:04:47 AM UTC 24 |
| Peak memory | 298096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=134767456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.flash_ctrl_rw_derr.134767456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.1223534652 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 44492300 ps |
| CPU time | 44.23 seconds |
| Started | Oct 03 08:02:35 AM UTC 24 |
| Finished | Oct 03 08:03:21 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223534652 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.1223534652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.887741311 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 30404800 ps |
| CPU time | 37.03 seconds |
| Started | Oct 03 08:02:40 AM UTC 24 |
| Finished | Oct 03 08:03:18 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=887741311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctr l_rw_evict_all_en.887741311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1851797484 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1701850200 ps |
| CPU time | 199.13 seconds |
| Started | Oct 03 08:00:41 AM UTC 24 |
| Finished | Oct 03 08:04:04 AM UTC 24 |
| Peak memory | 291828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1851797484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.1851797484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.557393495 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1370412600 ps |
| CPU time | 100.06 seconds |
| Started | Oct 03 08:02:58 AM UTC 24 |
| Finished | Oct 03 08:04:40 AM UTC 24 |
| Peak memory | 275156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557393495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.557393495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.3833806749 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 805677400 ps |
| CPU time | 330.22 seconds |
| Started | Oct 03 07:59:02 AM UTC 24 |
| Finished | Oct 03 08:04:37 AM UTC 24 |
| Peak memory | 289412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833806749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3833806749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.1278135579 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3675512800 ps |
| CPU time | 231.62 seconds |
| Started | Oct 03 08:00:14 AM UTC 24 |
| Finished | Oct 03 08:04:09 AM UTC 24 |
| Peak memory | 271176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1278135579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.1278135579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.2726677944 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 41435600 ps |
| CPU time | 27.69 seconds |
| Started | Oct 03 08:48:57 AM UTC 24 |
| Finished | Oct 03 08:49:26 AM UTC 24 |
| Peak memory | 294924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726677944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.2726677944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.2489439123 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 137259300 ps |
| CPU time | 151.08 seconds |
| Started | Oct 03 08:48:56 AM UTC 24 |
| Finished | Oct 03 08:51:30 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489439123 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.2489439123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.3964276539 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 40845800 ps |
| CPU time | 25.07 seconds |
| Started | Oct 03 08:49:01 AM UTC 24 |
| Finished | Oct 03 08:49:27 AM UTC 24 |
| Peak memory | 284812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964276539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3964276539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.2882694312 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 143805300 ps |
| CPU time | 176.76 seconds |
| Started | Oct 03 08:49:00 AM UTC 24 |
| Finished | Oct 03 08:52:00 AM UTC 24 |
| Peak memory | 273312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882694312 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.2882694312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.2724941520 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 32896500 ps |
| CPU time | 16.32 seconds |
| Started | Oct 03 08:49:04 AM UTC 24 |
| Finished | Oct 03 08:49:22 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724941520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2724941520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.3343865757 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 125931100 ps |
| CPU time | 168.55 seconds |
| Started | Oct 03 08:49:02 AM UTC 24 |
| Finished | Oct 03 08:51:54 AM UTC 24 |
| Peak memory | 273244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343865757 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.3343865757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.3801960931 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 71659900 ps |
| CPU time | 20.59 seconds |
| Started | Oct 03 08:49:06 AM UTC 24 |
| Finished | Oct 03 08:49:28 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801960931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3801960931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.3036557155 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 43823000 ps |
| CPU time | 129.74 seconds |
| Started | Oct 03 08:49:06 AM UTC 24 |
| Finished | Oct 03 08:51:18 AM UTC 24 |
| Peak memory | 271348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036557155 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.3036557155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.3641170474 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 36030800 ps |
| CPU time | 21.55 seconds |
| Started | Oct 03 08:49:10 AM UTC 24 |
| Finished | Oct 03 08:49:33 AM UTC 24 |
| Peak memory | 294920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641170474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3641170474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1778685385 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 64785000 ps |
| CPU time | 179.7 seconds |
| Started | Oct 03 08:49:07 AM UTC 24 |
| Finished | Oct 03 08:52:10 AM UTC 24 |
| Peak memory | 271200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778685385 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.1778685385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.3109300762 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 15652100 ps |
| CPU time | 29.5 seconds |
| Started | Oct 03 08:49:11 AM UTC 24 |
| Finished | Oct 03 08:49:42 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109300762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3109300762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.2734835439 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 468112200 ps |
| CPU time | 164.15 seconds |
| Started | Oct 03 08:49:11 AM UTC 24 |
| Finished | Oct 03 08:51:58 AM UTC 24 |
| Peak memory | 270944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734835439 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.2734835439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.1521998420 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 27104500 ps |
| CPU time | 21.28 seconds |
| Started | Oct 03 08:49:13 AM UTC 24 |
| Finished | Oct 03 08:49:36 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521998420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1521998420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.506254256 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 65399500 ps |
| CPU time | 189.32 seconds |
| Started | Oct 03 08:49:12 AM UTC 24 |
| Finished | Oct 03 08:52:25 AM UTC 24 |
| Peak memory | 271076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506254256 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.506254256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.1100376212 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 15211600 ps |
| CPU time | 18.74 seconds |
| Started | Oct 03 08:49:15 AM UTC 24 |
| Finished | Oct 03 08:49:35 AM UTC 24 |
| Peak memory | 284616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100376212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1100376212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.2092852570 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 126441000 ps |
| CPU time | 167.84 seconds |
| Started | Oct 03 08:49:15 AM UTC 24 |
| Finished | Oct 03 08:52:06 AM UTC 24 |
| Peak memory | 275112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092852570 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.2092852570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.286624782 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 26879900 ps |
| CPU time | 20.29 seconds |
| Started | Oct 03 08:49:17 AM UTC 24 |
| Finished | Oct 03 08:49:38 AM UTC 24 |
| Peak memory | 283804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286624782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.286624782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.4166232084 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 36483500 ps |
| CPU time | 130.71 seconds |
| Started | Oct 03 08:49:17 AM UTC 24 |
| Finished | Oct 03 08:51:30 AM UTC 24 |
| Peak memory | 274312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166232084 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.4166232084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.1768280706 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 39916900 ps |
| CPU time | 22.01 seconds |
| Started | Oct 03 08:49:21 AM UTC 24 |
| Finished | Oct 03 08:49:44 AM UTC 24 |
| Peak memory | 294856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768280706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.1768280706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.854937827 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 244698300 ps |
| CPU time | 160.54 seconds |
| Started | Oct 03 08:49:19 AM UTC 24 |
| Finished | Oct 03 08:52:02 AM UTC 24 |
| Peak memory | 271016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854937827 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.854937827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.3572749596 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 49008700 ps |
| CPU time | 27.39 seconds |
| Started | Oct 03 08:06:46 AM UTC 24 |
| Finished | Oct 03 08:07:14 AM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572749596 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.3572749596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.269947282 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 18785600 ps |
| CPU time | 23.2 seconds |
| Started | Oct 03 08:06:19 AM UTC 24 |
| Finished | Oct 03 08:06:43 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269947282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.269947282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.3304399902 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 16193100 ps |
| CPU time | 38.57 seconds |
| Started | Oct 03 08:06:17 AM UTC 24 |
| Finished | Oct 03 08:06:57 AM UTC 24 |
| Peak memory | 285580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3304399902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_c trl_disable.3304399902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.2564184756 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 14196286000 ps |
| CPU time | 3152.07 seconds |
| Started | Oct 03 08:04:10 AM UTC 24 |
| Finished | Oct 03 08:57:17 AM UTC 24 |
| Peak memory | 278188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564184756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.2564184756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.1766703340 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3124380300 ps |
| CPU time | 1405.94 seconds |
| Started | Oct 03 08:04:07 AM UTC 24 |
| Finished | Oct 03 08:27:49 AM UTC 24 |
| Peak memory | 285588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766703340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1766703340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.325165378 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 6227319200 ps |
| CPU time | 46.06 seconds |
| Started | Oct 03 08:04:04 AM UTC 24 |
| Finished | Oct 03 08:04:52 AM UTC 24 |
| Peak memory | 273296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 5165378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch _code.325165378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3440485817 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 10012611400 ps |
| CPU time | 164.42 seconds |
| Started | Oct 03 08:06:44 AM UTC 24 |
| Finished | Oct 03 08:09:32 AM UTC 24 |
| Peak memory | 369692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3440485817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3440485817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.691309388 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 48938100 ps |
| CPU time | 25.05 seconds |
| Started | Oct 03 08:06:41 AM UTC 24 |
| Finished | Oct 03 08:07:08 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=691309388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7 .flash_ctrl_hw_read_seed_err.691309388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.1371363205 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 160176834000 ps |
| CPU time | 1036.25 seconds |
| Started | Oct 03 08:03:44 AM UTC 24 |
| Finished | Oct 03 08:21:12 AM UTC 24 |
| Peak memory | 273120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371363205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.1371363205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.378592273 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 10069510900 ps |
| CPU time | 197.08 seconds |
| Started | Oct 03 08:03:38 AM UTC 24 |
| Finished | Oct 03 08:06:58 AM UTC 24 |
| Peak memory | 273036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378592273 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.378592273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2889923665 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3183271000 ps |
| CPU time | 196.04 seconds |
| Started | Oct 03 08:04:57 AM UTC 24 |
| Finished | Oct 03 08:08:16 AM UTC 24 |
| Peak memory | 302228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889923665 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.2889923665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.369826302 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 52024808500 ps |
| CPU time | 310.52 seconds |
| Started | Oct 03 08:05:09 AM UTC 24 |
| Finished | Oct 03 08:10:23 AM UTC 24 |
| Peak memory | 301800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=369826302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_intr_rd_slow_flash.369826302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.4097274257 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 5079933100 ps |
| CPU time | 112.94 seconds |
| Started | Oct 03 08:05:09 AM UTC 24 |
| Finished | Oct 03 08:07:04 AM UTC 24 |
| Peak memory | 275256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097274257 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.4097274257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3882026802 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 171591769100 ps |
| CPU time | 330.94 seconds |
| Started | Oct 03 08:05:12 AM UTC 24 |
| Finished | Oct 03 08:10:48 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882026802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3882026802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.1814752294 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 822524300 ps |
| CPU time | 76.91 seconds |
| Started | Oct 03 08:04:11 AM UTC 24 |
| Finished | Oct 03 08:05:30 AM UTC 24 |
| Peak memory | 271176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814752294 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.1814752294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.4052991297 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 47337300 ps |
| CPU time | 25.81 seconds |
| Started | Oct 03 08:06:35 AM UTC 24 |
| Finished | Oct 03 08:07:02 AM UTC 24 |
| Peak memory | 275272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4052991297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_lcmgr_intg.4052991297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.3327423368 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 36594932000 ps |
| CPU time | 315.43 seconds |
| Started | Oct 03 08:03:57 AM UTC 24 |
| Finished | Oct 03 08:09:17 AM UTC 24 |
| Peak memory | 283544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=3327423368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.3327423368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.590505876 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 36874900 ps |
| CPU time | 222.68 seconds |
| Started | Oct 03 08:03:55 AM UTC 24 |
| Finished | Oct 03 08:07:41 AM UTC 24 |
| Peak memory | 273404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590505876 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.590505876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.3220943815 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 2586345800 ps |
| CPU time | 489.01 seconds |
| Started | Oct 03 08:03:37 AM UTC 24 |
| Finished | Oct 03 08:11:51 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220943815 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.3220943815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.355154828 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 8031973200 ps |
| CPU time | 234.11 seconds |
| Started | Oct 03 08:05:31 AM UTC 24 |
| Finished | Oct 03 08:09:29 AM UTC 24 |
| Peak memory | 273208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355154828 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.355154828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.4245161684 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 221581300 ps |
| CPU time | 1297.08 seconds |
| Started | Oct 03 08:03:32 AM UTC 24 |
| Finished | Oct 03 08:25:24 AM UTC 24 |
| Peak memory | 293708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245161684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.4245161684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.1302385900 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1138111700 ps |
| CPU time | 106.14 seconds |
| Started | Oct 03 08:04:27 AM UTC 24 |
| Finished | Oct 03 08:06:16 AM UTC 24 |
| Peak memory | 292040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1302385900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.1302385900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.3239868544 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2555765900 ps |
| CPU time | 153.84 seconds |
| Started | Oct 03 08:04:48 AM UTC 24 |
| Finished | Oct 03 08:07:25 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239868544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.3239868544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.2670346935 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 498370900 ps |
| CPU time | 124.68 seconds |
| Started | Oct 03 08:04:38 AM UTC 24 |
| Finished | Oct 03 08:06:45 AM UTC 24 |
| Peak memory | 292048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=2670346935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash _ctrl_ro_serr.2670346935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.846979987 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 37297000 ps |
| CPU time | 44.39 seconds |
| Started | Oct 03 08:05:32 AM UTC 24 |
| Finished | Oct 03 08:06:18 AM UTC 24 |
| Peak memory | 287604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846979987 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.846979987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.520627443 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 30892900 ps |
| CPU time | 50.25 seconds |
| Started | Oct 03 08:05:48 AM UTC 24 |
| Finished | Oct 03 08:06:40 AM UTC 24 |
| Peak memory | 287680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=520627443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctr l_rw_evict_all_en.520627443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.412862862 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 5105355900 ps |
| CPU time | 176.37 seconds |
| Started | Oct 03 08:04:41 AM UTC 24 |
| Finished | Oct 03 08:07:40 AM UTC 24 |
| Peak memory | 291852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=412862862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.412862862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.25201044 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 776012900 ps |
| CPU time | 104.06 seconds |
| Started | Oct 03 08:06:18 AM UTC 24 |
| Finished | Oct 03 08:08:04 AM UTC 24 |
| Peak memory | 275160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25201044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.25201044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2713356660 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 121273100 ps |
| CPU time | 166.96 seconds |
| Started | Oct 03 08:03:27 AM UTC 24 |
| Finished | Oct 03 08:06:17 AM UTC 24 |
| Peak memory | 287376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713356660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2713356660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.130232768 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1904832900 ps |
| CPU time | 194.92 seconds |
| Started | Oct 03 08:04:23 AM UTC 24 |
| Finished | Oct 03 08:07:42 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =130232768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.130232768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.1637759031 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 161084500 ps |
| CPU time | 23.23 seconds |
| Started | Oct 03 08:49:26 AM UTC 24 |
| Finished | Oct 03 08:49:51 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637759031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1637759031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.1272101811 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 76466700 ps |
| CPU time | 193.39 seconds |
| Started | Oct 03 08:49:23 AM UTC 24 |
| Finished | Oct 03 08:52:40 AM UTC 24 |
| Peak memory | 271456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272101811 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.1272101811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.487531924 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 21649600 ps |
| CPU time | 25.38 seconds |
| Started | Oct 03 08:49:29 AM UTC 24 |
| Finished | Oct 03 08:49:56 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487531924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.487531924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.2138580716 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 165984100 ps |
| CPU time | 152.3 seconds |
| Started | Oct 03 08:49:27 AM UTC 24 |
| Finished | Oct 03 08:52:02 AM UTC 24 |
| Peak memory | 270880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138580716 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.2138580716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.3593692965 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 49963600 ps |
| CPU time | 23.53 seconds |
| Started | Oct 03 08:49:29 AM UTC 24 |
| Finished | Oct 03 08:49:54 AM UTC 24 |
| Peak memory | 284812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593692965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3593692965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.893744859 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 40548800 ps |
| CPU time | 151.24 seconds |
| Started | Oct 03 08:49:29 AM UTC 24 |
| Finished | Oct 03 08:52:03 AM UTC 24 |
| Peak memory | 275192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893744859 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.893744859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.1471376187 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 16668200 ps |
| CPU time | 16.59 seconds |
| Started | Oct 03 08:49:34 AM UTC 24 |
| Finished | Oct 03 08:49:52 AM UTC 24 |
| Peak memory | 294920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471376187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1471376187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.3916497464 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 75923600 ps |
| CPU time | 164.82 seconds |
| Started | Oct 03 08:49:30 AM UTC 24 |
| Finished | Oct 03 08:52:18 AM UTC 24 |
| Peak memory | 273588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916497464 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.3916497464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.3326840201 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 14523600 ps |
| CPU time | 20.4 seconds |
| Started | Oct 03 08:49:36 AM UTC 24 |
| Finished | Oct 03 08:49:58 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326840201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3326840201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3894669715 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 132052100 ps |
| CPU time | 176.78 seconds |
| Started | Oct 03 08:49:36 AM UTC 24 |
| Finished | Oct 03 08:52:36 AM UTC 24 |
| Peak memory | 275296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894669715 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.3894669715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.4071110940 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 46029200 ps |
| CPU time | 19.11 seconds |
| Started | Oct 03 08:49:43 AM UTC 24 |
| Finished | Oct 03 08:50:03 AM UTC 24 |
| Peak memory | 284544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071110940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.4071110940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.3528494403 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 43273700 ps |
| CPU time | 179.05 seconds |
| Started | Oct 03 08:49:38 AM UTC 24 |
| Finished | Oct 03 08:52:41 AM UTC 24 |
| Peak memory | 270880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528494403 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.3528494403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.385791793 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 26241700 ps |
| CPU time | 25.35 seconds |
| Started | Oct 03 08:49:45 AM UTC 24 |
| Finished | Oct 03 08:50:12 AM UTC 24 |
| Peak memory | 284684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385791793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.385791793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.35022341 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 126327700 ps |
| CPU time | 167.26 seconds |
| Started | Oct 03 08:49:43 AM UTC 24 |
| Finished | Oct 03 08:52:33 AM UTC 24 |
| Peak memory | 271036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35022341 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.35022341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.3806602810 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 52517900 ps |
| CPU time | 23.87 seconds |
| Started | Oct 03 08:49:51 AM UTC 24 |
| Finished | Oct 03 08:50:16 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806602810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3806602810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.384604678 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 111017800 ps |
| CPU time | 154.68 seconds |
| Started | Oct 03 08:49:49 AM UTC 24 |
| Finished | Oct 03 08:52:26 AM UTC 24 |
| Peak memory | 271284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384604678 -assert nopostproc +UVM_TE STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.384604678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.3114572478 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 73153500 ps |
| CPU time | 23.72 seconds |
| Started | Oct 03 08:49:53 AM UTC 24 |
| Finished | Oct 03 08:50:18 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114572478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3114572478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.3249619592 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 143724000 ps |
| CPU time | 173.96 seconds |
| Started | Oct 03 08:49:52 AM UTC 24 |
| Finished | Oct 03 08:52:49 AM UTC 24 |
| Peak memory | 271148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249619592 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.3249619592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.1977611236 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 18953900 ps |
| CPU time | 24.04 seconds |
| Started | Oct 03 08:49:56 AM UTC 24 |
| Finished | Oct 03 08:50:22 AM UTC 24 |
| Peak memory | 284680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977611236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.1977611236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1190625637 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 671705200 ps |
| CPU time | 184.54 seconds |
| Started | Oct 03 08:49:54 AM UTC 24 |
| Finished | Oct 03 08:53:02 AM UTC 24 |
| Peak memory | 271092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190625637 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.1190625637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.2544908981 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 249398600 ps |
| CPU time | 24.41 seconds |
| Started | Oct 03 08:10:14 AM UTC 24 |
| Finished | Oct 03 08:10:39 AM UTC 24 |
| Peak memory | 269060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544908981 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.2544908981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.84241214 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 15142300 ps |
| CPU time | 25.4 seconds |
| Started | Oct 03 08:09:55 AM UTC 24 |
| Finished | Oct 03 08:10:22 AM UTC 24 |
| Peak memory | 294928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84241214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.84241214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.1807516803 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 27059800 ps |
| CPU time | 38.28 seconds |
| Started | Oct 03 08:09:33 AM UTC 24 |
| Finished | Oct 03 08:10:13 AM UTC 24 |
| Peak memory | 285560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1807516803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_c trl_disable.1807516803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.2696999767 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2035213100 ps |
| CPU time | 2956.39 seconds |
| Started | Oct 03 08:07:26 AM UTC 24 |
| Finished | Oct 03 08:57:14 AM UTC 24 |
| Peak memory | 273284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696999767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.2696999767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3159234832 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 792647600 ps |
| CPU time | 1495.54 seconds |
| Started | Oct 03 08:07:20 AM UTC 24 |
| Finished | Oct 03 08:32:32 AM UTC 24 |
| Peak memory | 283348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159234832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3159234832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.878492534 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 463626900 ps |
| CPU time | 33.12 seconds |
| Started | Oct 03 08:07:16 AM UTC 24 |
| Finished | Oct 03 08:07:50 AM UTC 24 |
| Peak memory | 273296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87 8492534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch _code.878492534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.45850070 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 10071882400 ps |
| CPU time | 70.76 seconds |
| Started | Oct 03 08:10:12 AM UTC 24 |
| Finished | Oct 03 08:11:25 AM UTC 24 |
| Peak memory | 275208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=45850070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.45850070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1649949472 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 15148000 ps |
| CPU time | 23.46 seconds |
| Started | Oct 03 08:10:08 AM UTC 24 |
| Finished | Oct 03 08:10:33 AM UTC 24 |
| Peak memory | 275212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1649949472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1649949472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.915407753 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 60133001000 ps |
| CPU time | 1005.47 seconds |
| Started | Oct 03 08:07:03 AM UTC 24 |
| Finished | Oct 03 08:24:01 AM UTC 24 |
| Peak memory | 275048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915407753 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.915407753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.46211330 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 11323050900 ps |
| CPU time | 83.79 seconds |
| Started | Oct 03 08:07:01 AM UTC 24 |
| Finished | Oct 03 08:08:27 AM UTC 24 |
| Peak memory | 273288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46211330 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.46211330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1218171487 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 757331900 ps |
| CPU time | 118.91 seconds |
| Started | Oct 03 08:08:17 AM UTC 24 |
| Finished | Oct 03 08:10:18 AM UTC 24 |
| Peak memory | 306100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218171487 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.1218171487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2731885893 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 65190240000 ps |
| CPU time | 416.95 seconds |
| Started | Oct 03 08:08:27 AM UTC 24 |
| Finished | Oct 03 08:15:32 AM UTC 24 |
| Peak memory | 303848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2731885893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_intr_rd_slow_flash.2731885893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3653645165 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 8926283300 ps |
| CPU time | 105.06 seconds |
| Started | Oct 03 08:08:20 AM UTC 24 |
| Finished | Oct 03 08:10:08 AM UTC 24 |
| Peak memory | 271164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653645165 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.3653645165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3547611795 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 78716268700 ps |
| CPU time | 269.48 seconds |
| Started | Oct 03 08:08:49 AM UTC 24 |
| Finished | Oct 03 08:13:22 AM UTC 24 |
| Peak memory | 275196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547611795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3547611795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3787429428 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 880047900 ps |
| CPU time | 70.41 seconds |
| Started | Oct 03 08:07:35 AM UTC 24 |
| Finished | Oct 03 08:08:47 AM UTC 24 |
| Peak memory | 270920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787429428 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3787429428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.334842361 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 32204300 ps |
| CPU time | 18.47 seconds |
| Started | Oct 03 08:10:06 AM UTC 24 |
| Finished | Oct 03 08:10:26 AM UTC 24 |
| Peak memory | 271112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=334842361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_lcmgr_intg.334842361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.905310945 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 10903593500 ps |
| CPU time | 239.39 seconds |
| Started | Oct 03 08:07:08 AM UTC 24 |
| Finished | Oct 03 08:11:11 AM UTC 24 |
| Peak memory | 283336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=905310945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_mp_regions.905310945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.1814904708 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 141602900 ps |
| CPU time | 177.78 seconds |
| Started | Oct 03 08:07:04 AM UTC 24 |
| Finished | Oct 03 08:10:05 AM UTC 24 |
| Peak memory | 271348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814904708 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.1814904708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.2847435971 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1462800600 ps |
| CPU time | 472.29 seconds |
| Started | Oct 03 08:06:59 AM UTC 24 |
| Finished | Oct 03 08:14:57 AM UTC 24 |
| Peak memory | 275336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847435971 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.2847435971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.1836811933 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 50579300 ps |
| CPU time | 20.57 seconds |
| Started | Oct 03 08:09:04 AM UTC 24 |
| Finished | Oct 03 08:09:26 AM UTC 24 |
| Peak memory | 275284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836811933 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.1836811933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.1726764590 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 146952300 ps |
| CPU time | 933.27 seconds |
| Started | Oct 03 08:06:58 AM UTC 24 |
| Finished | Oct 03 08:22:41 AM UTC 24 |
| Peak memory | 293516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726764590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.1726764590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.4069021229 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1740831400 ps |
| CPU time | 126.39 seconds |
| Started | Oct 03 08:07:42 AM UTC 24 |
| Finished | Oct 03 08:09:55 AM UTC 24 |
| Peak memory | 291876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4069021229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.4069021229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.1224353541 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1270200700 ps |
| CPU time | 185.86 seconds |
| Started | Oct 03 08:08:15 AM UTC 24 |
| Finished | Oct 03 08:11:24 AM UTC 24 |
| Peak memory | 291836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224353541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.1224353541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.4191525518 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 5392549000 ps |
| CPU time | 137.66 seconds |
| Started | Oct 03 08:07:52 AM UTC 24 |
| Finished | Oct 03 08:10:12 AM UTC 24 |
| Peak memory | 306368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl + ntb_random_seed=4191525518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_ro_serr.4191525518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.1629801314 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 6872189100 ps |
| CPU time | 536.51 seconds |
| Started | Oct 03 08:07:42 AM UTC 24 |
| Finished | Oct 03 08:16:49 AM UTC 24 |
| Peak memory | 320516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629801314 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.1629801314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3049029806 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1401539700 ps |
| CPU time | 173.62 seconds |
| Started | Oct 03 08:08:16 AM UTC 24 |
| Finished | Oct 03 08:11:12 AM UTC 24 |
| Peak memory | 298012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=3049029806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 8.flash_ctrl_rw_derr.3049029806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.1875588043 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 29502500 ps |
| CPU time | 54.48 seconds |
| Started | Oct 03 08:09:18 AM UTC 24 |
| Finished | Oct 03 08:10:15 AM UTC 24 |
| Peak memory | 285856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875588043 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.1875588043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.3390726634 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 30745300 ps |
| CPU time | 50.35 seconds |
| Started | Oct 03 08:09:27 AM UTC 24 |
| Finished | Oct 03 08:10:18 AM UTC 24 |
| Peak memory | 287640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3390726634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct rl_rw_evict_all_en.3390726634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.269826967 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1682195500 ps |
| CPU time | 196.53 seconds |
| Started | Oct 03 08:08:05 AM UTC 24 |
| Finished | Oct 03 08:11:24 AM UTC 24 |
| Peak memory | 306188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=269826967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.269826967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.2542435654 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3126490100 ps |
| CPU time | 89.08 seconds |
| Started | Oct 03 08:09:40 AM UTC 24 |
| Finished | Oct 03 08:11:11 AM UTC 24 |
| Peak memory | 275156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542435654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02 /flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.2542435654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.3644653713 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 83758300 ps |
| CPU time | 85.47 seconds |
| Started | Oct 03 08:06:47 AM UTC 24 |
| Finished | Oct 03 08:08:14 AM UTC 24 |
| Peak memory | 287364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644653713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3644653713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.716880693 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 11092275900 ps |
| CPU time | 186.17 seconds |
| Started | Oct 03 08:07:41 AM UTC 24 |
| Finished | Oct 03 08:10:54 AM UTC 24 |
| Peak memory | 275260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =716880693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.716880693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.3830037425 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 41587800 ps |
| CPU time | 25.3 seconds |
| Started | Oct 03 08:14:07 AM UTC 24 |
| Finished | Oct 03 08:14:34 AM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830037425 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.3830037425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.2934606662 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 13461400 ps |
| CPU time | 21.7 seconds |
| Started | Oct 03 08:13:44 AM UTC 24 |
| Finished | Oct 03 08:14:07 AM UTC 24 |
| Peak memory | 294924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934606662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2934606662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2919654760 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 10810500 ps |
| CPU time | 37.37 seconds |
| Started | Oct 03 08:13:30 AM UTC 24 |
| Finished | Oct 03 08:14:08 AM UTC 24 |
| Peak memory | 285628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2919654760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c trl_disable.2919654760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3406905673 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 45523802000 ps |
| CPU time | 3375.88 seconds |
| Started | Oct 03 08:10:49 AM UTC 24 |
| Finished | Oct 03 09:07:43 AM UTC 24 |
| Peak memory | 276140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406905673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.3406905673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.1840340923 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 831306600 ps |
| CPU time | 1409.26 seconds |
| Started | Oct 03 08:10:40 AM UTC 24 |
| Finished | Oct 03 08:34:24 AM UTC 24 |
| Peak memory | 285396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840340923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/f lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1840340923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.3238344559 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 860929700 ps |
| CPU time | 26.3 seconds |
| Started | Oct 03 08:10:33 AM UTC 24 |
| Finished | Oct 03 08:11:01 AM UTC 24 |
| Peak memory | 273100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32 38344559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc h_code.3238344559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.890871145 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 10053998500 ps |
| CPU time | 83.2 seconds |
| Started | Oct 03 08:13:50 AM UTC 24 |
| Finished | Oct 03 08:15:15 AM UTC 24 |
| Peak memory | 287792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=890871145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.890871145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.849568576 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 48950500 ps |
| CPU time | 23.51 seconds |
| Started | Oct 03 08:13:48 AM UTC 24 |
| Finished | Oct 03 08:14:13 AM UTC 24 |
| Peak memory | 269032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=849568576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9 .flash_ctrl_hw_read_seed_err.849568576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.3958470628 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 40123573200 ps |
| CPU time | 884.72 seconds |
| Started | Oct 03 08:10:23 AM UTC 24 |
| Finished | Oct 03 08:25:19 AM UTC 24 |
| Peak memory | 274976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958470628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.3958470628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.2075096461 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 3926647800 ps |
| CPU time | 90.63 seconds |
| Started | Oct 03 08:10:21 AM UTC 24 |
| Finished | Oct 03 08:11:54 AM UTC 24 |
| Peak memory | 275092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075096461 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.2075096461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.594870017 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1670437700 ps |
| CPU time | 304.81 seconds |
| Started | Oct 03 08:11:52 AM UTC 24 |
| Finished | Oct 03 08:17:01 AM UTC 24 |
| Peak memory | 293740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594870017 -assert nopostp roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.594870017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2914827407 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 55055057600 ps |
| CPU time | 299.39 seconds |
| Started | Oct 03 08:11:58 AM UTC 24 |
| Finished | Oct 03 08:17:01 AM UTC 24 |
| Peak memory | 301792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s im.tcl +ntb_random_seed=2914827407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_intr_rd_slow_flash.2914827407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.83338324 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 49287726100 ps |
| CPU time | 110.41 seconds |
| Started | Oct 03 08:11:54 AM UTC 24 |
| Finished | Oct 03 08:13:47 AM UTC 24 |
| Peak memory | 271156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83338324 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.83338324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1626771779 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 20085900000 ps |
| CPU time | 239.87 seconds |
| Started | Oct 03 08:12:06 AM UTC 24 |
| Finished | Oct 03 08:16:09 AM UTC 24 |
| Peak memory | 275276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_ buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626771779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1626771779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.223326597 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3366357400 ps |
| CPU time | 58.44 seconds |
| Started | Oct 03 08:10:56 AM UTC 24 |
| Finished | Oct 03 08:11:56 AM UTC 24 |
| Peak memory | 275204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223326597 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.223326597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.2200375508 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 45772800 ps |
| CPU time | 25.15 seconds |
| Started | Oct 03 08:13:45 AM UTC 24 |
| Finished | Oct 03 08:14:12 AM UTC 24 |
| Peak memory | 271172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2200375508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_lcmgr_intg.2200375508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.506556274 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 7245940100 ps |
| CPU time | 441.13 seconds |
| Started | Oct 03 08:10:26 AM UTC 24 |
| Finished | Oct 03 08:17:54 AM UTC 24 |
| Peak memory | 283564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/ dv/tools/sim.tcl +ntb_random_seed=506556274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_mp_regions.506556274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.4185478595 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 35646900 ps |
| CPU time | 165.86 seconds |
| Started | Oct 03 08:10:24 AM UTC 24 |
| Finished | Oct 03 08:13:13 AM UTC 24 |
| Peak memory | 271084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185478595 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.4185478595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2290535398 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 131989500 ps |
| CPU time | 189.82 seconds |
| Started | Oct 03 08:10:19 AM UTC 24 |
| Finished | Oct 03 08:13:32 AM UTC 24 |
| Peak memory | 273088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290535398 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2290535398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.3284000765 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1298762000 ps |
| CPU time | 124.77 seconds |
| Started | Oct 03 08:12:47 AM UTC 24 |
| Finished | Oct 03 08:14:54 AM UTC 24 |
| Peak memory | 273428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284000765 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.3284000765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.1463352384 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 341693900 ps |
| CPU time | 1076.69 seconds |
| Started | Oct 03 08:10:19 AM UTC 24 |
| Finished | Oct 03 08:28:27 AM UTC 24 |
| Peak memory | 293512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463352384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1463352384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.1264316591 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 79363200 ps |
| CPU time | 48.31 seconds |
| Started | Oct 03 08:13:23 AM UTC 24 |
| Finished | Oct 03 08:14:12 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264316591 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.1264316591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.3869734255 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 532686700 ps |
| CPU time | 147.78 seconds |
| Started | Oct 03 08:11:13 AM UTC 24 |
| Finished | Oct 03 08:13:43 AM UTC 24 |
| Peak memory | 302072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3869734255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.3869734255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.3924442030 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 13754281100 ps |
| CPU time | 136.67 seconds |
| Started | Oct 03 08:11:25 AM UTC 24 |
| Finished | Oct 03 08:13:44 AM UTC 24 |
| Peak memory | 291828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924442030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3924442030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1471096455 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 30188440100 ps |
| CPU time | 540.66 seconds |
| Started | Oct 03 08:11:13 AM UTC 24 |
| Finished | Oct 03 08:20:21 AM UTC 24 |
| Peak memory | 324796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471096455 - assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.1471096455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.2408984241 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1513807100 ps |
| CPU time | 186.87 seconds |
| Started | Oct 03 08:11:26 AM UTC 24 |
| Finished | Oct 03 08:14:36 AM UTC 24 |
| Peak memory | 291832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/ hw/dv/tools/sim.tcl +ntb_random_seed=2408984241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/ null -cm_name 9.flash_ctrl_rw_derr.2408984241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2182251960 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 29442200 ps |
| CPU time | 34.5 seconds |
| Started | Oct 03 08:13:13 AM UTC 24 |
| Finished | Oct 03 08:13:49 AM UTC 24 |
| Peak memory | 287676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182251960 -assert nopost proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.2182251960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.2982925393 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 153193600 ps |
| CPU time | 56.55 seconds |
| Started | Oct 03 08:13:15 AM UTC 24 |
| Finished | Oct 03 08:14:14 AM UTC 24 |
| Peak memory | 287704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd _data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2982925393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct rl_rw_evict_all_en.2982925393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.4283203017 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 6944920600 ps |
| CPU time | 274.58 seconds |
| Started | Oct 03 08:11:25 AM UTC 24 |
| Finished | Oct 03 08:16:04 AM UTC 24 |
| Peak memory | 302076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10 00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4283203017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.4283203017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3809992085 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 27151000 ps |
| CPU time | 148.31 seconds |
| Started | Oct 03 08:10:16 AM UTC 24 |
| Finished | Oct 03 08:12:47 AM UTC 24 |
| Peak memory | 287568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809992085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3809992085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.788194959 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 5238048600 ps |
| CPU time | 196.21 seconds |
| Started | Oct 03 08:11:02 AM UTC 24 |
| Finished | Oct 03 08:14:21 AM UTC 24 |
| Peak memory | 275452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode= 1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =788194959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.788194959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest |
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