748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0.720s | 30.562us | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.690s | 31.369us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwrmgr_csr_rw | 0.710s | 22.012us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 1.860s | 289.190us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 0.810s | 110.471us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.220s | 52.746us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.710s | 22.012us | 20 | 20 | 100.00 |
| pwrmgr_csr_aliasing | 0.810s | 110.471us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 103 | 105 | 98.10 | |||
| V2 | wakeup | pwrmgr_wakeup | 1.590s | 256.818us | 50 | 50 | 100.00 |
| V2 | control_clks | pwrmgr_wakeup | 1.590s | 256.818us | 50 | 50 | 100.00 |
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.790s | 97.969us | 46 | 50 | 92.00 |
| pwrmgr_lowpower_invalid | 0.760s | 41.268us | 49 | 50 | 98.00 | ||
| V2 | reset | pwrmgr_reset | 1.220s | 75.202us | 49 | 50 | 98.00 |
| pwrmgr_reset_invalid | 1.040s | 100.151us | 49 | 50 | 98.00 | ||
| V2 | main_power_glitch_reset | pwrmgr_reset | 1.220s | 75.202us | 49 | 50 | 98.00 |
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.590s | 333.435us | 48 | 50 | 96.00 |
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.680s | 275.243us | 49 | 50 | 98.00 |
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.940s | 63.664us | 50 | 50 | 100.00 |
| V2 | stress_all | pwrmgr_stress_all | 9.800s | 2.189ms | 42 | 50 | 84.00 |
| V2 | intr_test | pwrmgr_intr_test | 0.710s | 170.789us | 47 | 50 | 94.00 |
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.710s | 473.757us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.710s | 473.757us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.690s | 31.369us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.710s | 22.012us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 0.810s | 110.471us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.900s | 37.435us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.690s | 31.369us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.710s | 22.012us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 0.810s | 110.471us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.900s | 37.435us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 519 | 540 | 96.11 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.720s | 404.087us | 20 | 20 | 100.00 |
| pwrmgr_sec_cm | 2.020s | 570.954us | 5 | 5 | 100.00 | ||
| V2S | prim_count_check | pwrmgr_sec_cm | 2.020s | 570.954us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | pwrmgr_sec_cm | 2.020s | 570.954us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.720s | 404.087us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 3.960s | 834.974us | 49 | 50 | 98.00 |
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 4.140s | 767.627us | 49 | 50 | 98.00 |
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.930s | 71.891us | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.700s | 29.498us | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.020s | 570.954us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.020s | 570.954us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.020s | 570.954us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.680s | 33.389us | 49 | 50 | 98.00 |
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.700s | 41.193us | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.730s | 196.620us | 48 | 50 | 96.00 |
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.710s | 22.012us | 20 | 20 | 100.00 |
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.710s | 22.012us | 20 | 20 | 100.00 |
| V2S | TOTAL | 367 | 375 | 97.87 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 1.070s | 683.189us | 48 | 50 | 96.00 |
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 31.230s | 6.683ms | 31 | 50 | 62.00 |
| V3 | TOTAL | 79 | 100 | 79.00 | |||
| TOTAL | 1068 | 1120 | 95.36 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 12 | 12 | 4 | 33.33 |
| V2S | 9 | 9 | 2 | 22.22 |
| V3 | 2 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.92 | 98.22 | 96.58 | 99.44 | 96.00 | 96.32 | 100.00 | 98.85 |
Exit reason: Error: User command failed Job returned non-zero exit code has 28 failures:
Test pwrmgr_intr_test has 3 failures.
2.pwrmgr_intr_test.42670099059954242416518155714039275912634089793363689709057851757626566810853
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_intr_test/latest/run.log
[make]: simulate
cd /workspace/2.pwrmgr_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449986277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.3449986277
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
7.pwrmgr_intr_test.85354020899319790369973370744066672168655113696252368546557122447837588158920
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest/run.log
[make]: simulate
cd /workspace/7.pwrmgr_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898852296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2898852296
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test pwrmgr_stress_all has 2 failures.
24.pwrmgr_stress_all.72926528366875296254007986355548392144370563388371859993419212749506318561158
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest/run.log
[make]: simulate
cd /workspace/24.pwrmgr_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955458950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.1955458950
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
27.pwrmgr_stress_all.102993510403611125296079594876496004091686420942024065679355883346823159317396
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest/run.log
[make]: simulate
cd /workspace/27.pwrmgr_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585991060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.585991060
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr_sec_cm_ctrl_config_regwen has 2 failures.
27.pwrmgr_sec_cm_ctrl_config_regwen.100170167634908960749496408775937900347561683900374960842739643894520243736573
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
[make]: simulate
cd /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest && /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084832765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.3084832765
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
31.pwrmgr_sec_cm_ctrl_config_regwen.50731654934621852488892203886323696651872124419272147398363501603965293089107
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
[make]: simulate
cd /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest && /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136972115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.1136972115
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr_esc_clk_rst_malfunc has 1 failures.
28.pwrmgr_esc_clk_rst_malfunc.113988744240621769372935709099023384642779836651937763987411397096582688727512
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_esc_clk_rst_malfunc/latest/run.log
[make]: simulate
cd /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest && /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290096088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_malfunc.3290096088
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr_global_esc has 1 failures.
30.pwrmgr_global_esc.54093205394000391508547408439120814339299545296815192993713150228919265303684
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest/run.log
[make]: simulate
cd /workspace/30.pwrmgr_global_esc/latest && /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267426948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.267426948
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 13 more tests.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 24 failures:
0.pwrmgr_stress_all_with_rand_reset.59673023121452939761133234377227161881322233353785214988228458844667573654712
Line 1051, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2464158607 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 2464158607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_stress_all_with_rand_reset.44652286295237487300912252764247302119732214946496674830667071035445611614440
Line 3375, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1412552794 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 1412552794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
0.pwrmgr_stress_all.107363291386049522734925854919261912613260097457266716681456547749094292232041
Line 292, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 75436658 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 75436658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_stress_all.19946070743668299181952649165118228324151434664328109134496641231419238101352
Line 299, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 155340693 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 155340693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
4.pwrmgr_aborted_low_power.70050108642944008207654685393983814172147857420845194438331675643980626878238
Line 285, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_aborted_low_power/latest/run.log
UVM_ERROR @ 37415422 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 37415422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.pwrmgr_aborted_low_power.83881935155931202643195026363579371746406193546309241421252794341219282728853
Line 281, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_aborted_low_power/latest/run.log
UVM_ERROR @ 95707346 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 95707346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---