042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0.720s | 29.174us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.650s | 34.440us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwrmgr_csr_rw | 0.750s | 28.212us | 13 | 20 | 65.00 |
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.230s | 326.257us | 4 | 5 | 80.00 |
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 0.970s | 186.536us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.440s | 60.095us | 17 | 20 | 85.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.750s | 28.212us | 13 | 20 | 65.00 |
| pwrmgr_csr_aliasing | 0.970s | 186.536us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 94 | 105 | 89.52 | |||
| V2 | wakeup | pwrmgr_wakeup | 1.640s | 240.746us | 49 | 50 | 98.00 |
| V2 | control_clks | pwrmgr_wakeup | 1.640s | 240.746us | 49 | 50 | 98.00 |
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.830s | 59.072us | 42 | 50 | 84.00 |
| pwrmgr_lowpower_invalid | 0.750s | 41.867us | 50 | 50 | 100.00 | ||
| V2 | reset | pwrmgr_reset | 1.140s | 58.395us | 50 | 50 | 100.00 |
| pwrmgr_reset_invalid | 1.080s | 109.071us | 50 | 50 | 100.00 | ||
| V2 | main_power_glitch_reset | pwrmgr_reset | 1.140s | 58.395us | 50 | 50 | 100.00 |
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.710s | 277.047us | 50 | 50 | 100.00 |
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.560s | 246.546us | 50 | 50 | 100.00 |
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.940s | 67.009us | 50 | 50 | 100.00 |
| V2 | stress_all | pwrmgr_stress_all | 7.750s | 2.293ms | 43 | 50 | 86.00 |
| V2 | intr_test | pwrmgr_intr_test | 0.680s | 27.626us | 42 | 50 | 84.00 |
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.380s | 464.741us | 15 | 20 | 75.00 |
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.380s | 464.741us | 15 | 20 | 75.00 |
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.650s | 34.440us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.750s | 28.212us | 13 | 20 | 65.00 | ||
| pwrmgr_csr_aliasing | 0.970s | 186.536us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.930s | 45.068us | 16 | 20 | 80.00 | ||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.650s | 34.440us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.750s | 28.212us | 13 | 20 | 65.00 | ||
| pwrmgr_csr_aliasing | 0.970s | 186.536us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.930s | 45.068us | 16 | 20 | 80.00 | ||
| V2 | TOTAL | 507 | 540 | 93.89 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.640s | 210.302us | 15 | 20 | 75.00 |
| pwrmgr_sec_cm | 2.080s | 636.312us | 5 | 5 | 100.00 | ||
| V2S | prim_count_check | pwrmgr_sec_cm | 2.080s | 636.312us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | pwrmgr_sec_cm | 2.080s | 636.312us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.640s | 210.302us | 15 | 20 | 75.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 3.970s | 841.716us | 49 | 50 | 98.00 |
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 4.110s | 844.543us | 50 | 50 | 100.00 |
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 1.000s | 67.259us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.680s | 29.124us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.080s | 636.312us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.080s | 636.312us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.080s | 636.312us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.710s | 85.134us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.700s | 48.091us | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.810s | 283.209us | 50 | 50 | 100.00 |
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.750s | 28.212us | 13 | 20 | 65.00 |
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.750s | 28.212us | 13 | 20 | 65.00 |
| V2S | TOTAL | 369 | 375 | 98.40 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 1.030s | 161.453us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 44.030s | 9.054ms | 34 | 50 | 68.00 |
| V3 | TOTAL | 84 | 100 | 84.00 | |||
| TOTAL | 1054 | 1120 | 94.11 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 3 | 50.00 |
| V2 | 12 | 12 | 6 | 50.00 |
| V2S | 9 | 9 | 7 | 77.78 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.94 | 98.22 | 96.58 | 99.44 | 96.00 | 96.32 | 100.00 | 99.02 |
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 32 failures:
Test pwrmgr_stress_all_with_rand_reset has 16 failures.
0.pwrmgr_stress_all_with_rand_reset.82785082161956780398047920073941676214698244166571118065306253065134398695873
Line 3582, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3688639683 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 3688639683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_stress_all_with_rand_reset.11022537951277817436841060179412894237350574621774189682871276293173864614528
Line 730, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 702872856 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 702872856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
Test pwrmgr_wakeup has 1 failures.
7.pwrmgr_wakeup.75660138080649612502887229758248456858231362772670251740648514700828251832367
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 42981855 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 42981855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwrmgr_aborted_low_power has 8 failures.
7.pwrmgr_aborted_low_power.93458440015055465423922318716285853977117249866104936047799468252351702105718
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest/run.log
UVM_ERROR @ 144391309 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 144391309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pwrmgr_aborted_low_power.80994848032094610489132323224175377974863869088800321601779132119118647950965
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest/run.log
UVM_ERROR @ 47606053 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 47606053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test pwrmgr_stress_all has 7 failures.
13.pwrmgr_stress_all.48922233545268186276480596164590673680659206574344585409201977096491479176284
Line 1478, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 1590094236 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 1590094236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.pwrmgr_stress_all.66467211763362954361545404576248269477224527506928162411008349597021028487330
Line 870, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 498672206 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
UVM_INFO @ 498672206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 28 failures:
Test pwrmgr_csr_bit_bash has 1 failures.
0.pwrmgr_csr_bit_bash.1353403928708784109925627150182861168179890190760832531641681072212916959830
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/0.pwrmgr_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479328854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.479328854
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test pwrmgr_csr_mem_rw_with_rand_reset has 3 failures.
1.pwrmgr_csr_mem_rw_with_rand_reset.91263874931065033734296738222493391140233814692927742681075939943571885843100
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608601244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.3608601244
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
6.pwrmgr_csr_mem_rw_with_rand_reset.28765494035729529913503471289905260324409197257029808318515896279390810458878
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840171774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.1840171774
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test pwrmgr_tl_errors has 3 failures.
2.pwrmgr_tl_errors.64718974194096252147735032533715231955274220052717735554582345553836298746387
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest/run.log
[make]: simulate
cd /workspace/2.pwrmgr_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046048787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.2046048787
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
14.pwrmgr_tl_errors.6305129175449083896678432307246115278817622143194108556490067208369974369038
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest/run.log
[make]: simulate
cd /workspace/14.pwrmgr_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864981262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1864981262
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:34 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test pwrmgr_tl_intg_err has 4 failures.
8.pwrmgr_tl_intg_err.81659176420593138296267493193691536756064086307693812578350399851445914756053
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/8.pwrmgr_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024072149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.2024072149
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
14.pwrmgr_tl_intg_err.90820208395240949837814896739227739865168636349230791080583185858072486924405
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/14.pwrmgr_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465517685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.2465517685
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:34 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 2 more failures.
Test pwrmgr_same_csr_outstanding has 3 failures.
9.pwrmgr_same_csr_outstanding.104948715467509522966990724384865234217579245236698836001312908667736136160603
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/9.pwrmgr_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331421019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.331421019
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
11.pwrmgr_same_csr_outstanding.34698642622665097805736629245701472935880214115628966704035335781900725434956
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/11.pwrmgr_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473245260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.2473245260
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:31 2024
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make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
... and 2 more tests.
Job pwrmgr-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
Test pwrmgr_tl_errors has 2 failures.
5.pwrmgr_tl_errors.105787217581537985876881067564990630921169601726752649441950628125200779516315
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest/run.log
Job ID: smart:2f31ec01-7fc4-4241-83f1-737ca66dac1a
9.pwrmgr_tl_errors.25527440557457005726059706927431114564700001478465043097782311557767592788815
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest/run.log
Job ID: smart:f812f5c0-028f-4573-b829-4b5989bc2654
Test pwrmgr_csr_rw has 1 failures.
5.pwrmgr_csr_rw.21324050061857099351608045125197652183806184928014012592777905538246826889677
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest/run.log
Job ID: smart:0d7283d0-cd21-402c-abdc-c0383d15a393
Test pwrmgr_same_csr_outstanding has 1 failures.
8.pwrmgr_same_csr_outstanding.20550749643419055340303163080371701510384993823663619469599997062945463407555
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest/run.log
Job ID: smart:86adac34-97d2-4146-b8de-b75cd726a9fd
Test pwrmgr_tl_intg_err has 1 failures.
11.pwrmgr_tl_intg_err.27857231926553672632548816959786906897247052764910717857721592698342597365331
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest/run.log
Job ID: smart:86d6f690-8256-4d78-ab0f-831e63718054
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.70377689668073049123577515355622160825563123620661472375775048457348000956997
Line 633, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---