PWRMGR Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	30.592us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	46.223us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.760s	19.703us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.330s	826.817us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.030s	179.105us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.160s	50.233us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.760s	19.703us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	179.105us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.670s	250.305us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.670s	250.305us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.870s	61.350us	47	50	94.00
		pwrmgr_lowpower_invalid	0.780s	46.875us	50	50	100.00
V2	reset	pwrmgr_reset	1.440s	89.947us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	106.369us	49	50	98.00
V2	main_power_glitch_reset	pwrmgr_reset	1.440s	89.947us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.710s	290.884us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.770s	286.426us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.030s	67.932us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.010s	1.812ms	48	50	96.00
V2	intr_test	pwrmgr_intr_test	0.690s	16.966us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.500s	48.800us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.500s	48.800us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	46.223us	5	5	100.00
		pwrmgr_csr_rw	0.760s	19.703us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	179.105us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	47.164us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	46.223us	5	5	100.00
		pwrmgr_csr_rw	0.760s	19.703us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	179.105us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.970s	47.164us	20	20	100.00
V2		TOTAL			534	540	98.89
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.660s	218.637us	20	20	100.00
		pwrmgr_sec_cm	1.600s	763.219us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.600s	763.219us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.600s	763.219us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.660s	218.637us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.490s	789.922us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.510s	824.241us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	69.742us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	38.444us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.600s	763.219us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.600s	763.219us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.600s	763.219us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	47.572us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	53.997us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.740s	280.974us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.760s	19.703us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.760s	19.703us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.100s	162.495us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	47.780s	11.009ms	30	50	60.00
V3		TOTAL			79	100	79.00
		TOTAL			1093	1120	97.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 25 failures:

Test pwrmgr_stress_all_with_rand_reset has 20 failures.

0.pwrmgr_stress_all_with_rand_reset.37389613241677060940434277041807492838554436557211343646410051552117954771050
Line 3937, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3769841385 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 3769841385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_stress_all_with_rand_reset.90006253453895727406996612835961461603195902746087380255360992318316102579037
Line 6425, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7895404078 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 7895404078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Test pwrmgr_aborted_low_power has 3 failures.

1.pwrmgr_aborted_low_power.114839718878671950769218037865452090121204994851967550111793656087368558628929
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  41473983 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  41473983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.pwrmgr_aborted_low_power.14759973025041477923039091093136752168524214849540012342437745599118482678334
Line 283, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @ 103256419 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 103256419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test pwrmgr_stress_all has 2 failures.

22.pwrmgr_stress_all.6904043019678970645322033696151599853239523650752895093678223810090025826368
Line 618, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 1068562103 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 1068562103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.pwrmgr_stress_all.55952202122793473460229681618072424967916363441550413263045857001297660551595
Line 745, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 1052715222 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 1052715222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 10.pwrmgr_escalation_timeout.99809121801298867509719855203907482248096629850171732841094580875012120839865
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_FATAL @ 1722179926 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
  UVM_INFO @ 1722179926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:
- Test pwrmgr_reset_invalid has 1 failures.
  - 31.pwrmgr_reset_invalid.103518054189744411581904629229292105910412624806789678816714201329123812577333
    Line 270, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest/run.log
```
      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 158317579 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 158317579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```