PWRMGR Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.720s	35.927us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	69.900us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	49.161us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.690s	1.221ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.030s	90.635us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.580s	128.415us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	49.161us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	90.635us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.490s	306.552us	49	50	98.00
V2	control_clks	pwrmgr_wakeup	1.490s	306.552us	49	50	98.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.850s	35.951us	45	50	90.00
		pwrmgr_lowpower_invalid	0.820s	46.129us	50	50	100.00
V2	reset	pwrmgr_reset	1.450s	91.308us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	105.627us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.450s	91.308us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.780s	278.515us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.600s	268.517us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.040s	54.215us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.680s	1.793ms	43	50	86.00
V2	intr_test	pwrmgr_intr_test	0.680s	19.164us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.400s	47.539us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.400s	47.539us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	69.900us	5	5	100.00
		pwrmgr_csr_rw	0.700s	49.161us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	90.635us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	133.247us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	69.900us	5	5	100.00
		pwrmgr_csr_rw	0.700s	49.161us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	90.635us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	133.247us	20	20	100.00
V2		TOTAL			527	540	97.59
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.690s	217.410us	20	20	100.00
		pwrmgr_sec_cm	2.110s	678.459us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.110s	678.459us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.110s	678.459us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.690s	217.410us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.010s	907.336us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.670s	789.046us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	70.756us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	38.589us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.110s	678.459us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.110s	678.459us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.110s	678.459us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	96.844us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	40.034us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.720s	234.549us	49	50	98.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	49.161us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	49.161us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	692.514us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	39.370s	8.346ms	25	50	50.00
V3		TOTAL			74	100	74.00
		TOTAL			1080	1120	96.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	9	8	88.89
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 39 failures:

Test pwrmgr_aborted_low_power has 5 failures.

0.pwrmgr_aborted_low_power.35459136207165457415295792785273510357001757934370486812025746448571100240970
Line 269, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  16433819 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  16433819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.pwrmgr_aborted_low_power.83757641391016550927202801928012858106920746893983897271112273645922693582035
Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  43771514 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  43771514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test pwrmgr_stress_all_with_rand_reset has 25 failures.

0.pwrmgr_stress_all_with_rand_reset.32295607337158674162395582553709832248995451599599211021895558910560850568459
Line 5853, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7936667701 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 7936667701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_stress_all_with_rand_reset.21894780487943397908683470731835456087586211557984252702557423399876065419716
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  18852955 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  18852955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.

Test pwrmgr_stress_all has 7 failures.

0.pwrmgr_stress_all.24938101526985411654617669562844267321252775218803020350569694908650294029799
Line 731, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 1858426048 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 1858426048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwrmgr_stress_all.56887307427389373172867621117235031448773749609249174459100835002064904358110
Line 1875, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 2279594503 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 2279594503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test pwrmgr_wakeup has 1 failures.

5.pwrmgr_wakeup.106711026056931391403526256353431753483609017205355714856892316380189468760707
Line 255, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest/run.log

  UVM_ERROR @  26065248 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  26065248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwrmgr_sec_cm_ctrl_config_regwen has 1 failures.
- 40.pwrmgr_sec_cm_ctrl_config_regwen.46561670933754323608219385089215269927341605673427720048858407909462594816609
  Line 274, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  95267206 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  95267206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 27.pwrmgr_escalation_timeout.104688174748440436995426221139096707267472023856126616994146527908866241774649
    Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest/run.log
```
      Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
  UVM_ERROR @  98023984 ps: (pwrmgr.sv:173) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
  UVM_INFO @  98023984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```