PWRMGR Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	32.160us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	30.442us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	20.617us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.440s	322.758us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.060s	45.483us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.380s	53.693us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	20.617us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	45.483us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.450s	189.119us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.450s	189.119us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.880s	39.704us	44	50	88.00
		pwrmgr_lowpower_invalid	0.860s	38.230us	50	50	100.00
V2	reset	pwrmgr_reset	1.280s	76.046us	50	50	100.00
		pwrmgr_reset_invalid	1.120s	95.470us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.280s	76.046us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.900s	313.331us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.590s	257.674us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.900s	59.561us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.700s	2.355ms	46	50	92.00
V2	intr_test	pwrmgr_intr_test	0.690s	45.490us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.530s	56.721us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.530s	56.721us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	30.442us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.617us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	45.483us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	71.469us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	30.442us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.617us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	45.483us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	71.469us	20	20	100.00
V2		TOTAL			530	540	98.15
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.750s	215.105us	20	20	100.00
		pwrmgr_sec_cm	1.920s	611.846us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.920s	611.846us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.920s	611.846us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.750s	215.105us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.280s	850.294us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.460s	862.585us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	155.470us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	29.629us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.920s	611.846us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.920s	611.846us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.920s	611.846us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.660s	55.805us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.790s	61.000us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.740s	241.364us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	20.617us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	20.617us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.220s	247.423us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	41.140s	9.568ms	33	50	66.00
V3		TOTAL			82	100	82.00
		TOTAL			1092	1120	97.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 27 failures:

Test pwrmgr_stress_all_with_rand_reset has 17 failures.

0.pwrmgr_stress_all_with_rand_reset.115683061297555890977078003642032941594831130870278829860996475677606883976835
Line 2849, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2772002421 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 2772002421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwrmgr_stress_all_with_rand_reset.11452467596541826351219478402930091622373256992004737085196960939612556885002
Line 3710, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2580112055 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 2580112055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

Test pwrmgr_stress_all has 4 failures.

0.pwrmgr_stress_all.71598690189348682076954632527595009504377187036443510590452160840085573907737
Line 275, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  25055346 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  25055346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.pwrmgr_stress_all.82690005315512359593866936237960087948146551473289069095886281218276331616494
Line 546, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 473334857 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 473334857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test pwrmgr_aborted_low_power has 6 failures.

7.pwrmgr_aborted_low_power.63271555669826301575162159526153328395543199945371728115148151369182212174543
Line 271, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  56282697 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  56282697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.pwrmgr_aborted_low_power.36679880827886303935295630626990092686531802795845393907611855879320133909708
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  20352418 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  20352418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 31.pwrmgr_escalation_timeout.25609063054182307162823569013015759257921696432119801599635528538384410525409
    Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest/run.log
```
      Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
  UVM_ERROR @ 103068903 ps: (pwrmgr.sv:173) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
  UVM_INFO @ 103068903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```