PWRMGR Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.780s	31.506us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	44.661us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	19.719us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.410s	402.437us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.070s	51.058us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.460s	136.723us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	19.719us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	51.058us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.740s	288.627us	49	50	98.00
V2	control_clks	pwrmgr_wakeup	1.740s	288.627us	49	50	98.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.880s	31.173us	47	50	94.00
		pwrmgr_lowpower_invalid	0.800s	42.458us	50	50	100.00
V2	reset	pwrmgr_reset	1.210s	62.228us	50	50	100.00
		pwrmgr_reset_invalid	1.250s	96.719us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.210s	62.228us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.790s	308.551us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.490s	186.389us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.010s	67.669us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	9.450s	1.871ms	45	50	90.00
V2	intr_test	pwrmgr_intr_test	0.680s	19.779us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.610s	139.585us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.610s	139.585us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	44.661us	5	5	100.00
		pwrmgr_csr_rw	0.730s	19.719us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	51.058us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	46.956us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	44.661us	5	5	100.00
		pwrmgr_csr_rw	0.730s	19.719us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	51.058us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	46.956us	20	20	100.00
V2		TOTAL			530	540	98.15
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.730s	557.508us	20	20	100.00
		pwrmgr_sec_cm	2.110s	633.580us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.110s	633.580us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.110s	633.580us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.730s	557.508us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.410s	790.465us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.330s	919.795us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.040s	75.502us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	30.314us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.110s	633.580us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.110s	633.580us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.110s	633.580us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	60.780us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.750s	62.674us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.750s	314.348us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	19.719us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	19.719us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	167.305us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	51.970s	11.741ms	34	50	68.00
V3		TOTAL			83	100	83.00
		TOTAL			1093	1120	97.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	8	66.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 25 failures:

Test pwrmgr_stress_all_with_rand_reset has 16 failures.

0.pwrmgr_stress_all_with_rand_reset.108782014410508535258169574842749952458606119752453831352136232986290052301021
Line 3752, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6909252681 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 6909252681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.pwrmgr_stress_all_with_rand_reset.49887977133632750810047111380759435426583119098529597948973131480933388476438
Line 514, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 569522626 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 569522626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

Test pwrmgr_aborted_low_power has 3 failures.

14.pwrmgr_aborted_low_power.57490905083963102399233260122249623021430799273555169282022010109849279384107
Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  21094302 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  21094302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.pwrmgr_aborted_low_power.27119600343795923397979392785962716224632955962902053844186957441086030782965
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  51513974 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  51513974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test pwrmgr_lowpower_wakeup_race has 1 failures.
- 31.pwrmgr_lowpower_wakeup_race.114133364091181373387278572501810720874137755291000241582269881607931739113643
  Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest/run.log
```
  UVM_ERROR @  39849138 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  39849138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test pwrmgr_stress_all has 4 failures.

43.pwrmgr_stress_all.17537052215010852265238870286676438963493634753305845575685808049158271523891
Line 952, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 780252308 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 780252308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.pwrmgr_stress_all.64709927073897007323333908910623798547046118354810138612077006765493747343475
Line 343, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 150891394 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 150891394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test pwrmgr_wakeup has 1 failures.

48.pwrmgr_wakeup.25289345782730306235066820662404449356270730547106117301240791108430939756075
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest/run.log

  UVM_ERROR @  47108086 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  47108086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' has 1 failures:
- Test pwrmgr_stress_all has 1 failures.
  - 15.pwrmgr_stress_all.79764351621116581286527391556933845311595230236127780695002231238596873837791
    Line 336, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest/run.log
```
      Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]'
  UVM_ERROR @ 474200858 ps: (pwrmgr_sec_cm_checker_assert.sv:128) [ASSERT FAILED] RstreqChkMainpd_A
  UVM_INFO @ 474200858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 35.pwrmgr_escalation_timeout.12738731362063680811721504249810289421004115043832616508276255382741079639644
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_FATAL @ 1723301087 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
  UVM_INFO @ 1723301087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```