PWRMGR Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	33.073us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	61.675us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	23.497us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.510s	313.218us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.040s	82.173us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.530s	58.830us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	23.497us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	82.173us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.460s	222.773us	49	50	98.00
V2	control_clks	pwrmgr_wakeup	1.460s	222.773us	49	50	98.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.820s	95.056us	48	50	96.00
		pwrmgr_lowpower_invalid	0.810s	42.258us	50	50	100.00
V2	reset	pwrmgr_reset	1.380s	82.053us	50	50	100.00
		pwrmgr_reset_invalid	1.130s	108.604us	49	50	98.00
V2	main_power_glitch_reset	pwrmgr_reset	1.380s	82.053us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.770s	254.706us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.600s	264.414us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.970s	66.436us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.740s	1.986ms	40	50	80.00
V2	intr_test	pwrmgr_intr_test	0.690s	41.611us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.640s	822.720us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.640s	822.720us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	61.675us	5	5	100.00
		pwrmgr_csr_rw	0.730s	23.497us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	82.173us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	50.252us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	61.675us	5	5	100.00
		pwrmgr_csr_rw	0.730s	23.497us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	82.173us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.980s	50.252us	20	20	100.00
V2		TOTAL			525	540	97.22
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.140s	393.308us	20	20	100.00
		pwrmgr_sec_cm	1.480s	922.165us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.480s	922.165us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.480s	922.165us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.140s	393.308us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.030s	813.536us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.490s	838.319us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	74.523us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.660s	38.861us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.480s	922.165us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.480s	922.165us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.480s	922.165us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	52.155us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	56.324us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.850s	312.010us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	23.497us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	23.497us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	618.221us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	33.990s	10.220ms	30	50	60.00
V3		TOTAL			80	100	80.00
		TOTAL			1084	1120	96.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	7	58.33
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 33 failures:

Test pwrmgr_wakeup has 1 failures.

0.pwrmgr_wakeup.37872909719287205450919394121374233384229745010218843183243536833824039501092
Line 286, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log

  UVM_ERROR @  22834055 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  22834055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwrmgr_stress_all_with_rand_reset has 20 failures.

0.pwrmgr_stress_all_with_rand_reset.68256981155645933601829061796743348833111086124442842317843792664384210180555
Line 1114, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2360658078 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 2360658078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_stress_all_with_rand_reset.83414572068053363302468179560466033361881332579703530021528709918266835628317
Line 1000, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1963196168 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 1963196168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Test pwrmgr_stress_all has 10 failures.

2.pwrmgr_stress_all.60804164456414591770599241578184288595989859709756130893044334475653903885013
Line 359, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  80292537 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  80292537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwrmgr_stress_all.49424064681547992573567515590013292504773352861594523561502983725011059565076
Line 287, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 345407705 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 345407705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test pwrmgr_aborted_low_power has 2 failures.

6.pwrmgr_aborted_low_power.101037099659248402139561205143619235803005536448824485967312041181476030042446
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  14349170 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  14349170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.pwrmgr_aborted_low_power.10765891927733459803711820543316263422763458663823647617861734673571095835975
Line 287, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  15941908 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  15941908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test pwrmgr_wakeup_reset has 1 failures.
  - 31.pwrmgr_wakeup_reset.38034738680461341424223592792770647226289572258027104693509342580921051240784
    Line 392, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest/run.log
```
  UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.
  - 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.64109663777370338203400269302255628540064747916440358099206883858798637524953
    Line 636, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
```
  UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:
- Test pwrmgr_reset_invalid has 1 failures.
  - 5.pwrmgr_reset_invalid.60359691142792361211048424723717419133954704112593237642591520581800430926191
    Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest/run.log
```
      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 160787144 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 160787144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```