PWRMGR Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	28.535us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	24.749us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	19.511us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.730s	146.618us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.990s	49.372us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.520s	57.544us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	19.511us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	49.372us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.550s	213.182us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.550s	213.182us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.820s	24.177us	48	50	96.00
		pwrmgr_lowpower_invalid	0.840s	45.792us	50	50	100.00
V2	reset	pwrmgr_reset	1.310s	82.819us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	112.376us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.310s	82.819us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.730s	310.961us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.760s	264.901us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.940s	74.531us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	13.610s	2.937ms	43	50	86.00
V2	intr_test	pwrmgr_intr_test	0.670s	18.350us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.600s	55.976us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.600s	55.976us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	24.749us	5	5	100.00
		pwrmgr_csr_rw	0.700s	19.511us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	49.372us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	45.649us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	24.749us	5	5	100.00
		pwrmgr_csr_rw	0.700s	19.511us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	49.372us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	45.649us	20	20	100.00
V2		TOTAL			530	540	98.15
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.620s	363.798us	20	20	100.00
		pwrmgr_sec_cm	1.700s	716.137us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.700s	716.137us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.700s	716.137us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.620s	363.798us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.300s	826.498us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.210s	871.261us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.080s	70.892us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	30.138us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.700s	716.137us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.700s	716.137us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.700s	716.137us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	38.267us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	61.729us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.750s	276.049us	48	50	96.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	19.511us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	19.511us	20	20	100.00
V2S		TOTAL			373	375	99.47
V3	escalation_timeout	pwrmgr_escalation_timeout	1.040s	640.904us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	39.380s	9.836ms	33	50	66.00
V3		TOTAL			83	100	83.00
		TOTAL			1091	1120	97.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	98.23	96.43	99.44	96.00	96.37	100.00	99.02

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 26 failures:

Test pwrmgr_stress_all_with_rand_reset has 14 failures.

0.pwrmgr_stress_all_with_rand_reset.110999771959957636734797355912486771989622553823079160588322697383531892154320
Line 1788, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2991152322 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 2991152322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.pwrmgr_stress_all_with_rand_reset.2993469996938988293436531028423557739820849760071369496390226679188840404866
Line 323, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 652994799 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
  UVM_INFO @ 652994799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test pwrmgr_aborted_low_power has 2 failures.

2.pwrmgr_aborted_low_power.89164598313958681244007131881290830987295937212010000486223966755851959130153
Line 269, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  40539317 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  40539317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.pwrmgr_aborted_low_power.6880302772123161870691048930503875762833796513868068600414913985601095733166
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  55203349 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  55203349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwrmgr_stress_all has 7 failures.

9.pwrmgr_stress_all.99773060068190354483979776509849330815177264473339470423144546953977969204876
Line 506, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 374341196 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 374341196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.pwrmgr_stress_all.6547614242860047683576836096490455254129847713895129408522979522319883041037
Line 438, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 396425494 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 396425494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test pwrmgr_sec_cm_ctrl_config_regwen has 2 failures.

32.pwrmgr_sec_cm_ctrl_config_regwen.50799308941752321920840615186415446021810573196134966205229580204519432968963
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_ERROR @  37953763 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  37953763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.pwrmgr_sec_cm_ctrl_config_regwen.100869349395427463342696178810606677883276207779419700717001737097903731109416
Line 272, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_ERROR @  41494371 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  41494371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwrmgr_lowpower_wakeup_race has 1 failures.
- 46.pwrmgr_lowpower_wakeup_race.52314250701543444792765107279031399186817013385789446393932336969467411131147
  Line 306, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest/run.log
```
  UVM_ERROR @ 105914041 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 105914041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 2 failures:
- Test pwrmgr_stress_all_with_rand_reset has 2 failures.
  - 13.pwrmgr_stress_all_with_rand_reset.33363863816011857123424919864176756361739666616153295143885469250669130096682
    Line 1077, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 1950399383 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 1950399383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 42.pwrmgr_stress_all_with_rand_reset.53219204727285182151891202898698692147069376320016448199610505235330099270744
    Line 10049, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 27559850661 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 27559850661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 38.pwrmgr_stress_all_with_rand_reset.43319082852034035049101447639102107397491499077178906264693325346770116420069
    Line 3947, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7390668498 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7390668498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```