PWRMGR Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.720s	33.397us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	29.087us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.820s	18.290us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.450s	817.863us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.030s	62.619us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.260s	71.784us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.820s	18.290us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	62.619us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.430s	218.751us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.430s	218.751us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.820s	111.411us	46	50	92.00
		pwrmgr_lowpower_invalid	0.770s	45.805us	50	50	100.00
V2	reset	pwrmgr_reset	1.330s	71.646us	50	50	100.00
		pwrmgr_reset_invalid	1.120s	99.638us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.330s	71.646us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.850s	322.274us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.500s	254.194us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.890s	75.056us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.910s	1.698ms	44	50	88.00
V2	intr_test	pwrmgr_intr_test	0.720s	23.135us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.550s	578.423us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.550s	578.423us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	29.087us	5	5	100.00
		pwrmgr_csr_rw	0.820s	18.290us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	62.619us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.010s	162.523us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	29.087us	5	5	100.00
		pwrmgr_csr_rw	0.820s	18.290us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	62.619us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.010s	162.523us	20	20	100.00
V2		TOTAL			530	540	98.15
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.940s	233.908us	20	20	100.00
		pwrmgr_sec_cm	1.670s	753.047us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.670s	753.047us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.670s	753.047us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.940s	233.908us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.030s	852.835us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.110s	893.793us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	70.429us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	30.178us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.670s	753.047us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.670s	753.047us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.670s	753.047us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.650s	49.405us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	62.047us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.690s	329.800us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.820s	18.290us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.820s	18.290us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.070s	1.068ms	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	59.160s	11.933ms	34	50	68.00
V3		TOTAL			83	100	83.00
		TOTAL			1093	1120	97.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 25 failures:

Test pwrmgr_stress_all_with_rand_reset has 15 failures.

1.pwrmgr_stress_all_with_rand_reset.56046460765781746544987092042392352001422137510344233647497405382932671916529
Line 1002, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1230455904 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 1230455904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.pwrmgr_stress_all_with_rand_reset.87175193105924336024548195556752440680003204650860017167021088871106945872327
Line 478, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 288250256 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 288250256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test pwrmgr_stress_all has 6 failures.

2.pwrmgr_stress_all.2461811508746433316291911705533436647003092010271688274485805200608784281030
Line 2054, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 3022599283 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 3022599283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.pwrmgr_stress_all.70509562523595779055172820431468324694555176721403556032425917069871193558307
Line 1885, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 2011727644 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 2011727644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test pwrmgr_aborted_low_power has 4 failures.

7.pwrmgr_aborted_low_power.97920309199434857549724411830108703075335134984695774341884859356899104587210
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  18539622 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  18539622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.pwrmgr_aborted_low_power.50477858187047552722233982697038785037597714133397293765060497467309092299199
Line 273, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest/run.log

  UVM_ERROR @  33274858 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  33274858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 0.pwrmgr_escalation_timeout.93987561136298700472283268517118102813000520706606882075133432846364531689865
    Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log
```
  UVM_FATAL @ 1717175492 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
  UVM_INFO @ 1717175492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 22.pwrmgr_stress_all_with_rand_reset.39119206323507245646754435556573085098296674347949960317464218018335202240601
    Line 1628, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4121764605 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4121764605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```