PWRMGR Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: bc285b7382

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.770s 32.962us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.760s 38.906us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.740s 66.740us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.580s 858.389us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.940s 39.516us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.650s 56.817us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.740s 66.740us 20 20 100.00
pwrmgr_csr_aliasing 0.940s 39.516us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.070s 160.129us 35 50 70.00
V2 control_clks pwrmgr_wakeup 1.070s 160.129us 35 50 70.00
V2 aborted_low_power pwrmgr_aborted_low_power 0.860s 112.198us 46 50 92.00
pwrmgr_lowpower_invalid 0.770s 41.340us 50 50 100.00
V2 reset pwrmgr_reset 1.070s 89.794us 50 50 100.00
pwrmgr_reset_invalid 1.080s 106.250us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.070s 89.794us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.430s 243.595us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.070s 395.672us 32 50 64.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.890s 68.876us 50 50 100.00
V2 stress_all pwrmgr_stress_all 4.390s 1.049ms 14 50 28.00
V2 intr_test pwrmgr_intr_test 0.710s 21.325us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.650s 133.644us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.650s 133.644us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.760s 38.906us 5 5 100.00
pwrmgr_csr_rw 0.740s 66.740us 20 20 100.00
pwrmgr_csr_aliasing 0.940s 39.516us 5 5 100.00
pwrmgr_same_csr_outstanding 0.980s 49.037us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.760s 38.906us 5 5 100.00
pwrmgr_csr_rw 0.740s 66.740us 20 20 100.00
pwrmgr_csr_aliasing 0.940s 39.516us 5 5 100.00
pwrmgr_same_csr_outstanding 0.980s 49.037us 20 20 100.00
V2 TOTAL 467 540 86.48
V2S tl_intg_err pwrmgr_tl_intg_err 1.820s 200.113us 20 20 100.00
pwrmgr_sec_cm 2.090s 669.136us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.090s 669.136us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.090s 669.136us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.820s 200.113us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.320s 824.047us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.470s 912.034us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.010s 78.435us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.700s 31.097us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.090s 669.136us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.090s 669.136us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.090s 669.136us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.700s 66.196us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.710s 76.043us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.290s 342.545us 33 50 66.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.740s 66.740us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.740s 66.740us 20 20 100.00
V2S TOTAL 358 375 95.47
V3 escalation_timeout pwrmgr_escalation_timeout 1.090s 613.827us 49 50 98.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 10.920s 7.944ms 1 50 2.00
V3 TOTAL 50 100 50.00
TOTAL 980 1120 87.50

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 8 66.67
V2S 9 9 8 88.89
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.72 98.23 96.58 90.98 96.00 96.37 100.00 98.85

Failure Buckets

Past Results