PWRMGR Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0 50 0.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.710s 25.937us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.720s 25.491us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.530s 330.447us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.030s 90.572us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.550s 107.312us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.720s 25.491us 20 20 100.00
pwrmgr_csr_aliasing 1.030s 90.572us 5 5 100.00
V1 TOTAL 55 105 52.38
V2 wakeup pwrmgr_wakeup 0 50 0.00
V2 control_clks pwrmgr_wakeup 0 50 0.00
V2 aborted_low_power pwrmgr_aborted_low_power 0 50 0.00
pwrmgr_lowpower_invalid 0 50 0.00
V2 reset pwrmgr_reset 0 50 0.00
pwrmgr_reset_invalid 0 50 0.00
V2 main_power_glitch_reset pwrmgr_reset 0 50 0.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 0 50 0.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 0 50 0.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0 50 0.00
V2 stress_all pwrmgr_stress_all 0 50 0.00
V2 intr_test pwrmgr_intr_test 0.680s 21.715us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.740s 178.598us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.740s 178.598us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.710s 25.937us 5 5 100.00
pwrmgr_csr_rw 0.720s 25.491us 20 20 100.00
pwrmgr_csr_aliasing 1.030s 90.572us 5 5 100.00
pwrmgr_same_csr_outstanding 0.900s 30.442us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.710s 25.937us 5 5 100.00
pwrmgr_csr_rw 0.720s 25.491us 20 20 100.00
pwrmgr_csr_aliasing 1.030s 90.572us 5 5 100.00
pwrmgr_same_csr_outstanding 0.900s 30.442us 20 20 100.00
V2 TOTAL 90 540 16.67
V2S tl_intg_err pwrmgr_tl_intg_err 1.770s 1.529ms 20 20 100.00
pwrmgr_sec_cm 0 5 0.00
V2S prim_count_check pwrmgr_sec_cm 0 5 0.00
V2S prim_fsm_check pwrmgr_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.770s 1.529ms 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 0 50 0.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 0 50 0.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 0 50 0.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0 50 0.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 0 5 0.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 0 5 0.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 0 5 0.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0 50 0.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0 50 0.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 0 50 0.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.720s 25.491us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.720s 25.491us 20 20 100.00
V2S TOTAL 20 375 5.33
V3 escalation_timeout pwrmgr_escalation_timeout 0 50 0.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 100 0.00
TOTAL 165 1120 14.73

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 12 12 3 25.00
V2S 9 9 1 11.11
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
53.15 42.44 64.05 77.73 0.00 42.18 100.00 45.66

Failure Buckets

Past Results