PWRMGR Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.740s 28.349us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.690s 48.058us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.700s 66.847us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.470s 599.368us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.050s 167.612us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.700s 82.722us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.700s 66.847us 20 20 100.00
pwrmgr_csr_aliasing 1.050s 167.612us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.350s 281.069us 34 50 68.00
V2 control_clks pwrmgr_wakeup 1.350s 281.069us 34 50 68.00
V2 aborted_low_power pwrmgr_aborted_low_power 0.830s 119.867us 50 50 100.00
pwrmgr_lowpower_invalid 0.750s 49.869us 50 50 100.00
V2 reset pwrmgr_reset 1.050s 67.613us 50 50 100.00
pwrmgr_reset_invalid 1.120s 107.202us 49 50 98.00
V2 main_power_glitch_reset pwrmgr_reset 1.050s 67.613us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.490s 303.275us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.190s 267.903us 40 50 80.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.920s 74.877us 50 50 100.00
V2 stress_all pwrmgr_stress_all 5.200s 4.445ms 22 50 44.00
V2 intr_test pwrmgr_intr_test 0.660s 17.930us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.880s 1.269ms 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.880s 1.269ms 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.690s 48.058us 5 5 100.00
pwrmgr_csr_rw 0.700s 66.847us 20 20 100.00
pwrmgr_csr_aliasing 1.050s 167.612us 5 5 100.00
pwrmgr_same_csr_outstanding 0.930s 44.958us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.690s 48.058us 5 5 100.00
pwrmgr_csr_rw 0.700s 66.847us 20 20 100.00
pwrmgr_csr_aliasing 1.050s 167.612us 5 5 100.00
pwrmgr_same_csr_outstanding 0.930s 44.958us 20 20 100.00
V2 TOTAL 485 540 89.81
V2S tl_intg_err pwrmgr_tl_intg_err 1.740s 200.904us 20 20 100.00
pwrmgr_sec_cm 1.880s 604.595us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.880s 604.595us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.880s 604.595us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.740s 200.904us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.420s 830.380us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.340s 860.915us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.050s 66.789us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.740s 32.724us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.880s 604.595us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.880s 604.595us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.880s 604.595us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.770s 38.191us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.780s 63.282us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.280s 259.827us 35 50 70.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.700s 66.847us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.700s 66.847us 20 20 100.00
V2S TOTAL 360 375 96.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.080s 732.563us 50 50 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 18.030s 40.418ms 4 50 8.00
V3 TOTAL 54 100 54.00
TOTAL 1004 1120 89.64

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 8 66.67
V2S 9 9 8 88.89
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.90 98.23 96.43 99.44 96.00 96.37 100.00 98.85

Failure Buckets

Past Results