PWRMGR Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.720s	28.703us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.720s	32.545us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	18.725us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.520s	3.325ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.030s	27.236us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.200s	88.445us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	18.725us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	27.236us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.220s	274.012us	32	50	64.00
V2	control_clks	pwrmgr_wakeup	1.220s	274.012us	32	50	64.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.840s	68.187us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	45.976us	50	50	100.00
V2	reset	pwrmgr_reset	1.060s	86.364us	49	50	98.00
		pwrmgr_reset_invalid	1.150s	100.590us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.060s	86.364us	49	50	98.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.610s	286.695us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.180s	379.172us	28	50	56.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.850s	55.992us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	4.550s	4.854ms	23	50	46.00
V2	intr_test	pwrmgr_intr_test	0.700s	17.929us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.300s	478.466us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.300s	478.466us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.720s	32.545us	5	5	100.00
		pwrmgr_csr_rw	0.690s	18.725us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	27.236us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	79.222us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.720s	32.545us	5	5	100.00
		pwrmgr_csr_rw	0.690s	18.725us	20	20	100.00
		pwrmgr_csr_aliasing	1.030s	27.236us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	79.222us	20	20	100.00
V2		TOTAL			472	540	87.41
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.770s	208.511us	20	20	100.00
		pwrmgr_sec_cm	2.250s	665.722us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.250s	665.722us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.250s	665.722us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.770s	208.511us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.160s	683.533us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.510s	841.441us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.990s	76.028us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	31.620us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.250s	665.722us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.250s	665.722us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.250s	665.722us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.740s	42.206us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	53.169us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.480s	278.307us	34	50	68.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	18.725us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	18.725us	20	20	100.00
V2S		TOTAL			359	375	95.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	365.536us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	25.850s	42.241ms	5	50	10.00
V3		TOTAL			55	100	55.00
		TOTAL			991	1120	88.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	8	66.67
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.72	98.23	96.58	90.98	96.00	96.37	100.00	98.85

Failure Buckets

UVM_FATAL (pwrmgr_base_vseq.sv:712) [pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} init:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 57 failures:

Test pwrmgr_lowpower_wakeup_race has 22 failures.

0.pwrmgr_lowpower_wakeup_race.81793855810154921144512390861942979617979839713313429049421028365691492766218
Line 411, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_FATAL @ 177587272 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout  exp:'{reasons:'{d:'h24}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h3e}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 177587272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_lowpower_wakeup_race.67323603264668587450038805741837131972233721904703755131551589708787159896239
Line 287, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_FATAL @  96339564 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout  exp:'{reasons:'{d:'h18}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h1c}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  96339564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.

Test pwrmgr_stress_all_with_rand_reset has 24 failures.

1.pwrmgr_stress_all_with_rand_reset.54829437572325225878554223708475615936758058297176483855354076697899149144158
Line 472, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 395341421 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout  exp:'{reasons:'{d:'he}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h1f}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 395341421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwrmgr_stress_all_with_rand_reset.8704046002209163508847238853809330470391753582191948638431319182843810501288
Line 470, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 327141060 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout  exp:'{reasons:'{d:'h9}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h1d}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 327141060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 22 more failures.

Test pwrmgr_stress_all has 11 failures.

3.pwrmgr_stress_all.37608665767965823280817661892749984738821356536643025137596193150244364909531
Line 622, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 633656518 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout  exp:'{reasons:'{d:'h2}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h32}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 633656518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.pwrmgr_stress_all.17791154164952205795929688481629065117996118152949034660370333529974892059601
Line 563, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 1140394748 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout  exp:'{reasons:'{d:'h21}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h23}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 1140394748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_FATAL (pwrmgr_base_vseq.sv:712) [pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} init:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 53 failures:

Test pwrmgr_wakeup has 17 failures.

0.pwrmgr_wakeup.43053267732216866222505106175431904359146479819921270756452451490329833671282
Line 305, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log

  UVM_FATAL @ 164242998 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout  exp:'{reasons:'{d:'h4}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'hc}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 164242998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_wakeup.2785570163344886778539920098392504409385794234712145979327301003760392935201
Line 284, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest/run.log

  UVM_FATAL @  81712243 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout  exp:'{reasons:'{d:'h10}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h30}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  81712243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

Test pwrmgr_stress_all_with_rand_reset has 20 failures.

0.pwrmgr_stress_all_with_rand_reset.56939252128403646578207042229418678154118143385109743029726820663840657033674
Line 1027, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 919826022 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout  exp:'{reasons:'{d:'h2b}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h3b}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 919826022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_stress_all_with_rand_reset.86493520244090777517058017092719444946980712930810310867146302949953804650969
Line 438, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 149872893 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout  exp:'{reasons:'{d:'h4}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h5}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 149872893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Test pwrmgr_stress_all has 16 failures.

2.pwrmgr_stress_all.63198090049336312037471874527427336401251032767498747187675784703835098205128
Line 427, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 406622843 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout  exp:'{reasons:'{d:'h9}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'hd}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 406622843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwrmgr_stress_all.23853171801998988855648936415871204897284474621507014085186066801755568049703
Line 523, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 629825066 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout  exp:'{reasons:'{d:'hc}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h3c}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 629825066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

UVM_FATAL (pwrmgr_base_vseq.sv:712) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} init:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 15 failures:

Test pwrmgr_sec_cm_ctrl_config_regwen has 15 failures.

1.pwrmgr_sec_cm_ctrl_config_regwen.86077178632719386680561489169435528196085024488545841371742178493160728186593
Line 308, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_FATAL @ 196370983 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout  exp:'{reasons:'{d:'h20}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'h28}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 196370983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_sec_cm_ctrl_config_regwen.81712942654585951115968520088467274045270897465699605479479782559835878163143
Line 401, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_FATAL @ 227065894 ps: (pwrmgr_base_vseq.sv:712) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout  exp:'{reasons:'{d:'h4}, fall_through:'{d:'h0}, abort:'{d:'h0}}  init:'{reasons:'{d:'hc}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 227065894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 2 failures:
- Test pwrmgr_reset has 1 failures.
  - 31.pwrmgr_reset.91753297302084421724191372868242291224483098889993904837235577323899199562510
    Line 312, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_reset/latest/run.log
```
  UVM_ERROR @  68543055 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @  68543055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 35.pwrmgr_stress_all_with_rand_reset.38153023794555487066390198406099861727488618585573955996301113525222478176186
    Line 1195, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1359323668 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 1359323668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 1 failures:
- Test pwrmgr_sec_cm_ctrl_config_regwen has 1 failures.
  - 11.pwrmgr_sec_cm_ctrl_config_regwen.93335717968634685103639982123592137509483386377068513070067404586117247651737
    Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  75013778 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  75013778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_wakeup has 1 failures.
  - 39.pwrmgr_wakeup.53207840040230716936874082732772883035314416245717870432023946404607646075033
    Line 364, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest/run.log
```
  UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```