PWRMGR Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	32.209us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.800s	33.011us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	24.690us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.910s	278.889us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	93.355us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.340s	53.070us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	24.690us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	93.355us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.380s	274.248us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.380s	274.248us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.200s	34.928us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	42.694us	50	50	100.00
V2	reset	pwrmgr_reset	1.010s	82.722us	50	50	100.00
		pwrmgr_reset_invalid	1.150s	98.752us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.010s	82.722us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.460s	317.935us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.590s	333.092us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	62.398us	49	50	98.00
V2	stress_all	pwrmgr_stress_all	8.160s	2.645ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.690s	21.955us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.390s	164.095us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.390s	164.095us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.800s	33.011us	5	5	100.00
		pwrmgr_csr_rw	0.720s	24.690us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	93.355us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.000s	262.123us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.800s	33.011us	5	5	100.00
		pwrmgr_csr_rw	0.720s	24.690us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	93.355us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.000s	262.123us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.770s	198.296us	20	20	100.00
		pwrmgr_sec_cm	2.360s	688.659us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.360s	688.659us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.360s	688.659us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.770s	198.296us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.340s	820.058us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.480s	904.753us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.030s	73.963us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	30.580us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.360s	688.659us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.360s	688.659us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.360s	688.659us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	36.646us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	62.017us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.460s	328.745us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	24.690us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	24.690us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.040s	163.102us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	33.740s	9.983ms	46	50	92.00
V3		TOTAL			95	100	95.00
		TOTAL			1114	1120	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 3 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 3 failures.

    • 2.pwrmgr_stress_all_with_rand_reset.574355950020898610479164033494049786079878261114805949872070616947875368412
      Line 1556, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1636296158 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 1636296158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.pwrmgr_stress_all_with_rand_reset.104679816069148517192072677961050059112436880226743363172745274895844457456517
      Line 688, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 464796721 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 464796721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 3.pwrmgr_stress_all_with_rand_reset.8940467850719073691497135707114555828364039762770639528733127237543115077455
      Line 1955, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3783170822 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 3783170822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:

  • Test pwrmgr_disable_rom_integrity_check has 1 failures.

    • 6.pwrmgr_disable_rom_integrity_check.98909731730319735813459712785344079496860375828636016464542980964800812708197
      Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @  31941476 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @  31941476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 11.pwrmgr_escalation_timeout.33762539647019131226540826934268516721737525273810337621207154766900586365520
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 1438612556 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 1438612556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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