PWRMGR Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	29.254us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.730s	37.167us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	18.326us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.420s	376.047us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.960s	22.898us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.360s	239.955us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	18.326us	20	20	100.00
		pwrmgr_csr_aliasing	0.960s	22.898us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.320s	256.825us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.320s	256.825us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.120s	35.624us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	43.009us	50	50	100.00
V2	reset	pwrmgr_reset	0.970s	80.109us	49	50	98.00
		pwrmgr_reset_invalid	1.090s	107.142us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.970s	80.109us	49	50	98.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.420s	271.026us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.360s	217.669us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	73.101us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.320s	2.444ms	49	50	98.00
V2	intr_test	pwrmgr_intr_test	0.660s	140.875us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.980s	975.057us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.980s	975.057us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.730s	37.167us	5	5	100.00
		pwrmgr_csr_rw	0.690s	18.326us	20	20	100.00
		pwrmgr_csr_aliasing	0.960s	22.898us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.890s	42.667us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.730s	37.167us	5	5	100.00
		pwrmgr_csr_rw	0.690s	18.326us	20	20	100.00
		pwrmgr_csr_aliasing	0.960s	22.898us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.890s	42.667us	20	20	100.00
V2		TOTAL			537	540	99.44
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.720s	195.985us	20	20	100.00
		pwrmgr_sec_cm	2.430s	690.369us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.430s	690.369us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.430s	690.369us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.720s	195.985us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.440s	868.586us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.450s	880.497us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.070s	76.188us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	30.048us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.430s	690.369us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.430s	690.369us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.430s	690.369us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	155.315us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	63.021us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.480s	301.668us	49	50	98.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	18.326us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	18.326us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	166.862us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	33.190s	10.918ms	45	50	90.00
V3		TOTAL			94	100	94.00
		TOTAL			1110	1120	99.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	9	8	88.89
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 4 failures:

  • Test pwrmgr_sec_cm_ctrl_config_regwen has 1 failures.

    • 17.pwrmgr_sec_cm_ctrl_config_regwen.24103892901280134581861951524057028449966912148930592306811171248283147886679
      Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

        UVM_ERROR @  26069036 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @  26069036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 22.pwrmgr_stress_all_with_rand_reset.84045466560881718727088223972614716223915723232359469687342878680618313653434
      Line 1751, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4279769955 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 4279769955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all has 1 failures.

    • 33.pwrmgr_stress_all.73728356881369184312007163462343543118414482414728160990931066427920874615887
      Line 1276, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 1942399725 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 1942399725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_lowpower_wakeup_race has 1 failures.

    • 45.pwrmgr_lowpower_wakeup_race.84123809619748543726430396681845684490355003905961722897939951371120168726030
      Line 260, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_lowpower_wakeup_race/latest/run.log

        UVM_ERROR @  21762794 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @  21762794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 3 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 15.pwrmgr_stress_all_with_rand_reset.113355318943674232396567549825887939854415677596561370147994574905196429210118
      Line 5082, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9642734433 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 9642734433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 26.pwrmgr_stress_all_with_rand_reset.1570540623955175754655076346413430542784151300602463668983388432680606121263
      Line 630, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 623797997 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 623797997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_reset has 1 failures.

    • 42.pwrmgr_reset.102210567976149942753519053332957668536580511951123980446716248144425198873969
      Line 305, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_reset/latest/run.log

        UVM_ERROR @  43459966 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  43459966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_reset_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 13.pwrmgr_stress_all_with_rand_reset.44125806550429802867811838807860464305187059614527410766714198884943314867393
      Line 4856, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 8147966234 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 8147966234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 32.pwrmgr_escalation_timeout.87084941726997106349649459047703842904165670927666269918677518814470668540821
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 1724980512 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 1724980512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:753) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 38.pwrmgr_stress_all_with_rand_reset.31802726876849180345530840889661644178497250613576808881481164842901009044224
      Line 1541, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2433756741 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2433756741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.03.22_04.59.47
• 2024.03.20_03.59.01
• 2024.03.18_04.56.06
• 2024.03.15_00.28.59
• 2024.03.13_04.25.06