PWRMGR Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.710s	32.241us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	49.985us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	31.850us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.820s	77.233us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.060s	48.110us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.350s	53.691us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	31.850us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	48.110us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.310s	288.895us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.310s	288.895us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.080s	33.235us	50	50	100.00
		pwrmgr_lowpower_invalid	0.760s	42.718us	50	50	100.00
V2	reset	pwrmgr_reset	1.030s	87.581us	50	50	100.00
		pwrmgr_reset_invalid	1.090s	106.570us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.030s	87.581us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.500s	325.571us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.330s	293.965us	48	50	96.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.890s	63.929us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.260s	1.972ms	49	50	98.00
V2	intr_test	pwrmgr_intr_test	0.700s	26.598us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.940s	411.819us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.940s	411.819us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	49.985us	5	5	100.00
		pwrmgr_csr_rw	0.700s	31.850us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	48.110us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	48.904us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	49.985us	5	5	100.00
		pwrmgr_csr_rw	0.700s	31.850us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	48.110us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	48.904us	20	20	100.00
V2		TOTAL			537	540	99.44
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.730s	214.980us	20	20	100.00
		pwrmgr_sec_cm	2.180s	650.494us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.180s	650.494us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.180s	650.494us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.730s	214.980us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.260s	825.360us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.480s	859.237us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	62.729us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	28.205us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.180s	650.494us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.180s	650.494us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.180s	650.494us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	31.002us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	51.320us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.630s	251.740us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	31.850us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	31.850us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.040s	190.535us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	38.470s	9.670ms	45	50	90.00
V3		TOTAL			94	100	94.00
		TOTAL			1111	1120	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 4 failures:

  • Test pwrmgr_stress_all has 1 failures.

    • 8.pwrmgr_stress_all.2761086464819175802041802016556590561386628620967739881432131136153348847909
      Line 514, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 505617877 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 505617877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 3 failures.

    • 11.pwrmgr_stress_all_with_rand_reset.22914232412537976102580803329546171294228907367497063705771413960605207075661
      Line 1684, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2256460860 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 2256460860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.pwrmgr_stress_all_with_rand_reset.44672308817005552973017042369597536494796640984831811243289646637008405588014
      Line 1067, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1836334540 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 1836334540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 3 failures:

  • Test pwrmgr_lowpower_wakeup_race has 2 failures.

    • 33.pwrmgr_lowpower_wakeup_race.15208343082891499246868736981892474264208695828057002034686406552400333275517
      Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest/run.log

        UVM_ERROR @  38885737 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @  38885737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 37.pwrmgr_lowpower_wakeup_race.27995421116989647203880588912210853550032916583127279318666011607709152476158
      Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_lowpower_wakeup_race/latest/run.log

        UVM_ERROR @  37074925 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @  37074925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 41.pwrmgr_stress_all_with_rand_reset.43244588135662243633344490179065336638895205084589547340467762115661164968236
      Line 2806, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4552244563 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 4552244563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 21.pwrmgr_stress_all_with_rand_reset.17230094676094757466991997081528242084035453883657193306779591964322122391120
      Line 2127, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 8574827740 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 8574827740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 24.pwrmgr_escalation_timeout.67784167743984169975118023316023578481545144800102901042878894712656378148436
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 1718936572 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 1718936572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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