PWRMGR Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	31.310us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	38.971us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	23.296us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.230s	218.681us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	156.588us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.660s	143.997us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	23.296us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	156.588us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.300s	260.311us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.300s	260.311us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.080s	32.791us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	44.937us	50	50	100.00
V2	reset	pwrmgr_reset	1.010s	76.327us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	108.633us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.010s	76.327us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.460s	322.423us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.290s	256.887us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.900s	58.562us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.810s	2.140ms	47	50	94.00
V2	intr_test	pwrmgr_intr_test	0.680s	44.273us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.690s	466.648us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.690s	466.648us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	38.971us	5	5	100.00
		pwrmgr_csr_rw	0.720s	23.296us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	156.588us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	33.154us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	38.971us	5	5	100.00
		pwrmgr_csr_rw	0.720s	23.296us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	156.588us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	33.154us	20	20	100.00
V2		TOTAL			535	540	99.07
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.910s	191.306us	20	20	100.00
		pwrmgr_sec_cm	2.260s	646.032us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.260s	646.032us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.260s	646.032us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.910s	191.306us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.270s	868.116us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.560s	810.691us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.030s	74.489us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	31.548us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.260s	646.032us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.260s	646.032us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.260s	646.032us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	63.524us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	47.642us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.470s	241.134us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	23.296us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	23.296us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	166.681us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	41.420s	13.487ms	44	50	88.00
V3		TOTAL			94	100	94.00
		TOTAL			1109	1120	99.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 6 failures:
- Test pwrmgr_stress_all_with_rand_reset has 4 failures.
  - 3.pwrmgr_stress_all_with_rand_reset.66325975770040474813109115515301742694553525672875083441751085524060028795651
    Line 1773, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1785336126 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 1785336126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.pwrmgr_stress_all_with_rand_reset.44522757371060360686214599941567275065680476108018496546761556912502063280184
    Line 4972, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7162714721 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 7162714721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test pwrmgr_stress_all has 2 failures.
  - 10.pwrmgr_stress_all.3008579741837134949906187433042196816695655025779437326734137044911873872667
    Line 1147, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1316407802 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 1316407802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.pwrmgr_stress_all.75841386884691615910565872092351378830936212966009143698644389341279510885330
    Line 846, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest/run.log
```
  UVM_ERROR @ 756630250 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 756630250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 3 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 7.pwrmgr_stress_all_with_rand_reset.76423173195409058418054797516169737838981900077682500376657449086169003467102
    Line 1048, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 921785247 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 921785247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwrmgr_stress_all has 1 failures.
  - 33.pwrmgr_stress_all.33527405225978260018727213318032529984255760958881105121726807842867171033572
    Line 495, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest/run.log
```
  UVM_ERROR @ 556866390 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 556866390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwrmgr_lowpower_wakeup_race has 1 failures.
  - 43.pwrmgr_lowpower_wakeup_race.21909244260765413519708156481818306272795410628124974681501077942150650987598
    Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest/run.log
```
  UVM_ERROR @  22756898 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  22756898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_wakeup_reset has 1 failures.
  - 33.pwrmgr_wakeup_reset.71977289022436187326331997394928575448855785033079934414368220891352836404907
    Line 388, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest/run.log
```
  UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 43.pwrmgr_stress_all_with_rand_reset.5193340329331949129476234617431105624637857185138306509662977352675353921849
    Line 2369, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3882951762 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3882951762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

PWRMGR Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4ee21f808f`