PWRMGR Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	31.084us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	64.775us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.670s	26.596us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.040s	220.842us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.920s	39.063us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.280s	52.101us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.670s	26.596us	20	20	100.00
		pwrmgr_csr_aliasing	0.920s	39.063us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.390s	290.390us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.390s	290.390us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.010s	45.968us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	44.447us	50	50	100.00
V2	reset	pwrmgr_reset	1.030s	83.656us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	106.468us	49	50	98.00
V2	main_power_glitch_reset	pwrmgr_reset	1.030s	83.656us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.480s	331.806us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.340s	278.544us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.920s	60.435us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.560s	2.364ms	47	50	94.00
V2	intr_test	pwrmgr_intr_test	0.690s	23.262us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.760s	658.846us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.760s	658.846us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	64.775us	5	5	100.00
		pwrmgr_csr_rw	0.670s	26.596us	20	20	100.00
		pwrmgr_csr_aliasing	0.920s	39.063us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	355.976us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	64.775us	5	5	100.00
		pwrmgr_csr_rw	0.670s	26.596us	20	20	100.00
		pwrmgr_csr_aliasing	0.920s	39.063us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	355.976us	20	20	100.00
V2		TOTAL			536	540	99.26
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.940s	507.613us	20	20	100.00
		pwrmgr_sec_cm	1.380s	1.178ms	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.380s	1.178ms	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.380s	1.178ms	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.940s	507.613us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.360s	746.197us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.520s	828.250us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	71.066us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	31.032us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.380s	1.178ms	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.380s	1.178ms	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.380s	1.178ms	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	53.334us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	60.654us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.400s	274.354us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.670s	26.596us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.670s	26.596us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	165.318us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	47.310s	11.013ms	43	50	86.00
V3		TOTAL			93	100	93.00
		TOTAL			1109	1120	99.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 5 failures:

  • Test pwrmgr_stress_all has 2 failures.

    • 9.pwrmgr_stress_all.21878357120806413869705599145696881356117513341790745272566058704569698494947
      Line 1636, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 2127428294 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 2127428294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 38.pwrmgr_stress_all.87748850130924739744718041299074889891600484230237560572412532390865428429195
      Line 299, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 144591292 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 144591292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 3 failures.

    • 16.pwrmgr_stress_all_with_rand_reset.53253640098037820341188459749470418813357905396345068633431570074675554596337
      Line 2301, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5681206241 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 5681206241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 31.pwrmgr_stress_all_with_rand_reset.88011828752078336289834557783301780244556379652766707876428860543298538673183
      Line 1479, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5899657691 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 5899657691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 4 failures:

  • Test pwrmgr_stress_all has 1 failures.

    • 7.pwrmgr_stress_all.102876742208012685120886199659162375886864442710068475493715408983033152164927
      Line 323, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @  63662216 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  63662216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 3 failures.

    • 23.pwrmgr_stress_all_with_rand_reset.42734728903427871691327185372597161452061406248576831822426947688464588779578
      Line 2237, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4600115596 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 4600115596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.pwrmgr_stress_all_with_rand_reset.1011624514896310699008870576426329606709215347708759864179261266560799274970
      Line 854, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1464133345 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 1464133345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 21.pwrmgr_stress_all_with_rand_reset.75273999749608592481176661819630354620580722153458692569424782153665871400227
      Line 2571, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10392120006 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 10392120006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 45.pwrmgr_reset_invalid.93373069254173892410299876619045523440683946017160609935459772798517120184990
      Line 268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 319716836 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 319716836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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