PWRMGR Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	29.873us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	26.596us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	22.239us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.410s	324.628us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.100s	405.144us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.490s	94.315us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	22.239us	20	20	100.00
		pwrmgr_csr_aliasing	1.100s	405.144us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.350s	300.201us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.350s	300.201us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.140s	36.216us	50	50	100.00
		pwrmgr_lowpower_invalid	0.750s	43.812us	50	50	100.00
V2	reset	pwrmgr_reset	1.130s	90.468us	50	50	100.00
		pwrmgr_reset_invalid	1.190s	106.363us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.130s	90.468us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.560s	321.189us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.440s	268.961us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.940s	60.835us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.860s	1.685ms	48	50	96.00
V2	intr_test	pwrmgr_intr_test	0.670s	24.316us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.740s	296.035us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.740s	296.035us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	26.596us	5	5	100.00
		pwrmgr_csr_rw	0.690s	22.239us	20	20	100.00
		pwrmgr_csr_aliasing	1.100s	405.144us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	232.028us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	26.596us	5	5	100.00
		pwrmgr_csr_rw	0.690s	22.239us	20	20	100.00
		pwrmgr_csr_aliasing	1.100s	405.144us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	232.028us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.680s	190.740us	20	20	100.00
		pwrmgr_sec_cm	2.190s	661.435us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.190s	661.435us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.190s	661.435us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.680s	190.740us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.180s	819.874us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.460s	902.167us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.050s	65.261us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	30.890us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.190s	661.435us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.190s	661.435us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.190s	661.435us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.720s	49.782us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	42.585us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.600s	331.308us	49	50	98.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	22.239us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	22.239us	20	20	100.00
V2S		TOTAL			373	375	99.47
V3	escalation_timeout	pwrmgr_escalation_timeout	1.100s	161.299us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	37.340s	10.222ms	46	50	92.00
V3		TOTAL			95	100	95.00
		TOTAL			1111	1120	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	7	77.78
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 5 failures:
- Test pwrmgr_stress_all has 2 failures.
  - 10.pwrmgr_stress_all.107503499685500202104633089377881896088749527967483875575817825874272642250209
    Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest/run.log
```
  UVM_ERROR @  47660435 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  47660435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.pwrmgr_stress_all.36527524233659675079041378745615172840715299863989457592843260250134149738379
    Line 328, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest/run.log
```
  UVM_ERROR @ 112421640 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 112421640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwrmgr_stress_all_with_rand_reset has 2 failures.
  - 11.pwrmgr_stress_all_with_rand_reset.99252607202281359079800651587666873950077022421212646537680904198089061495332
    Line 2028, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5263004232 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 5263004232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.pwrmgr_stress_all_with_rand_reset.438919633026727172358988204843052748239711285632437866489491410097595721732
    Line 4976, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6443724995 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 6443724995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwrmgr_sec_cm_ctrl_config_regwen has 1 failures.
  - 34.pwrmgr_sec_cm_ctrl_config_regwen.98189984149652080539242635262128260108511985673547867897443657238633206819544
    Line 287, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  49685877 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  49685877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 1.pwrmgr_stress_all_with_rand_reset.104725986190332675571627479564586193372494963612137231365796005173755451417608
    Line 1127, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1476176629 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 1476176629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 2.pwrmgr_escalation_timeout.27890256617569333063469999280509201768705564900296666504589016483446290421276
    Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest/run.log
```
      Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
  UVM_ERROR @  95895913 ps: (pwrmgr.sv:173) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
  UVM_INFO @  95895913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 21.pwrmgr_stress_all_with_rand_reset.106254589125854669999591714891663092699598246047195923197699195912596424692422
    Line 2712, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3129757142 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3129757142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.
  - 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4826367999702512077645150783111085545878393508935269532560951542920607054487
    Line 645, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
```
  UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

PWRMGR Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: 1fbe1ece8d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `1fbe1ece8d`