PWRMGR Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	42.348us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	69.332us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.680s	23.075us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.190s	1.852ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.950s	42.812us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.520s	128.261us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.680s	23.075us	20	20	100.00
		pwrmgr_csr_aliasing	0.950s	42.812us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.420s	315.531us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.420s	315.531us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.170s	33.204us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	41.438us	50	50	100.00
V2	reset	pwrmgr_reset	0.960s	106.784us	50	50	100.00
		pwrmgr_reset_invalid	1.110s	107.215us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.960s	106.784us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.470s	343.367us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.350s	281.996us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.860s	57.050us	49	50	98.00
V2	stress_all	pwrmgr_stress_all	6.730s	2.191ms	49	50	98.00
V2	intr_test	pwrmgr_intr_test	0.670s	110.152us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.880s	148.438us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.880s	148.438us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	69.332us	5	5	100.00
		pwrmgr_csr_rw	0.680s	23.075us	20	20	100.00
		pwrmgr_csr_aliasing	0.950s	42.812us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	317.215us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	69.332us	5	5	100.00
		pwrmgr_csr_rw	0.680s	23.075us	20	20	100.00
		pwrmgr_csr_aliasing	0.950s	42.812us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	317.215us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.860s	1.139ms	20	20	100.00
		pwrmgr_sec_cm	2.130s	671.236us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.130s	671.236us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.130s	671.236us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.860s	1.139ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.330s	854.973us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.250s	903.496us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.040s	56.238us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	32.456us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.130s	671.236us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.130s	671.236us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.130s	671.236us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	27.140us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	43.664us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.440s	256.752us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.680s	23.075us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.680s	23.075us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.030s	637.413us	48	50	96.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	36.030s	9.799ms	44	50	88.00
V3		TOTAL			92	100	92.00
		TOTAL			1110	1120	99.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 5 failures:
- Test pwrmgr_stress_all has 1 failures.
  - 31.pwrmgr_stress_all.50879712254654135707670848491141826392892810022844562189754466298184716898465
    Line 370, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest/run.log
```
  UVM_ERROR @ 166879927 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 166879927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwrmgr_disable_rom_integrity_check has 1 failures.
  - 38.pwrmgr_disable_rom_integrity_check.103839213183944489970352192399715874087906604592827682676305074082371827315173
    Line 274, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest/run.log
```
  UVM_ERROR @  34024932 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @  34024932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwrmgr_stress_all_with_rand_reset has 3 failures.
  - 43.pwrmgr_stress_all_with_rand_reset.16322321050000320392970256850185798249449072417893753411548099078709865085976
    Line 4611, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8127680975 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 8127680975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.pwrmgr_stress_all_with_rand_reset.14982486008668189447166994262393517096701046403388947663051508462418823417463
    Line 5200, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7798049778 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 7798049778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 3 failures:
- Test pwrmgr_stress_all_with_rand_reset has 3 failures.
  - 18.pwrmgr_stress_all_with_rand_reset.10803850776628416118465462503493033526495780470347247685712736987749030881711
    Line 625, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 754332764 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 754332764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.pwrmgr_stress_all_with_rand_reset.44999700245839851503341234072580418716580633953196889406029265997723131804571
    Line 4943, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10479702613 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 10479702613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test pwrmgr_escalation_timeout has 1 failures.

24.pwrmgr_escalation_timeout.15007122445531716703304393743786071795812570634086012261164496938788558014751
Log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest/run.log

  [make]: simulate
  cd /workspace/24.pwrmgr_escalation_timeout/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810354975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.810354975
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Apr  4 14:40 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:
- Test pwrmgr_escalation_timeout has 1 failures.
  - 28.pwrmgr_escalation_timeout.75818850480627066766947343012481324864629057079036823487405388984288209724801
    Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest/run.log
```
      Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
  UVM_ERROR @  98743677 ps: (pwrmgr.sv:173) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
  UVM_INFO @  98743677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```