PWRMGR Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	37.540us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	42.653us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	17.897us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.360s	4.308ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	47.729us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.230s	97.821us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	17.897us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	47.729us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.230s	285.337us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.230s	285.337us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.230s	37.367us	50	50	100.00
		pwrmgr_lowpower_invalid	0.800s	71.813us	50	50	100.00
V2	reset	pwrmgr_reset	1.060s	80.165us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	104.121us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.060s	80.165us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.450s	313.881us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.240s	268.698us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.900s	60.348us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.540s	1.764ms	47	50	94.00
V2	intr_test	pwrmgr_intr_test	0.710s	46.754us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.810s	290.093us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.810s	290.093us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	42.653us	5	5	100.00
		pwrmgr_csr_rw	0.720s	17.897us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	47.729us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	41.859us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	42.653us	5	5	100.00
		pwrmgr_csr_rw	0.720s	17.897us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	47.729us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	41.859us	20	20	100.00
V2		TOTAL			537	540	99.44
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.650s	230.986us	20	20	100.00
		pwrmgr_sec_cm	2.120s	636.724us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.120s	636.724us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.120s	636.724us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.650s	230.986us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.300s	799.580us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.530s	872.664us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.000s	65.875us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.670s	30.261us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.120s	636.724us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.120s	636.724us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.120s	636.724us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.730s	58.303us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	54.596us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.510s	286.950us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	17.897us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	17.897us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.080s	315.364us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	31.170s	9.293ms	44	50	88.00
V3		TOTAL			94	100	94.00
		TOTAL			1111	1120	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 3 failures:

  • Test pwrmgr_stress_all has 1 failures.

    • 1.pwrmgr_stress_all.43386486399054001157800440639926223486754873954833402380197189863142344212556
      Line 301, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @  49899986 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @  49899986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 12.pwrmgr_stress_all_with_rand_reset.74735968781702311853520235610574362168242615340577863826563954573103532969508
      Line 3025, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6171423350 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 6171423350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.pwrmgr_stress_all_with_rand_reset.38265136337890104820331771506131173821178856280628250528553138612207179664472
      Line 578, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1017554072 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 1017554072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 3 failures:

  • Test pwrmgr_stress_all has 2 failures.

    • 4.pwrmgr_stress_all.115285185434094667349521255309252965443164569144199860183472134582627346857100
      Line 575, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 482554745 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 482554745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.pwrmgr_stress_all.73132683550412130975690709081483220822281079486636743934047292482695879766798
      Line 1064, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 1648138000 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 1648138000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 18.pwrmgr_stress_all_with_rand_reset.90928310456612418039908457392190102100635280855047560264297620578580382066129
      Line 2048, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1668010617 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 1668010617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_reset_vseq] timeout waiting for pwrmgr fast fsm target activity has 2 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 24.pwrmgr_stress_all_with_rand_reset.41733583045529300362776549989131291349300114652000924768304489869063923248346
      Line 284, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  85056941 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @  85056941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.pwrmgr_stress_all_with_rand_reset.24963294680046339813302683484070012944736267091499532462643889402678302679590
      Line 1066, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 978336819 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 978336819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 46.pwrmgr_stress_all_with_rand_reset.35013595467590632396976505554192711369949653545825692889092801390152822852014
      Line 3020, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 20501767490 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 20501767490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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