PWRMGR Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	30.633us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.640s	33.140us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	21.260us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.820s	76.778us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.980s	24.724us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.540s	118.663us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	21.260us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	24.724us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.440s	292.843us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.440s	292.843us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.120s	34.845us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	45.265us	50	50	100.00
V2	reset	pwrmgr_reset	1.020s	93.226us	50	50	100.00
		pwrmgr_reset_invalid	1.160s	92.912us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.020s	93.226us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.680s	329.897us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.370s	289.916us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.930s	62.886us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.060s	1.930ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	19.803us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.510s	569.835us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.510s	569.835us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.640s	33.140us	5	5	100.00
		pwrmgr_csr_rw	0.690s	21.260us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	24.724us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	49.963us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.640s	33.140us	5	5	100.00
		pwrmgr_csr_rw	0.690s	21.260us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	24.724us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	49.963us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.670s	275.981us	20	20	100.00
		pwrmgr_sec_cm	1.910s	604.402us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.910s	604.402us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.910s	604.402us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.670s	275.981us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.440s	834.683us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.440s	849.872us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	84.705us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	29.676us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.910s	604.402us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.910s	604.402us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.910s	604.402us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	34.260us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.770s	42.720us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.530s	256.599us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	21.260us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	21.260us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.080s	312.651us	48	50	96.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	35.900s	12.279ms	40	50	80.00
V3		TOTAL			88	100	88.00
		TOTAL			1108	1120	98.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	98.23	96.43	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 7 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 7 failures.

    • 5.pwrmgr_stress_all_with_rand_reset.56695480195006331860405145618346738069948297234457333929806967961855188470244
      Line 5032, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6187781752 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 6187781752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.pwrmgr_stress_all_with_rand_reset.72593515375336069417140644188598249913072035780508042989217512049451279401948
      Line 860, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1421202722 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 1421202722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 2 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 1.pwrmgr_stress_all_with_rand_reset.63906674265748496621371687628041906849015665630122827856715496530967556517352
      Line 4701, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6317671619 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 6317671619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.pwrmgr_stress_all_with_rand_reset.111446806843141115721033330949365687378330941156944256254541651415934079909145
      Line 1925, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3040897013 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 3040897013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 21.pwrmgr_escalation_timeout.57961593978609072826683331701445119590169333308585418343510462503864088069355
      Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  98049492 ps: (pwrmgr.sv:173) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  98049492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 28.pwrmgr_escalation_timeout.37414168815648224561086321048870305847722370673400322411049516939369174747862
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 1729314448 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 1729314448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (pwrmgr_base_vseq.sv:692) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.wakeup_status == expected_wakeups (* [*] vs * [*]) has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 32.pwrmgr_stress_all_with_rand_reset.45154488750899865427125346544938113552950308858173671826265000576491907260885
      Line 3257, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10143608323 ps: (pwrmgr_base_vseq.sv:692) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.wakeup_status == expected_wakeups (0 [0x0] vs 20 [0x14])
        UVM_INFO @ 10143608323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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