PWRMGR Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.720s	31.536us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.700s	33.248us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	48.416us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.190s	225.119us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.060s	56.210us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.610s	122.462us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	48.416us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	56.210us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.340s	272.854us	49	50	98.00
V2	control_clks	pwrmgr_wakeup	1.340s	272.854us	49	50	98.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.130s	36.957us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	42.162us	49	50	98.00
V2	reset	pwrmgr_reset	1.050s	84.105us	50	50	100.00
		pwrmgr_reset_invalid	1.160s	94.712us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.050s	84.105us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.520s	269.154us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.400s	302.412us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.900s	68.614us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.210s	2.067ms	46	50	92.00
V2	intr_test	pwrmgr_intr_test	0.680s	20.264us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.900s	268.875us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.900s	268.875us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.700s	33.248us	5	5	100.00
		pwrmgr_csr_rw	0.700s	48.416us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	56.210us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	49.262us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.700s	33.248us	5	5	100.00
		pwrmgr_csr_rw	0.700s	48.416us	20	20	100.00
		pwrmgr_csr_aliasing	1.060s	56.210us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.940s	49.262us	20	20	100.00
V2		TOTAL			534	540	98.89
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.740s	185.349us	20	20	100.00
		pwrmgr_sec_cm	1.500s	337.012us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.500s	337.012us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.500s	337.012us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.740s	185.349us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.280s	842.363us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.290s	906.268us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.940s	101.145us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.660s	40.953us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.500s	337.012us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.500s	337.012us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.500s	337.012us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.750s	47.764us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	60.961us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.350s	293.312us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	48.416us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	48.416us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.040s	688.402us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	42.560s	12.183ms	43	50	86.00
V3		TOTAL			93	100	93.00
		TOTAL			1107	1120	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 5 failures:

  • Test pwrmgr_wakeup has 1 failures.

    • 2.pwrmgr_wakeup.8881458212369511184992771521201373548491533553038094124176422606430972834311
      Line 304, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest/run.log

        UVM_ERROR @ 161721976 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 161721976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 4 failures.

    • 24.pwrmgr_stress_all_with_rand_reset.32990310703524655764339444818555995882868603026671545552020320122777367969357
      Line 2145, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5937732601 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 5937732601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 28.pwrmgr_stress_all_with_rand_reset.65416093702953544904322826533670136844963962358849375697338034155341670001914
      Line 2161, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3562274531 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 3562274531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 4 failures:

  • Test pwrmgr_stress_all has 3 failures.

    • 7.pwrmgr_stress_all.103162042373588233017866259003872197324245829651286367108981520954740780421162
      Line 986, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 2305704668 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 2305704668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.pwrmgr_stress_all.25216206977773330181021278205452851286415570777460449111135348309256546644872
      Line 1520, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 1414291405 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 1414291405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 10.pwrmgr_stress_all_with_rand_reset.73223352002634637332307974995581057194034516189363342591980445930992847057894
      Line 2660, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3957941002 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 3957941002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 2 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 4.pwrmgr_stress_all_with_rand_reset.68594524359714358415445399067011233566444000412250310651572358017066416351441
      Line 582, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 2060543779 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 2060543779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all has 1 failures.

    • 35.pwrmgr_stress_all.47435689119815159667001617648108783579994316441285837103369904809461090079616
      Line 350, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 1252299246 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 1252299246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:

  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 17.pwrmgr_lowpower_invalid.702795329327624298208351346443143345873194689863634937750652437439533622331
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  43462530 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  43462530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:753) [pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 42.pwrmgr_stress_all_with_rand_reset.89806482521766722070195166079169601583541138061517682218863681850384311690357
      Line 7233, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4352801628 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 4352801628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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