PWRMGR Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	29.974us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	75.274us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	55.462us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.920s	76.640us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.080s	294.158us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.510s	88.543us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	55.462us	20	20	100.00
		pwrmgr_csr_aliasing	1.080s	294.158us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.330s	252.539us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.330s	252.539us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.290s	36.265us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	39.400us	50	50	100.00
V2	reset	pwrmgr_reset	1.040s	88.708us	49	50	98.00
		pwrmgr_reset_invalid	1.170s	108.232us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.040s	88.708us	49	50	98.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.680s	337.258us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.380s	304.034us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.950s	60.803us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.540s	2.517ms	46	50	92.00
V2	intr_test	pwrmgr_intr_test	0.690s	18.842us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.530s	156.343us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.530s	156.343us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	75.274us	5	5	100.00
		pwrmgr_csr_rw	0.720s	55.462us	20	20	100.00
		pwrmgr_csr_aliasing	1.080s	294.158us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	39.186us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	75.274us	5	5	100.00
		pwrmgr_csr_rw	0.720s	55.462us	20	20	100.00
		pwrmgr_csr_aliasing	1.080s	294.158us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	39.186us	20	20	100.00
V2		TOTAL			534	540	98.89
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.730s	193.931us	20	20	100.00
		pwrmgr_sec_cm	2.270s	706.181us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.270s	706.181us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.270s	706.181us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.730s	193.931us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.430s	932.249us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.620s	897.871us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.060s	69.138us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	30.809us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.270s	706.181us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.270s	706.181us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.270s	706.181us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.720s	99.604us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	29.980us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.660s	277.206us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	55.462us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	55.462us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.090s	169.541us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	35.960s	9.600ms	41	50	82.00
V3		TOTAL			91	100	91.00
		TOTAL			1105	1120	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 8 failures:

Test pwrmgr_stress_all_with_rand_reset has 5 failures.

0.pwrmgr_stress_all_with_rand_reset.53327110149363182519005854700405318047831163379299045420368267837849752963280
Line 1230, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2460816669 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 2460816669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.pwrmgr_stress_all_with_rand_reset.101018687157819324974160387385022890844441727605843322825669532947159304985416
Line 1376, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1846861739 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 1846861739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test pwrmgr_stress_all has 2 failures.

13.pwrmgr_stress_all.18126004726517730365152730904355798118217930015681171543371413708886193315199
Line 938, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 1247915436 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 1247915436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.pwrmgr_stress_all.113788088632344732364496737449343198941329042032382086883949443713664038473183
Line 464, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 534541210 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @ 534541210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwrmgr_reset has 1 failures.

17.pwrmgr_reset.42254518978512733531056853843576265393292544395354883000505499524172962949021
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_reset/latest/run.log

  UVM_ERROR @  23980426 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
  UVM_INFO @  23980426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 6 failures:
- Test pwrmgr_stress_all has 2 failures.
  - 4.pwrmgr_stress_all.86580642021252028371289678998490978812927398038674436353554343810995818815970
    Line 987, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1098067357 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 1098067357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.pwrmgr_stress_all.115651890763071155514746473473412478357028703903451750865564883964386008798345
    Line 688, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest/run.log
```
  UVM_ERROR @ 614546505 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 614546505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwrmgr_stress_all_with_rand_reset has 3 failures.
  - 9.pwrmgr_stress_all_with_rand_reset.99434721478203744405547067578082324328831349143971832570489947626806188818880
    Line 3629, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7227922019 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 7227922019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.pwrmgr_stress_all_with_rand_reset.39618146062158186074839045819322088677961626605332495591885998603602362234645
    Line 2155, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4605152178 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @ 4605152178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test pwrmgr_lowpower_wakeup_race has 1 failures.
  - 35.pwrmgr_lowpower_wakeup_race.36398115170745455710567040747209626170902029551808891139897530916890939845286
    Line 274, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest/run.log
```
  UVM_ERROR @  19939047 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
  UVM_INFO @  19939047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 20.pwrmgr_stress_all_with_rand_reset.50733448932050653921315975075660136672566844181810454740089504580678519772912
    Line 1516, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 7046418598 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 7046418598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```