PWRMGR Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	32.214us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.720s	62.164us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	23.313us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.500s	1.269ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.980s	24.546us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.170s	82.492us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	23.313us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	24.546us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.420s	275.553us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.420s	275.553us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.200s	35.084us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	42.903us	50	50	100.00
V2	reset	pwrmgr_reset	1.030s	79.302us	50	50	100.00
		pwrmgr_reset_invalid	1.220s	103.609us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.030s	79.302us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.550s	268.427us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.380s	278.509us	49	50	98.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.920s	65.412us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.260s	2.277ms	48	50	96.00
V2	intr_test	pwrmgr_intr_test	0.680s	19.941us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.390s	168.639us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.390s	168.639us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.720s	62.164us	5	5	100.00
		pwrmgr_csr_rw	0.700s	23.313us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	24.546us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	27.887us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.720s	62.164us	5	5	100.00
		pwrmgr_csr_rw	0.700s	23.313us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	24.546us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	27.887us	20	20	100.00
V2		TOTAL			537	540	99.44
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.770s	200.286us	20	20	100.00
		pwrmgr_sec_cm	2.090s	638.677us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.090s	638.677us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.090s	638.677us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.770s	200.286us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.490s	804.176us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.610s	906.489us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	77.364us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	29.063us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.090s	638.677us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.090s	638.677us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.090s	638.677us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.720s	49.444us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.740s	56.402us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.590s	291.050us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	23.313us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	23.313us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	611.847us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	38.860s	16.098ms	38	50	76.00
V3		TOTAL			87	100	87.00
		TOTAL			1104	1120	98.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 9 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 7 failures.

    • 5.pwrmgr_stress_all_with_rand_reset.97708965367794205586278876958906745655015767803531935754322304675019906172559
      Line 4084, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6287581030 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 6287581030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.pwrmgr_stress_all_with_rand_reset.72503502834673219061572781061201403561201549865941753604894317513397486782176
      Line 4598, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6122926074 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 6122926074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

  • Test pwrmgr_stress_all has 2 failures.

    • 28.pwrmgr_stress_all.65049539111764030169971448211644783423557780865941028993465661134516328892742
      Line 429, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 318378066 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 318378066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.pwrmgr_stress_all.40987951041827633469110523925745014469077266146451285401913218047598877236877
      Line 1004, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 1381630433 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 1381630433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 5 failures:

  • Test pwrmgr_lowpower_wakeup_race has 1 failures.

    • 6.pwrmgr_lowpower_wakeup_race.22035542505149188798113084430331855968949526254730025074850586616431036645969
      Line 318, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest/run.log

        UVM_ERROR @  46031497 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @  46031497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 4 failures.

    • 22.pwrmgr_stress_all_with_rand_reset.108111568680494792026036792581576569441589227743948697639352577247967469984974
      Line 1712, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5100803259 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 5100803259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.pwrmgr_stress_all_with_rand_reset.37696200341649404783193606235102583425976731250817030891475797615668044580017
      Line 1414, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2196926774 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 2196926774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:31) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 3.pwrmgr_escalation_timeout.54297132618662109978363515535325529864485145998199541359657437562056630431945
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 1726206053 ps: (pwrmgr_escalation_timeout_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 1726206053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_base_vseq.sv:608) [pwrmgr_reset_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 38.pwrmgr_stress_all_with_rand_reset.65519880770293486104669715421170970042269057551457228764116910619668223372841
      Line 2805, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 5380338528 ps: (pwrmgr_base_vseq.sv:608) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 5380338528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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