PWRMGR Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	30.196us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.650s	273.353us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	44.584us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.820s	74.912us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.980s	180.000us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.660s	59.265us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	44.584us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	180.000us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.330s	296.145us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.330s	296.145us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.970s	29.408us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	44.532us	50	50	100.00
V2	reset	pwrmgr_reset	1.030s	92.968us	50	50	100.00
		pwrmgr_reset_invalid	1.090s	98.094us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.030s	92.968us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.590s	318.402us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.410s	286.606us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.880s	67.123us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.740s	2.052ms	49	50	98.00
V2	intr_test	pwrmgr_intr_test	0.700s	44.800us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.550s	544.100us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.550s	544.100us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.650s	273.353us	5	5	100.00
		pwrmgr_csr_rw	0.710s	44.584us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	180.000us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	129.932us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.650s	273.353us	5	5	100.00
		pwrmgr_csr_rw	0.710s	44.584us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	180.000us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	129.932us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.770s	206.725us	20	20	100.00
		pwrmgr_sec_cm	2.120s	662.584us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.120s	662.584us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.120s	662.584us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.770s	206.725us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.470s	850.960us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.340s	893.372us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.000s	74.765us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.650s	29.882us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.120s	662.584us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.120s	662.584us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.120s	662.584us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	44.176us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.760s	61.089us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.410s	285.459us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	44.584us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	44.584us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.020s	313.091us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	31.340s	9.270ms	42	50	84.00
V3		TOTAL			92	100	92.00
		TOTAL			1111	1120	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_ERROR (pwrmgr_scoreboard.sv:251) [scoreboard] Check failed item.d_data[i] == exp_intr[i] (* [*] vs * [*]) Interrupt bit * has 6 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 5 failures.

    • 0.pwrmgr_stress_all_with_rand_reset.100495902345519133210526747976682010719520609414511042558322014937401621239754
      Line 7818, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19021122372 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 19021122372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.pwrmgr_stress_all_with_rand_reset.32881258602740215265104615578015855286564598969806193295822778265724258436751
      Line 2316, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3961109645 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 3961109645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

  • Test pwrmgr_stress_all has 1 failures.

    • 7.pwrmgr_stress_all.53059805565543691006038665324452985327844453346525941436103486260911283825121
      Line 848, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

        UVM_ERROR @ 1163575403 ps: (pwrmgr_scoreboard.sv:251) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == exp_intr[i] (1 [0x1] vs 0 [0x0]) Interrupt bit 0
        UVM_INFO @ 1163575403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 2 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 2 failures.

    • 36.pwrmgr_stress_all_with_rand_reset.65052902105499553322166150432800481577979159377530940139928539206166161438714
      Line 3772, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 20358997692 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 20358997692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 48.pwrmgr_stress_all_with_rand_reset.76321074670689890818894954670123660165288633980371753084659699019246761760493
      Line 2967, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 14853630242 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 14853630242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 38.pwrmgr_stress_all_with_rand_reset.76340015454350880035796236657922390627428989365930889455182555243288268124836
      Line 1097, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1093804842 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:0
        UVM_INFO @ 1093804842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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