PWRMGR Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.740s	29.748us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.730s	32.829us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.730s	26.679us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.320s	930.687us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	42.587us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.410s	433.484us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.730s	26.679us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	42.587us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.290s	261.748us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.290s	261.748us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.170s	38.297us	50	50	100.00
		pwrmgr_lowpower_invalid	0.890s	43.854us	50	50	100.00
V2	reset	pwrmgr_reset	1.030s	91.132us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	110.004us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.030s	91.132us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.470s	304.742us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.300s	273.778us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.870s	71.630us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.360s	2.986ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.700s	19.746us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.950s	491.971us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.950s	491.971us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.730s	32.829us	5	5	100.00
		pwrmgr_csr_rw	0.730s	26.679us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	42.587us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	52.861us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.730s	32.829us	5	5	100.00
		pwrmgr_csr_rw	0.730s	26.679us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	42.587us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	52.861us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.900s	197.105us	20	20	100.00
		pwrmgr_sec_cm	1.540s	749.166us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.540s	749.166us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.540s	749.166us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.900s	197.105us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.200s	839.120us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.430s	896.807us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	69.826us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.650s	29.320us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.540s	749.166us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.540s	749.166us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.540s	749.166us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	48.790us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	44.569us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.460s	302.168us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.730s	26.679us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.730s	26.679us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	escalation_timeout	pwrmgr_escalation_timeout	1.130s	316.919us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	40.310s	11.297ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	8	88.89
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• Offending '((!slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx]) || pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx])' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 4.pwrmgr_stress_all_with_rand_reset.16962494344890396346661903356986048473171438227047615293126444387730875886022
      Line 982, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((!slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx]) || pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx])'
        UVM_ERROR @ 2890497748 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
        UVM_INFO @ 2890497748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.

    • 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.58836197355418952578109118994055617427829330258088457126096724786257081086375
      Line 645, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

        UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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