PWRMGR Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	32.499us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	43.112us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.680s	31.205us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.600s	5.048ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.000s	45.511us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.340s	324.688us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.680s	31.205us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	45.511us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.320s	306.980us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.320s	306.980us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.010s	34.519us	50	50	100.00
		pwrmgr_lowpower_invalid	0.790s	41.574us	50	50	100.00
V2	reset	pwrmgr_reset	1.070s	81.441us	50	50	100.00
		pwrmgr_reset_invalid	1.100s	111.055us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.070s	81.441us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.570s	335.993us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.310s	291.205us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.880s	50.174us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.490s	1.473ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	31.684us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.000s	245.294us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.000s	245.294us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	43.112us	5	5	100.00
		pwrmgr_csr_rw	0.680s	31.205us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	45.511us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	32.710us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	43.112us	5	5	100.00
		pwrmgr_csr_rw	0.680s	31.205us	20	20	100.00
		pwrmgr_csr_aliasing	1.000s	45.511us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.950s	32.710us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.780s	195.662us	20	20	100.00
		pwrmgr_sec_cm	2.140s	624.049us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.140s	624.049us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.140s	624.049us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.780s	195.662us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.440s	854.762us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.580s	809.279us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	76.190us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	30.617us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.140s	624.049us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.140s	624.049us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.140s	624.049us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	51.828us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	42.636us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.500s	246.150us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.680s	31.205us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.680s	31.205us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.050s	159.460us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	34.310s	9.773ms	50	50	100.00
V3		TOTAL			99	100	99.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:
  • Test pwrmgr_escalation_timeout has 1 failures.

    • 47.pwrmgr_escalation_timeout.60989311102654618611184629123728871154777429108140692484104196389913117091614
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  96917790 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  96917790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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