PWRMGR Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	29.987us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	27.984us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.680s	22.882us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.460s	1.194ms	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.040s	68.863us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.360s	103.944us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.680s	22.882us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	68.863us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.380s	256.171us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.380s	256.171us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.090s	30.007us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	133.650us	50	50	100.00
V2	reset	pwrmgr_reset	1.000s	84.065us	50	50	100.00
		pwrmgr_reset_invalid	1.160s	100.574us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.000s	84.065us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.520s	284.105us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.320s	318.973us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.880s	69.974us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.210s	2.463ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.660s	21.381us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.490s	114.097us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.490s	114.097us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	27.984us	5	5	100.00
		pwrmgr_csr_rw	0.680s	22.882us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	68.863us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	156.197us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	27.984us	5	5	100.00
		pwrmgr_csr_rw	0.680s	22.882us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	68.863us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	156.197us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	2.470s	2.186ms	20	20	100.00
		pwrmgr_sec_cm	2.300s	670.173us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.300s	670.173us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.300s	670.173us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	2.470s	2.186ms	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.340s	786.187us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.400s	928.945us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.000s	79.283us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.660s	29.989us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.300s	670.173us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.300s	670.173us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.300s	670.173us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	38.118us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.700s	43.833us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.450s	297.931us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.680s	22.882us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.680s	22.882us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.060s	840.991us	49	50	98.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	32.490s	8.748ms	50	50	100.00
V3		TOTAL			99	100	99.00
		TOTAL			1119	1120	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	98.23	96.58	99.44	96.00	96.37	100.00	98.85

Failure Buckets

• Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:
  • Test pwrmgr_escalation_timeout has 1 failures.

    • 46.pwrmgr_escalation_timeout.112340830127161064265467710394492572866224767615769166039011856225559838180642
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest/run.log

            Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
        UVM_ERROR @  96092703 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
        UVM_INFO @  96092703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• dv
• 2024.05.24_04.52.05
• 2024.05.22_04.49.36
• 2024.05.20_04.22.26
• 2024.05.17_06.52.00
• 2024.05.15_03.18.44