PWRMGR Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	38.577us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	55.932us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	22.166us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.100s	679.745us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.070s	42.982us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.490s	82.745us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	22.166us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	42.982us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.300s	186.264us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.300s	186.264us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.000s	41.006us	50	50	100.00
		pwrmgr_lowpower_invalid	0.750s	43.909us	49	50	98.00
V2	reset	pwrmgr_reset	1.130s	90.228us	50	50	100.00
		pwrmgr_reset_invalid	1.140s	110.458us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.130s	90.228us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.600s	345.715us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.390s	299.495us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.910s	68.831us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	6.910s	1.965ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	23.467us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.510s	53.095us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.510s	53.095us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	55.932us	5	5	100.00
		pwrmgr_csr_rw	0.720s	22.166us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	42.982us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.040s	51.774us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	55.932us	5	5	100.00
		pwrmgr_csr_rw	0.720s	22.166us	20	20	100.00
		pwrmgr_csr_aliasing	1.070s	42.982us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.040s	51.774us	20	20	100.00
V2		TOTAL			538	540	99.63
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.710s	277.679us	20	20	100.00
		pwrmgr_sec_cm	2.230s	776.068us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.230s	776.068us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.230s	776.068us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.710s	277.679us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.530s	788.796us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	3.490s	911.877us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.040s	73.502us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.680s	38.257us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.230s	776.068us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.230s	776.068us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.230s	776.068us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	44.277us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	61.103us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.550s	328.286us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	22.166us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	22.166us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.080s	612.300us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	38.140s	10.951ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1118	1120	99.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	98.23	96.58	99.44	96.00	96.37	100.00	99.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_wakeup_reset has 1 failures.

    • 17.pwrmgr_wakeup_reset.80596085677721929212648903728286591936431182264364530894442947957343046279040
      Line 397, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:

  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 23.pwrmgr_lowpower_invalid.3444973785178426762531333577437570133959961888913728692470101913921567659289
      Line 251, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  38904874 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  38904874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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